1 | ------------------------------------------------------------------------------- |
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2 | -- |
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3 | -- SD/MMC Bootloader |
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4 | -- |
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5 | -- $Id: spi_boot.vhd 77 2009-04-01 19:53:14Z arniml $ |
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6 | -- |
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7 | -- Copyright (c) 2005, Arnim Laeuger (arniml@opencores.org) |
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8 | -- |
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9 | -- All rights reserved, see COPYING. |
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10 | -- |
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11 | -- Redistribution and use in source and synthezised forms, with or without |
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12 | -- modification, are permitted provided that the following conditions are met: |
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13 | -- |
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14 | -- Redistributions of source code must retain the above copyright notice, |
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15 | -- this list of conditions and the following disclaimer. |
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16 | -- |
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17 | -- Redistributions in synthesized form must reproduce the above copyright |
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18 | -- notice, this list of conditions and the following disclaimer in the |
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19 | -- documentation and/or other materials provided with the distribution. |
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20 | -- |
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21 | -- Neither the name of the author nor the names of other contributors may |
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22 | -- be used to endorse or promote products derived from this software without |
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23 | -- specific prior written permission. |
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24 | -- |
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25 | -- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
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26 | -- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, |
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27 | -- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR |
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28 | -- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE |
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29 | -- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
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30 | -- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
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31 | -- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
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32 | -- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
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33 | -- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
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34 | -- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
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35 | -- POSSIBILITY OF SUCH DAMAGE. |
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36 | -- |
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37 | -- Please report bugs to the author, but before you do so, please |
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38 | -- make sure that this is not a derivative work and that |
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39 | -- you have the latest version of this file. |
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40 | -- |
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41 | -- The latest version of this file can be found at: |
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42 | -- http://www.opencores.org/projects.cgi/web/spi_boot/overview |
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43 | -- |
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44 | ------------------------------------------------------------------------------- |
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45 | |
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46 | library ieee; |
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47 | use ieee.std_logic_1164.all; |
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48 | |
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49 | |
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50 | entity spi_boot is |
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51 | |
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52 | generic ( |
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53 | -- width of bit counter: minimum 6, maximum 12 |
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54 | width_bit_cnt_g : integer := 6; |
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55 | -- width of image counter: minimum 0, maximum n |
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56 | width_img_cnt_g : integer := 2; |
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57 | -- number of bits required to address one image |
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58 | num_bits_per_img_g : integer := 18; |
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59 | -- SD specific initialization |
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60 | sd_init_g : integer := 0; |
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61 | -- clock divider to reach 400 kHz for MMC compatibility |
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62 | mmc_compat_clk_div_g : integer := 0; |
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63 | width_mmc_clk_div_g : integer := 0; |
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64 | -- active level of reset_i |
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65 | reset_level_g : integer := 0 |
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66 | ); |
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67 | |
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68 | port ( |
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69 | -- System Interface ------------------------------------------------------- |
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70 | clk_i : in std_logic; |
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71 | reset_i : in std_logic; |
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72 | set_sel_i : in std_logic_vector(31-width_img_cnt_g-num_bits_per_img_g |
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73 | downto 0); |
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74 | -- Card Interface --------------------------------------------------------- |
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75 | spi_clk_o : out std_logic; |
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76 | spi_cs_n_o : out std_logic; |
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77 | spi_data_in_i : in std_logic; |
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78 | spi_data_out_o : out std_logic; |
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79 | spi_en_outs_o : out std_logic; |
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80 | -- FPGA Configuration Interface ------------------------------------------- |
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81 | start_i : in std_logic; |
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82 | mode_i : in std_logic; |
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83 | config_n_o : out std_logic; |
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84 | detached_o : out std_logic; |
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85 | cfg_init_n_i : in std_logic; |
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86 | cfg_done_i : in std_logic; |
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87 | dat_done_i : in std_logic; |
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88 | cfg_clk_o : out std_logic; |
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89 | cfg_dat_o : out std_logic |
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90 | ); |
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91 | |
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92 | end spi_boot; |
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93 | |
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94 | |
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95 | library ieee; |
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96 | use ieee.numeric_std.all; |
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97 | use work.spi_boot_pack.all; |
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98 | |
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99 | architecture rtl of spi_boot is |
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100 | |
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101 | component spi_counter |
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102 | generic ( |
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103 | cnt_width_g : integer := 4; |
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104 | cnt_max_g : integer := 15 |
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105 | ); |
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106 | port ( |
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107 | clk_i : in std_logic; |
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108 | reset_i : in boolean; |
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109 | cnt_en_i : in boolean; |
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110 | cnt_o : out std_logic_vector(cnt_width_g-1 downto 0); |
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111 | cnt_ovfl_o : out boolean |
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112 | ); |
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113 | end component; |
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114 | |
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115 | |
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116 | ----------------------------------------------------------------------------- |
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117 | -- States of the controller FSM |
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118 | -- |
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119 | type ctrl_states_t is (POWER_UP1, POWER_UP2, |
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120 | CMD0, |
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121 | CMD1, |
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122 | CMD55, ACMD41, |
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123 | CMD16, |
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124 | WAIT_START, |
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125 | WAIT_INIT_LOW, WAIT_INIT_HIGH, |
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126 | CMD18, CMD18_DATA, |
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127 | CMD12, |
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128 | INC_IMG_CNT); |
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129 | -- |
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130 | signal ctrl_fsm_q, |
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131 | ctrl_fsm_s : ctrl_states_t; |
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132 | -- |
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133 | ----------------------------------------------------------------------------- |
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134 | |
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135 | ----------------------------------------------------------------------------- |
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136 | -- States of the command FSM |
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137 | -- |
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138 | type cmd_states_t is (CMD, START, R1, PAUSE); |
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139 | -- |
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140 | signal cmd_fsm_q, |
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141 | cmd_fsm_s : cmd_states_t; |
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142 | -- |
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143 | ----------------------------------------------------------------------------- |
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144 | |
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145 | subtype op_r is integer range 5 downto 0; |
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146 | type res_bc_t is (NONE, RES_MAX, RES_47, RES_15, RES_7); |
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147 | signal bit_cnt_q : unsigned(width_bit_cnt_g-1 downto 0); |
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148 | signal res_bc_s : res_bc_t; |
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149 | signal upper_bitcnt_zero_s : boolean; |
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150 | |
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151 | signal cfg_dat_q : std_logic; |
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152 | |
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153 | signal spi_clk_q : std_logic; |
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154 | signal spi_clk_rising_q : boolean; |
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155 | signal spi_clk_falling_q : boolean; |
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156 | signal spi_dat_q, |
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157 | spi_dat_s : std_logic; |
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158 | signal spi_cs_n_q, |
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159 | spi_cs_n_s : std_logic; |
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160 | |
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161 | signal cfg_clk_q : std_logic; |
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162 | |
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163 | signal start_q : std_logic; |
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164 | |
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165 | signal img_cnt_s : std_logic_vector(width_img_cnt_g downto 0); |
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166 | signal cnt_en_img_s : boolean; |
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167 | signal mmc_cnt_ovfl_s : boolean; |
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168 | signal mmc_compat_s : boolean; |
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169 | |
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170 | signal cmd_finished_s : boolean; |
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171 | |
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172 | signal r1_illcmd_q, |
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173 | r1_idle_q : std_logic; |
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174 | signal done_q, |
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175 | send_cmd12_q : boolean; |
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176 | |
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177 | signal en_outs_s, |
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178 | en_outs_q : boolean; |
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179 | |
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180 | signal reset_s : boolean; |
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181 | |
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182 | signal true_s : boolean; |
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183 | |
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184 | begin |
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185 | |
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186 | true_s <= true; |
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187 | |
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188 | reset_s <= true |
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189 | when (reset_level_g = 1 and reset_i = '1') or |
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190 | (reset_level_g = 0 and reset_i = '0') else |
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191 | false; |
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192 | |
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193 | ----------------------------------------------------------------------------- |
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194 | -- Process seq |
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195 | -- |
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196 | -- Purpose: |
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197 | -- Implements several sequential elements. |
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198 | -- |
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199 | seq: process (clk_i, reset_s) |
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200 | |
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201 | variable bit_cnt_v : unsigned(1 downto 0); |
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202 | |
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203 | begin |
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204 | if reset_s then |
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205 | -- reset bit counter to 63 for power up |
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206 | bit_cnt_q <= (others => '0'); |
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207 | bit_cnt_q(op_r) <= "111111"; |
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208 | spi_dat_q <= '1'; |
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209 | spi_cs_n_q <= '1'; |
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210 | cfg_dat_q <= '1'; |
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211 | start_q <= '0'; |
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212 | done_q <= false; |
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213 | send_cmd12_q <= false; |
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214 | ctrl_fsm_q <= POWER_UP1; |
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215 | cmd_fsm_q <= CMD; |
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216 | r1_illcmd_q <= '0'; |
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217 | r1_idle_q <= '0'; |
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218 | en_outs_q <= false; |
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219 | |
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220 | elsif clk_i'event and clk_i = '1' then |
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221 | -- bit counter control |
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222 | if spi_clk_rising_q then |
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223 | case res_bc_s is |
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224 | when NONE => |
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225 | bit_cnt_q <= bit_cnt_q - 1; |
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226 | when RES_MAX => |
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227 | bit_cnt_q <= (others => '1'); |
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228 | when RES_47 => |
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229 | bit_cnt_q <= (others => '0'); |
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230 | bit_cnt_q(op_r) <= "101111"; |
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231 | when RES_15 => |
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232 | bit_cnt_q <= (others => '0'); |
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233 | bit_cnt_q(op_r) <= "001111"; |
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234 | when RES_7 => |
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235 | bit_cnt_q <= (others => '0'); |
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236 | bit_cnt_q(op_r) <= "000111"; |
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237 | when others => |
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238 | bit_cnt_q <= (others => '0'); |
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239 | end case; |
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240 | end if; |
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241 | |
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242 | -- Card data output register |
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243 | -- spi_clk_falling_q acts as enable during MMC clock compatibility mode. |
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244 | -- As soon as this mode is left, the register must start latching. |
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245 | -- There is no explicit relation to spi_clk_q anymore in normal mode. |
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246 | -- Instead, spi_dat_s is operated by bit_cnt_q above which changes its |
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247 | -- value after the rising edge of spi_clk_q. |
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248 | -- -> spi_dat_q changes upon falling edge of spi_clk_q |
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249 | if spi_clk_falling_q or not mmc_compat_s then |
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250 | spi_dat_q <= spi_dat_s; |
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251 | end if; |
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252 | |
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253 | -- config data output register |
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254 | -- a new value is loaded when config clock is high, |
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255 | -- i.e. input data is sampled with rising spi_clk |
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256 | -- while output value changes on falling edge of cfg_clk |
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257 | if cfg_clk_q = '1' and spi_clk_rising_q then |
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258 | cfg_dat_q <= spi_data_in_i; |
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259 | end if; |
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260 | |
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261 | -- Controller FSM state |
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262 | ctrl_fsm_q <= ctrl_fsm_s; |
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263 | |
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264 | -- Command FSM state |
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265 | cmd_fsm_q <= cmd_fsm_s; |
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266 | |
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267 | -- CS signal for SPI card |
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268 | if spi_clk_q = '1' then |
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269 | spi_cs_n_q <= spi_cs_n_s; |
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270 | end if; |
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271 | |
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272 | -- Extract flags from R1 response |
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273 | if cmd_fsm_q = R1 then |
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274 | bit_cnt_v := bit_cnt_q(1 downto 0); |
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275 | case bit_cnt_v(1 downto 0) is |
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276 | when "10" => |
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277 | -- save "Illegal Command" flag |
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278 | r1_illcmd_q <= to_X01(spi_data_in_i); |
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279 | when "00" => |
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280 | -- save "Idle State" flag |
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281 | r1_idle_q <= to_X01(spi_data_in_i); |
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282 | when others => |
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283 | null; |
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284 | end case; |
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285 | end if; |
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286 | |
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287 | -- Start trigger register for rising edge detection |
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288 | -- the reset value is '0' thus a rising edge will always be detected |
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289 | -- after reset even though start_i is tied to '1' |
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290 | if start_i = '0' then |
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291 | start_q <= '0'; |
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292 | elsif ctrl_fsm_q = WAIT_START and cmd_finished_s then |
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293 | start_q <= start_i; |
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294 | end if; |
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295 | |
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296 | -- Marker for cfg_done and dat_done |
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297 | if ctrl_fsm_q = CMD18_DATA then |
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298 | if cfg_done_i = '1' and dat_done_i = '1' then |
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299 | done_q <= true; |
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300 | end if; |
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301 | |
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302 | if done_q and |
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303 | (not upper_bitcnt_zero_s or cmd_fsm_q = START) then |
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304 | -- activate sending of CMD12 when it is safe: |
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305 | -- * upper bits of bit counter are not zero |
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306 | -- -> transmission of CMD12 is not running |
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307 | -- * cmd FSM is in START state |
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308 | -- -> also no transmission running |
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309 | send_cmd12_q <= true; |
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310 | end if; |
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311 | elsif ctrl_fsm_q = WAIT_START then |
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312 | -- reset done_q when WAIT_START has been reached |
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313 | -- this is necessary to let the stop transmission process come to |
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314 | -- an end without interruption or generation of unwanted cfg_clk_q |
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315 | done_q <= false; |
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316 | send_cmd12_q <= false; |
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317 | end if; |
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318 | |
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319 | -- output enable |
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320 | if spi_clk_rising_q then |
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321 | en_outs_q <= en_outs_s; |
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322 | end if; |
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323 | |
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324 | end if; |
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325 | |
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326 | end process seq; |
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327 | -- |
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328 | ----------------------------------------------------------------------------- |
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329 | |
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330 | |
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331 | ----------------------------------------------------------------------------- |
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332 | -- Process upper_bits |
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333 | -- |
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334 | -- Purpose: |
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335 | -- Detects that the upper bits of the bit counter are zero. |
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336 | -- Upper bits = n downto 6, i.e. the optional part that is not required for |
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337 | -- commands but for extension of data blocks. |
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338 | -- |
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339 | upper_bits: process (bit_cnt_q) |
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340 | variable zero_v : boolean; |
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341 | begin |
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342 | |
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343 | zero_v := true; |
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344 | for i in bit_cnt_q'high downto 6 loop |
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345 | if bit_cnt_q(i) = '1' then |
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346 | zero_v := false; |
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347 | end if; |
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348 | end loop; |
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349 | |
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350 | upper_bitcnt_zero_s <= zero_v; |
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351 | |
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352 | end process upper_bits; |
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353 | -- |
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354 | ----------------------------------------------------------------------------- |
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355 | |
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356 | |
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357 | ----------------------------------------------------------------------------- |
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358 | -- Process clk_gen |
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359 | -- |
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360 | -- Purpose: |
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361 | -- Generates clocks for card and FPGA configuration. |
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362 | -- The card clock is free running with a divide by two of clk_i. |
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363 | -- The clock for FPGA config has an enable and is stopped on high level. |
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364 | -- There is a phase shift of half a period between spi_clk and cfg_clk. |
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365 | -- |
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366 | clk_gen: process (clk_i, reset_s) |
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367 | begin |
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368 | if reset_s then |
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369 | spi_clk_q <= '0'; |
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370 | cfg_clk_q <= '1'; |
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371 | |
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372 | elsif clk_i'event and clk_i = '1' then |
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373 | |
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374 | -- spi_clk_q rises according to the flag |
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375 | -- it falls with overflow indication |
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376 | -- the resulting duty cycle is not exactly 50:50, |
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377 | -- high time is a bit longer |
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378 | if mmc_compat_s then |
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379 | -- MMC clock compatibility mode: |
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380 | -- spi_clk_q rises when flagged by spi_clk_rising_q |
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381 | if spi_clk_rising_q then |
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382 | spi_clk_q <= '1'; |
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383 | elsif mmc_cnt_ovfl_s then |
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384 | -- upon counter overflow spi_clk_q falls in case it does not rise |
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385 | spi_clk_q <= '0'; |
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386 | end if; |
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387 | else |
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388 | -- normal mode |
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389 | -- spi_clk_q follows spi_clk_rising_q |
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390 | if spi_clk_rising_q then |
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391 | spi_clk_q <= '1'; |
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392 | else |
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393 | spi_clk_q <= '0'; |
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394 | end if; |
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395 | end if; |
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396 | |
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397 | -- clock for FPGA config must be enabled and follows spi_clk |
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398 | if ctrl_fsm_q = CMD18_DATA and cmd_fsm_q = CMD and |
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399 | not done_q then |
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400 | cfg_clk_q <= spi_clk_q; |
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401 | else |
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402 | cfg_clk_q <= '1'; |
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403 | end if; |
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404 | |
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405 | end if; |
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406 | |
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407 | end process clk_gen; |
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408 | -- |
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409 | ----------------------------------------------------------------------------- |
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410 | |
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411 | |
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412 | ----------------------------------------------------------------------------- |
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413 | -- Indication flags for rising and falling spi_clk_q. |
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414 | -- Essential for MMC clock compatibility mode. |
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415 | ----------------------------------------------------------------------------- |
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416 | mmc_comap: if mmc_compat_clk_div_g > 0 generate |
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417 | mmc_compat_sig: process (clk_i, reset_s) |
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418 | begin |
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419 | if reset_s then |
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420 | spi_clk_rising_q <= false; |
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421 | spi_clk_falling_q <= false; |
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422 | |
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423 | elsif clk_i'event and clk_i = '1' then |
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424 | if mmc_compat_s then |
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425 | -- MMC clock compatibility mode: |
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426 | -- spi_clk_rising_q is an impulse right before rising edge of spi_clk_q |
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427 | -- spi_clk_falling_q is an impulse right before falling edge of spi_clk_q |
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428 | if mmc_cnt_ovfl_s then |
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429 | spi_clk_rising_q <= spi_clk_q = '0'; |
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430 | spi_clk_falling_q <= spi_clk_q = '1'; |
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431 | else |
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432 | spi_clk_rising_q <= false; |
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433 | spi_clk_falling_q <= false; |
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434 | end if; |
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435 | else |
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436 | -- normal mode |
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437 | spi_clk_rising_q <= not spi_clk_rising_q; |
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438 | spi_clk_falling_q <= true; |
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439 | end if; |
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440 | |
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441 | end if; |
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442 | end process mmc_compat_sig; |
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443 | end generate; |
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444 | |
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445 | no_mmc_compat: if mmc_compat_clk_div_g = 0 generate |
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446 | -- SPI clock rising whenever spi_clk_q is '0' |
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447 | spi_clk_rising_q <= spi_clk_q = '0'; |
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448 | -- SPI clock falling whenever spi_clk_q is '1' |
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449 | spi_clk_falling_q <= spi_clk_q = '1'; |
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450 | end generate; |
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451 | |
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452 | |
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453 | ----------------------------------------------------------------------------- |
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454 | -- Process ctrl_fsm |
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455 | -- |
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456 | -- Purpose: |
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457 | -- Implements the controller FSM. |
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458 | -- |
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459 | ctrl_fsm: process (ctrl_fsm_q, |
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460 | cmd_finished_s, r1_illcmd_q, r1_idle_q, |
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461 | start_i, start_q, mode_i, |
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462 | cfg_init_n_i) |
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463 | |
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464 | variable mmc_compat_v : boolean; |
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465 | |
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466 | begin |
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467 | -- default assignments |
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468 | ctrl_fsm_s <= POWER_UP1; |
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469 | config_n_o <= '1'; |
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470 | cnt_en_img_s <= false; |
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471 | spi_cs_n_s <= '0'; |
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472 | mmc_compat_v := false; |
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473 | en_outs_s <= true; |
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474 | |
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475 | case ctrl_fsm_q is |
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476 | -- Let card finish power up, step 1 ------------------------------------- |
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477 | when POWER_UP1 => |
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478 | mmc_compat_v := true; |
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479 | spi_cs_n_s <= '1'; |
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480 | if cmd_finished_s then |
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481 | ctrl_fsm_s <= POWER_UP2; |
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482 | else |
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483 | ctrl_fsm_s <= POWER_UP1; |
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484 | end if; |
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485 | |
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486 | |
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487 | -- Let card finish power up, step 2 ------------------------------------- |
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488 | when POWER_UP2 => |
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489 | mmc_compat_v := true; |
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490 | if cmd_finished_s then |
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491 | ctrl_fsm_s <= CMD0; |
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492 | else |
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493 | spi_cs_n_s <= '1'; |
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494 | ctrl_fsm_s <= POWER_UP2; |
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495 | end if; |
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496 | |
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497 | |
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498 | -- Issue CMD0: GO_IDLE_STATE -------------------------------------------- |
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499 | when CMD0 => |
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500 | mmc_compat_v := true; |
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501 | if cmd_finished_s then |
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502 | if sd_init_g = 1 then |
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503 | ctrl_fsm_s <= CMD55; |
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504 | else |
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505 | ctrl_fsm_s <= CMD1; |
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506 | end if; |
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507 | else |
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508 | ctrl_fsm_s <= CMD0; |
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509 | end if; |
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510 | |
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511 | |
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512 | -- Issue CMD55: APP_CMD ------------------------------------------------- |
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513 | when CMD55 => |
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514 | if sd_init_g = 1 then |
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515 | |
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516 | mmc_compat_v := true; |
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517 | if cmd_finished_s then |
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518 | if r1_illcmd_q = '0' then |
---|
519 | -- command accepted, continue with ACMD41 |
---|
520 | ctrl_fsm_s <= ACMD41; |
---|
521 | else |
---|
522 | -- command rejected, it's an MMC card |
---|
523 | ctrl_fsm_s <= CMD1; |
---|
524 | end if; |
---|
525 | else |
---|
526 | ctrl_fsm_s <= CMD55; |
---|
527 | end if; |
---|
528 | |
---|
529 | end if; |
---|
530 | |
---|
531 | |
---|
532 | -- Issue ACMD41: SEND_OP_COND ------------------------------------------- |
---|
533 | when ACMD41 => |
---|
534 | if sd_init_g = 1 then |
---|
535 | |
---|
536 | mmc_compat_v := true; |
---|
537 | if cmd_finished_s then |
---|
538 | if r1_illcmd_q = '0' then |
---|
539 | -- ok, that's an SD card |
---|
540 | if r1_idle_q = '0' then |
---|
541 | ctrl_fsm_s <= CMD16; |
---|
542 | else |
---|
543 | ctrl_fsm_s <= CMD55; |
---|
544 | end if; |
---|
545 | |
---|
546 | else |
---|
547 | -- command rejected, though it accepted CMD55 -> it's an MMC |
---|
548 | ctrl_fsm_s <= CMD1; |
---|
549 | end if; |
---|
550 | |
---|
551 | else |
---|
552 | ctrl_fsm_s <= ACMD41; |
---|
553 | end if; |
---|
554 | |
---|
555 | end if; |
---|
556 | |
---|
557 | |
---|
558 | -- Issue CMD1: SEND_OP_COND --------------------------------------------- |
---|
559 | when CMD1 => |
---|
560 | mmc_compat_v := true; |
---|
561 | if cmd_finished_s then |
---|
562 | if r1_idle_q = '0' then |
---|
563 | ctrl_fsm_s <= CMD16; |
---|
564 | else |
---|
565 | ctrl_fsm_s <= CMD1; |
---|
566 | end if; |
---|
567 | else |
---|
568 | ctrl_fsm_s <= CMD1; |
---|
569 | end if; |
---|
570 | |
---|
571 | |
---|
572 | -- Issue CMD16: SET_BLOCKLEN -------------------------------------------- |
---|
573 | when CMD16 => |
---|
574 | if cmd_finished_s then |
---|
575 | ctrl_fsm_s <= WAIT_START; |
---|
576 | else |
---|
577 | ctrl_fsm_s <= CMD16; |
---|
578 | end if; |
---|
579 | |
---|
580 | |
---|
581 | -- Wait for configuration start request --------------------------------- |
---|
582 | when WAIT_START => |
---|
583 | spi_cs_n_s <= '1'; |
---|
584 | |
---|
585 | --POM 2012-06-23: Adding de-assertion of PROG |
---|
586 | config_n_o <= '1'; |
---|
587 | |
---|
588 | -- detect rising edge of start_i |
---|
589 | if start_i = '1' and start_q = '0' then |
---|
590 | -- decide which mode is requested |
---|
591 | if cmd_finished_s then |
---|
592 | if mode_i = '0' then |
---|
593 | ctrl_fsm_s <= CMD18; |
---|
594 | else |
---|
595 | ctrl_fsm_s <= WAIT_INIT_LOW; |
---|
596 | end if; |
---|
597 | else |
---|
598 | en_outs_s <= false; |
---|
599 | ctrl_fsm_s <= WAIT_START; |
---|
600 | end if; |
---|
601 | else |
---|
602 | en_outs_s <= false; |
---|
603 | ctrl_fsm_s <= WAIT_START; |
---|
604 | end if; |
---|
605 | |
---|
606 | |
---|
607 | -- Wait for INIT to become low ------------------------------------------ |
---|
608 | when WAIT_INIT_LOW => |
---|
609 | spi_cs_n_s <= '1'; |
---|
610 | -- activate FPGA configuration |
---|
611 | config_n_o <= '0'; |
---|
612 | |
---|
613 | if cfg_init_n_i = '0' then |
---|
614 | ctrl_fsm_s <= WAIT_INIT_HIGH; |
---|
615 | else |
---|
616 | ctrl_fsm_s <= WAIT_INIT_LOW; |
---|
617 | end if; |
---|
618 | |
---|
619 | |
---|
620 | -- Wait for INIT to become high ----------------------------------------- |
---|
621 | when WAIT_INIT_HIGH => |
---|
622 | spi_cs_n_s <= '1'; |
---|
623 | |
---|
624 | --POM 2012-06-23: Adding de-assertion of PROG |
---|
625 | config_n_o <= '1'; |
---|
626 | |
---|
627 | if cfg_init_n_i = '1' and cmd_finished_s then |
---|
628 | ctrl_fsm_s <= CMD18; |
---|
629 | else |
---|
630 | ctrl_fsm_s <= WAIT_INIT_HIGH; |
---|
631 | end if; |
---|
632 | |
---|
633 | |
---|
634 | -- Issue CMD18: READ_MULTIPLE_BLOCKS ------------------------------------ |
---|
635 | when CMD18 => |
---|
636 | if cmd_finished_s then |
---|
637 | ctrl_fsm_s <= CMD18_DATA; |
---|
638 | else |
---|
639 | ctrl_fsm_s <= CMD18; |
---|
640 | end if; |
---|
641 | -- |
---|
642 | -- receive a data block |
---|
643 | when CMD18_DATA => |
---|
644 | if cmd_finished_s then |
---|
645 | ctrl_fsm_s <= CMD12; |
---|
646 | else |
---|
647 | ctrl_fsm_s <= CMD18_DATA; |
---|
648 | end if; |
---|
649 | |
---|
650 | |
---|
651 | -- Issued CMD12: STOP_TRANSMISSION ------------------------------------- |
---|
652 | when CMD12 => |
---|
653 | if cmd_finished_s then |
---|
654 | ctrl_fsm_s <= INC_IMG_CNT; |
---|
655 | else |
---|
656 | ctrl_fsm_s <= CMD12; |
---|
657 | end if; |
---|
658 | |
---|
659 | |
---|
660 | -- Increment Image Counter ---------------------------------------------- |
---|
661 | when INC_IMG_CNT => |
---|
662 | spi_cs_n_s <= '1'; |
---|
663 | ctrl_fsm_s <= WAIT_START; |
---|
664 | cnt_en_img_s <= true; |
---|
665 | |
---|
666 | |
---|
667 | |
---|
668 | when others => |
---|
669 | null; |
---|
670 | |
---|
671 | end case; |
---|
672 | |
---|
673 | -- mmc_compat_s is suppressed if MMC clock compatibility is not required |
---|
674 | if mmc_compat_clk_div_g > 0 then |
---|
675 | mmc_compat_s <= mmc_compat_v; |
---|
676 | else |
---|
677 | mmc_compat_s <= false; |
---|
678 | end if; |
---|
679 | |
---|
680 | end process ctrl_fsm; |
---|
681 | -- |
---|
682 | ----------------------------------------------------------------------------- |
---|
683 | |
---|
684 | |
---|
685 | ----------------------------------------------------------------------------- |
---|
686 | -- Process cmd_fsm |
---|
687 | -- |
---|
688 | -- Purpose: |
---|
689 | -- Implements the command FSM. |
---|
690 | -- |
---|
691 | cmd_fsm: process (spi_clk_rising_q, |
---|
692 | spi_data_in_i, |
---|
693 | bit_cnt_q, |
---|
694 | ctrl_fsm_q, |
---|
695 | cmd_fsm_q, |
---|
696 | send_cmd12_q) |
---|
697 | |
---|
698 | variable cnt_zero_v : boolean; |
---|
699 | variable spi_data_low_v : boolean; |
---|
700 | variable no_startbit_v : boolean; |
---|
701 | |
---|
702 | begin |
---|
703 | -- default assignments |
---|
704 | cmd_finished_s <= false; |
---|
705 | cmd_fsm_s <= CMD; |
---|
706 | res_bc_s <= NONE; |
---|
707 | |
---|
708 | cnt_zero_v := spi_clk_rising_q and bit_cnt_q = 0; |
---|
709 | spi_data_low_v := spi_clk_rising_q and spi_data_in_i = '0'; |
---|
710 | |
---|
711 | -- these are no real commands thus there will be no startbit |
---|
712 | case ctrl_fsm_q is |
---|
713 | when POWER_UP1 | POWER_UP2 | |
---|
714 | WAIT_START | WAIT_INIT_HIGH | WAIT_INIT_LOW => |
---|
715 | no_startbit_v := true; |
---|
716 | when others => |
---|
717 | no_startbit_v := false; |
---|
718 | end case; |
---|
719 | |
---|
720 | |
---|
721 | case cmd_fsm_q is |
---|
722 | -- Send the command ----------------------------------------------------- |
---|
723 | when CMD => |
---|
724 | if cnt_zero_v then |
---|
725 | if ctrl_fsm_q /= CMD18_DATA then |
---|
726 | -- normal commands including CMD12 require startbit of R1 response |
---|
727 | cmd_fsm_s <= START; |
---|
728 | else |
---|
729 | if not send_cmd12_q then |
---|
730 | -- CMD18_DATA needs to read CRC |
---|
731 | cmd_fsm_s <= R1; |
---|
732 | res_bc_s <= RES_15; |
---|
733 | else |
---|
734 | -- CMD18_DATA finished, scan for startbit of response |
---|
735 | cmd_finished_s <= true; |
---|
736 | cmd_fsm_s <= START; |
---|
737 | end if; |
---|
738 | end if; |
---|
739 | else |
---|
740 | cmd_fsm_s <= CMD; |
---|
741 | end if; |
---|
742 | |
---|
743 | -- Wait for startbit of response ---------------------------------------- |
---|
744 | when START => |
---|
745 | -- startbit detection or skip of this check |
---|
746 | if no_startbit_v and spi_clk_rising_q then |
---|
747 | cmd_fsm_s <= R1; |
---|
748 | res_bc_s <= RES_7; |
---|
749 | elsif spi_data_low_v then |
---|
750 | if ctrl_fsm_q /= CMD18_DATA then |
---|
751 | cmd_fsm_s <= R1; |
---|
752 | else |
---|
753 | -- CMD18_DATA startbit detected, read payload |
---|
754 | cmd_fsm_s <= CMD; |
---|
755 | res_bc_s <= RES_MAX; |
---|
756 | end if; |
---|
757 | else |
---|
758 | cmd_fsm_s <= START; |
---|
759 | res_bc_s <= RES_7; |
---|
760 | end if; |
---|
761 | |
---|
762 | -- Read R1 response ----------------------------------------------------- |
---|
763 | when R1 => |
---|
764 | if cnt_zero_v then |
---|
765 | res_bc_s <= RES_7; |
---|
766 | |
---|
767 | if not (ctrl_fsm_q = CMD18 or ctrl_fsm_q = CMD18_DATA) then |
---|
768 | cmd_fsm_s <= PAUSE; |
---|
769 | else |
---|
770 | -- CMD18 needs another startbit detection for the data token. |
---|
771 | -- CMD18_DATA needs a startbit after having received the CRC, either |
---|
772 | -- * next data token |
---|
773 | -- * R1 response of CMD12 |
---|
774 | cmd_fsm_s <= START; |
---|
775 | |
---|
776 | if ctrl_fsm_q = CMD18 then |
---|
777 | -- CMD18 response received -> advance to CMD18_DATA |
---|
778 | cmd_finished_s <= true; |
---|
779 | end if; |
---|
780 | end if; |
---|
781 | else |
---|
782 | cmd_fsm_s <= R1; |
---|
783 | end if; |
---|
784 | |
---|
785 | -- PAUSE state -> required for Nrc, card response to host command ------- |
---|
786 | when PAUSE => |
---|
787 | if cnt_zero_v then |
---|
788 | cmd_fsm_s <= CMD; |
---|
789 | res_bc_s <= RES_47; |
---|
790 | cmd_finished_s <= true; |
---|
791 | else |
---|
792 | cmd_fsm_s <= PAUSE; |
---|
793 | end if; |
---|
794 | |
---|
795 | when others => |
---|
796 | null; |
---|
797 | |
---|
798 | end case; |
---|
799 | |
---|
800 | end process cmd_fsm; |
---|
801 | -- |
---|
802 | ----------------------------------------------------------------------------- |
---|
803 | |
---|
804 | |
---|
805 | ----------------------------------------------------------------------------- |
---|
806 | -- Process transmit |
---|
807 | -- |
---|
808 | -- Purpose: |
---|
809 | -- Generates the serial data output values based on the current FSM state |
---|
810 | -- |
---|
811 | -- The local variable cmd_v is 64 bits wide in contrast to an SPI command |
---|
812 | -- with 48 bits. There are two reasons for this: |
---|
813 | -- * During "overlaid" sending of CMD12 in FSM state CMD18_DATA, the bit |
---|
814 | -- counter will start from 3F on its lowest 6 bits. Therefore, it is |
---|
815 | -- necessary to provide all 64 positions in cmd_v. |
---|
816 | -- * Reduces logic. |
---|
817 | -- |
---|
818 | transmit: process (ctrl_fsm_q, |
---|
819 | cmd_fsm_q, |
---|
820 | bit_cnt_q, |
---|
821 | img_cnt_s, |
---|
822 | send_cmd12_q, |
---|
823 | set_sel_i, |
---|
824 | upper_bitcnt_zero_s) |
---|
825 | |
---|
826 | subtype cmd_r is natural range 47 downto 0; |
---|
827 | subtype cmd_t is std_logic_vector(cmd_r); |
---|
828 | subtype ext_cmd_t is std_logic_vector(63 downto 0); |
---|
829 | -- STCCCCCCAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAcccccccS |
---|
830 | constant cmd0_c : cmd_t := "010000000000000000000000000000000000000010010101"; |
---|
831 | constant cmd1_c : cmd_t := "0100000100000000000000000000000000000000-------1"; |
---|
832 | constant cmd12_c : cmd_t := "0100110000000000000000000000000000000000-------1"; |
---|
833 | constant cmd16_c : cmd_t := "0101000000000000000000000000000000000000-------1"; |
---|
834 | constant cmd18_c : cmd_t := "0101001000000000000000000000000000000000-------1"; |
---|
835 | constant cmd55_c : cmd_t := "0111011100000000000000000000000000000000-------1"; |
---|
836 | constant acmd41_c : cmd_t := "0110100100000000000000000000000000000000-------1"; |
---|
837 | |
---|
838 | variable cmd_v : ext_cmd_t; |
---|
839 | variable tx_v : boolean; |
---|
840 | |
---|
841 | begin |
---|
842 | -- default assignments |
---|
843 | spi_dat_s <= '1'; |
---|
844 | cmd_v := (others => '1'); |
---|
845 | tx_v := false; |
---|
846 | |
---|
847 | if cmd_fsm_q = CMD then |
---|
848 | case ctrl_fsm_q is |
---|
849 | when CMD0 => |
---|
850 | cmd_v(cmd_r) := cmd0_c; |
---|
851 | tx_v := true; |
---|
852 | when CMD1 => |
---|
853 | cmd_v(cmd_r) := cmd1_c; |
---|
854 | tx_v := true; |
---|
855 | when CMD16 => |
---|
856 | cmd_v(cmd_r) := cmd16_c; |
---|
857 | cmd_v(8 + width_bit_cnt_g-3) := '1'; |
---|
858 | tx_v := true; |
---|
859 | when CMD18 => |
---|
860 | cmd_v(cmd_r) := cmd18_c; |
---|
861 | -- insert image counter |
---|
862 | cmd_v(8 + num_bits_per_img_g + width_img_cnt_g |
---|
863 | downto 8 + num_bits_per_img_g) := img_cnt_s; |
---|
864 | -- insert set selection |
---|
865 | cmd_v(8 + 31 |
---|
866 | downto 8 + num_bits_per_img_g + width_img_cnt_g) := set_sel_i; |
---|
867 | tx_v := true; |
---|
868 | when CMD18_DATA => |
---|
869 | cmd_v(cmd_r) := cmd12_c; |
---|
870 | |
---|
871 | if send_cmd12_q and upper_bitcnt_zero_s then |
---|
872 | tx_v := true; |
---|
873 | end if; |
---|
874 | when CMD55 => |
---|
875 | cmd_v(cmd_r) := cmd55_c; |
---|
876 | tx_v := true; |
---|
877 | when ACMD41 => |
---|
878 | cmd_v(cmd_r) := acmd41_c; |
---|
879 | tx_v := true; |
---|
880 | |
---|
881 | when others => |
---|
882 | null; |
---|
883 | end case; |
---|
884 | end if; |
---|
885 | |
---|
886 | if tx_v then |
---|
887 | spi_dat_s <= cmd_v(to_integer(bit_cnt_q(5 downto 0))); |
---|
888 | end if; |
---|
889 | |
---|
890 | end process transmit; |
---|
891 | -- |
---|
892 | ----------------------------------------------------------------------------- |
---|
893 | |
---|
894 | |
---|
895 | ----------------------------------------------------------------------------- |
---|
896 | -- Optional Image Counter |
---|
897 | ----------------------------------------------------------------------------- |
---|
898 | img_cnt: if width_img_cnt_g > 0 generate |
---|
899 | img_cnt_b : spi_counter |
---|
900 | generic map ( |
---|
901 | cnt_width_g => width_img_cnt_g, |
---|
902 | cnt_max_g => 2**width_img_cnt_g - 1 |
---|
903 | ) |
---|
904 | port map ( |
---|
905 | clk_i => clk_i, |
---|
906 | reset_i => reset_s, |
---|
907 | cnt_en_i => cnt_en_img_s, |
---|
908 | cnt_o => img_cnt_s(width_img_cnt_g-1 downto 0), |
---|
909 | cnt_ovfl_o => open |
---|
910 | ); |
---|
911 | img_cnt_s(width_img_cnt_g) <= '0'; |
---|
912 | end generate; |
---|
913 | |
---|
914 | no_img_cnt: if width_img_cnt_g = 0 generate |
---|
915 | img_cnt_s <= (others => '0'); |
---|
916 | end generate; |
---|
917 | |
---|
918 | |
---|
919 | ----------------------------------------------------------------------------- |
---|
920 | -- Optional MMC compatibility counter |
---|
921 | ----------------------------------------------------------------------------- |
---|
922 | mmc_cnt: if mmc_compat_clk_div_g > 0 generate |
---|
923 | mmc_cnt_b : spi_counter |
---|
924 | generic map ( |
---|
925 | cnt_width_g => width_mmc_clk_div_g, |
---|
926 | cnt_max_g => mmc_compat_clk_div_g |
---|
927 | ) |
---|
928 | port map ( |
---|
929 | clk_i => clk_i, |
---|
930 | reset_i => reset_s, |
---|
931 | cnt_en_i => true_s, |
---|
932 | cnt_o => open, |
---|
933 | cnt_ovfl_o => mmc_cnt_ovfl_s |
---|
934 | ); |
---|
935 | end generate; |
---|
936 | |
---|
937 | no_mmc_cnt: if mmc_compat_clk_div_g = 0 generate |
---|
938 | mmc_cnt_ovfl_s <= true; |
---|
939 | end generate; |
---|
940 | |
---|
941 | |
---|
942 | ----------------------------------------------------------------------------- |
---|
943 | -- Output Mapping |
---|
944 | ----------------------------------------------------------------------------- |
---|
945 | spi_clk_o <= spi_clk_q; |
---|
946 | spi_cs_n_o <= spi_cs_n_q; |
---|
947 | spi_data_out_o <= spi_dat_q; |
---|
948 | spi_en_outs_o <= '1' |
---|
949 | when en_outs_q else |
---|
950 | '0'; |
---|
951 | cfg_clk_o <= cfg_clk_q; |
---|
952 | cfg_dat_o <= cfg_dat_q; |
---|
953 | detached_o <= '0' |
---|
954 | when en_outs_q else |
---|
955 | '1'; |
---|
956 | |
---|
957 | end rtl; |
---|