1 | /***************************************************************************** |
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2 | * Filename: radio_controller.h |
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3 | * Version: 2.00.a |
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4 | * Description: radio_controller Driver Header File |
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5 | *****************************************************************************/ |
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6 | |
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7 | #ifndef RADIO_CONTROLLER_H |
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8 | #define RADIO_CONTROLLER_H |
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9 | |
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10 | /***************************** Include Files *******************************/ |
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11 | |
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12 | #include "xbasic_types.h" |
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13 | #include "xstatus.h" |
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14 | #include "xil_io.h" |
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15 | #include "sleep.h" |
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16 | |
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17 | int radio_controller_init(u32 ba, u32 rfSel, u8 clkDiv_SPI, u8 clkDiv_TxDelays); |
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18 | int radio_controller_TxEnable(u32 ba, u32 rfSel); |
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19 | int radio_controller_RxEnable(u32 ba, u32 rfSel); |
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20 | int radio_controller_TxRxDisable(u32 ba, u32 rfSel); |
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21 | int radio_controller_setCenterFrequency(u32 ba, u32 rfSel, u8 bandSel, u8 chanNum); |
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22 | u16 radio_controller_SPI_read(u32 ba, u32 rfSel, u8 regAddr); |
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23 | int radio_controller_SPI_setRegBits(u32 ba, u32 rfSel, u8 regAddr, u16 regDataMask, u16 regData); |
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24 | int radio_controller_setRadioParam(u32 ba, u32 rfSel, u32 paramID, u32 paramVal); |
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25 | int radio_controller_setTxGainSource(u32 ba, u32 rfSel, u8 gainSrc); |
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26 | int radio_controller_setRxGainSource(u32 ba, u32 rfSel, u8 gainSrc); |
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27 | int radio_controller_setCtrlSource(u32 ba, u32 rfSel, u32 ctrlSrcMask, u8 ctrlSrc); |
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28 | int radio_controller_setRxHP(u32 ba, u32 rfSel, u8 mode); |
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29 | int radio_controller_setTxGainTarget(u32 ba, u32 rfSel, u8 gainTarget); |
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30 | int radio_controller_apply_TxDCO_calibration(u32 rc_ba, u32 eeprom_ba, u32 rfSel); |
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31 | int radio_controller_DAC_OffsetAdj(u32 rc_ba, u32 rf_sel, u8 chan, short dc_val); |
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32 | |
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33 | /************************** Constant Definitions ***************************/ |
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34 | |
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35 | #define RC_USER_SLV_SPACE_OFFSET (0x00000000) |
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36 | #define RC_SLV_REG0_OFFSET (RC_USER_SLV_SPACE_OFFSET + 0x00000000) |
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37 | #define RC_SLV_REG1_OFFSET (RC_USER_SLV_SPACE_OFFSET + 0x00000004) |
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38 | #define RC_SLV_REG2_OFFSET (RC_USER_SLV_SPACE_OFFSET + 0x00000008) |
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39 | #define RC_SLV_REG3_OFFSET (RC_USER_SLV_SPACE_OFFSET + 0x0000000C) |
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40 | #define RC_SLV_REG4_OFFSET (RC_USER_SLV_SPACE_OFFSET + 0x00000010) |
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41 | #define RC_SLV_REG5_OFFSET (RC_USER_SLV_SPACE_OFFSET + 0x00000014) |
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42 | #define RC_SLV_REG6_OFFSET (RC_USER_SLV_SPACE_OFFSET + 0x00000018) |
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43 | #define RC_SLV_REG7_OFFSET (RC_USER_SLV_SPACE_OFFSET + 0x0000001C) |
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44 | #define RC_SLV_REG8_OFFSET (RC_USER_SLV_SPACE_OFFSET + 0x00000020) |
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45 | #define RC_SLV_REG9_OFFSET (RC_USER_SLV_SPACE_OFFSET + 0x00000024) |
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46 | #define RC_SLV_REG10_OFFSET (RC_USER_SLV_SPACE_OFFSET + 0x00000028) |
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47 | #define RC_SLV_REG11_OFFSET (RC_USER_SLV_SPACE_OFFSET + 0x0000002C) |
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48 | #define RC_SLV_REG12_OFFSET (RC_USER_SLV_SPACE_OFFSET + 0x00000030) |
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49 | #define RC_SLV_REG13_OFFSET (RC_USER_SLV_SPACE_OFFSET + 0x00000034) |
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50 | #define RC_SLV_REG14_OFFSET (RC_USER_SLV_SPACE_OFFSET + 0x00000038) |
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51 | #define RC_SLV_REG15_OFFSET (RC_USER_SLV_SPACE_OFFSET + 0x0000003C) |
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52 | #define RC_SLV_REG16_OFFSET (RC_USER_SLV_SPACE_OFFSET + 0x00000040) |
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53 | #define RC_SLV_REG17_OFFSET (RC_USER_SLV_SPACE_OFFSET + 0x00000044) |
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54 | #define RC_SLV_REG18_OFFSET (RC_USER_SLV_SPACE_OFFSET + 0x00000048) |
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55 | #define RC_SLV_REG19_OFFSET (RC_USER_SLV_SPACE_OFFSET + 0x0000004C) |
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56 | #define RC_SLV_REG20_OFFSET (RC_USER_SLV_SPACE_OFFSET + 0x00000050) |
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57 | #define RC_SLV_REG21_OFFSET (RC_USER_SLV_SPACE_OFFSET + 0x00000054) |
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58 | #define RC_SLV_REG22_OFFSET (RC_USER_SLV_SPACE_OFFSET + 0x00000058) |
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59 | #define RC_SLV_REG23_OFFSET (RC_USER_SLV_SPACE_OFFSET + 0x0000005C) |
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60 | #define RC_SLV_REG24_OFFSET (RC_USER_SLV_SPACE_OFFSET + 0x00000060) |
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61 | #define RC_SLV_REG25_OFFSET (RC_USER_SLV_SPACE_OFFSET + 0x00000064) |
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62 | #define RC_SLV_REG26_OFFSET (RC_USER_SLV_SPACE_OFFSET + 0x00000068) |
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63 | #define RC_SLV_REG27_OFFSET (RC_USER_SLV_SPACE_OFFSET + 0x0000006C) |
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64 | #define RC_SLV_REG28_OFFSET (RC_USER_SLV_SPACE_OFFSET + 0x00000070) |
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65 | #define RC_SLV_REG29_OFFSET (RC_USER_SLV_SPACE_OFFSET + 0x00000074) |
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66 | #define RC_SLV_REG30_OFFSET (RC_USER_SLV_SPACE_OFFSET + 0x00000078) |
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67 | #define RC_SLV_REG31_OFFSET (RC_USER_SLV_SPACE_OFFSET + 0x0000007C) |
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68 | #define RC_SLV_REG32_OFFSET (RC_USER_SLV_SPACE_OFFSET + 0x00000080) |
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69 | #define RC_SLV_REG33_OFFSET (RC_USER_SLV_SPACE_OFFSET + 0x00000084) |
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70 | #define RC_SLV_REG34_OFFSET (RC_USER_SLV_SPACE_OFFSET + 0x00000088) |
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71 | #define RC_SLV_REG35_OFFSET (RC_USER_SLV_SPACE_OFFSET + 0x0000008C) |
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72 | #define RC_SLV_REG36_OFFSET (RC_USER_SLV_SPACE_OFFSET + 0x00000090) |
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73 | #define RC_SLV_REG37_OFFSET (RC_USER_SLV_SPACE_OFFSET + 0x00000094) |
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74 | #define RC_SLV_REG38_OFFSET (RC_USER_SLV_SPACE_OFFSET + 0x00000098) |
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75 | #define RC_SLV_REG39_OFFSET (RC_USER_SLV_SPACE_OFFSET + 0x0000009C) |
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76 | #define RC_SLV_REG40_OFFSET (RC_USER_SLV_SPACE_OFFSET + 0x000000A0) |
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77 | #define RC_SLV_REG41_OFFSET (RC_USER_SLV_SPACE_OFFSET + 0x000000A4) |
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78 | #define RC_SLV_REG42_OFFSET (RC_USER_SLV_SPACE_OFFSET + 0x000000A8) |
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79 | #define RC_SLV_REG43_OFFSET (RC_USER_SLV_SPACE_OFFSET + 0x000000AC) |
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80 | #define RC_SLV_REG44_OFFSET (RC_USER_SLV_SPACE_OFFSET + 0x000000B0) |
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81 | #define RC_SLV_REG45_OFFSET (RC_USER_SLV_SPACE_OFFSET + 0x000000B4) |
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82 | #define RC_SLV_REG46_OFFSET (RC_USER_SLV_SPACE_OFFSET + 0x000000B8) |
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83 | #define RC_SLV_REG47_OFFSET (RC_USER_SLV_SPACE_OFFSET + 0x000000BC) |
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84 | #define RC_SLV_REG48_OFFSET (RC_USER_SLV_SPACE_OFFSET + 0x000000C0) |
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85 | #define RC_SLV_REG49_OFFSET (RC_USER_SLV_SPACE_OFFSET + 0x000000C4) |
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86 | #define RC_SLV_REG50_OFFSET (RC_USER_SLV_SPACE_OFFSET + 0x000000C8) |
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87 | #define RC_SLV_REG51_OFFSET (RC_USER_SLV_SPACE_OFFSET + 0x000000CC) |
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88 | #define RC_SLV_REG52_OFFSET (RC_USER_SLV_SPACE_OFFSET + 0x000000D0) |
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89 | #define RC_SLV_REG53_OFFSET (RC_USER_SLV_SPACE_OFFSET + 0x000000D4) |
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90 | #define RC_SLV_REG54_OFFSET (RC_USER_SLV_SPACE_OFFSET + 0x000000D8) |
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91 | #define RC_SLV_REG55_OFFSET (RC_USER_SLV_SPACE_OFFSET + 0x000000DC) |
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92 | #define RC_SLV_REG56_OFFSET (RC_USER_SLV_SPACE_OFFSET + 0x000000E0) |
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93 | #define RC_SLV_REG57_OFFSET (RC_USER_SLV_SPACE_OFFSET + 0x000000E4) |
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94 | #define RC_SLV_REG58_OFFSET (RC_USER_SLV_SPACE_OFFSET + 0x000000E8) |
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95 | #define RC_SLV_REG59_OFFSET (RC_USER_SLV_SPACE_OFFSET + 0x000000EC) |
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96 | #define RC_SLV_REG60_OFFSET (RC_USER_SLV_SPACE_OFFSET + 0x000000F0) |
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97 | #define RC_SLV_REG61_OFFSET (RC_USER_SLV_SPACE_OFFSET + 0x000000F4) |
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98 | #define RC_SLV_REG62_OFFSET (RC_USER_SLV_SPACE_OFFSET + 0x000000F8) |
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99 | #define RC_SLV_REG63_OFFSET (RC_USER_SLV_SPACE_OFFSET + 0x000000FC) |
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100 | |
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101 | |
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102 | /***** Register Masks ******** |
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103 | * See comments in user_logic.v for full address map |
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104 | *******************************/ |
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105 | |
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106 | //Control source bits: 0=use registers, 1=use hardware ports (usr_* in HDL) |
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107 | |
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108 | //Per-RF chain masks, shared by registers 0, 2, 3, 11 below |
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109 | #define RC_CTRLREGMASK_RFA 0x000000FF |
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110 | #define RC_CTRLREGMASK_RFB 0x0000FF00 |
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111 | #define RC_CTRLREGMASK_RFC 0x00FF0000 |
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112 | #define RC_CTRLREGMASK_RFD 0xFF000000 |
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113 | |
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114 | //register 0 masks |
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115 | #define RC_REG0_TXEN 0x80808080 |
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116 | #define RC_REG0_RXEN 0x40404040 |
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117 | #define RC_REG0_RXHP 0x20202020 |
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118 | #define RC_REG0_SHDN 0x10101010 |
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119 | |
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120 | #define RC_REG0_TXEN_CTRLSRC 0x08080808 |
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121 | #define RC_REG0_RXEN_CTRLSRC 0x04040404 |
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122 | #define RC_REG0_RXHP_CTRLSRC 0x02020202 |
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123 | #define RC_REG0_SHDN_CTRLSRC 0x01010101 |
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124 | |
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125 | #define RC_REG0_ALL_CTRLSRC 0x0F0F0F0F |
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126 | |
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127 | //register 1 masks |
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128 | #define RC_REG1_DLY_PAEN 0x00FF0000 |
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129 | #define RC_REG1_DLY_TXEN 0x0000FF00 |
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130 | #define RX_REG1_DLY_PHY 0x000000FF |
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131 | |
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132 | //register 2 masks |
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133 | #define RC_REG2_TXGAIN 0x3F3F3F3F |
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134 | #define RC_REG2_TXGAIN_CTRLSRC 0x80808080 |
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135 | |
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136 | //register 3 masks |
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137 | #define RC_REG3_RXGAIN_BB 0x1F1F1F1F |
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138 | #define RC_REG3_RXGAIN_RF 0x60606060 |
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139 | #define RC_REG3_RXGAIN_CTRLSRC 0x80808080 |
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140 | |
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141 | //register 4 masks |
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142 | #define RC_REG4_CLKDIV_SPI 0x00000070 |
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143 | #define RC_REG4_CLKDIV_SPI_SHIFT 4 |
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144 | |
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145 | #define RC_REG4_CLKDIV_TXDLY 0x00000003 |
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146 | #define RC_REG4_CLKDIV_TXDLY_SHIFT 0 |
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147 | |
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148 | #define RC_REG4_CLKDIV_DAC_SPI 0x00070000 |
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149 | #define RC_REG4_CLKDIV_DAC_SPI_SHIFT 16 |
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150 | |
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151 | //register 5 masks |
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152 | #define RC_REG5_RFSEL_RFD 0x80000000 |
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153 | #define RC_REG5_RFSEL_RFC 0x40000000 |
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154 | #define RC_REG5_RFSEL_RFB 0x20000000 |
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155 | #define RC_REG5_RFSEL_RFA 0x10000000 |
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156 | #define RC_REG5_RFSEL_ALL (RC_REG5_RFSEL_RFA | RC_REG5_RFSEL_RFB | RC_REG5_RFSEL_RFC | RC_REG5_RFSEL_RFD) |
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157 | |
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158 | #define RC_REG5_REGADDR 0x000F0000 |
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159 | #define RF_REG5_REGADDR_SHIFT 16 |
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160 | #define RC_REG5_REGDATA 0x00003FFF |
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161 | |
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162 | //register 6 masks |
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163 | #define RC_REG6_DACSEL_RFD 0x80000000 |
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164 | #define RC_REG6_DACSEL_RFC 0x40000000 |
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165 | #define RC_REG6_DACSEL_RFB 0x20000000 |
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166 | #define RC_REG6_DACSEL_RFA 0x10000000 |
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167 | #define RC_REG6_DACSEL_ALL (RC_REG6_DACSEL_RFA | RC_REG6_DACSEL_RFB | RC_REG6_DACSEL_RFC | RC_REG6_DACSEL_RFD) |
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168 | |
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169 | #define RC_REG6_REGADDR 0x000F0000 //AD9777 registers have 5 bit addresses, but MSB is always 0 |
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170 | #define RC_REG6_REGADDR_SHIFT 16 |
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171 | #define RC_REG6_REGDATA 0x000000FF //AD9777 SPI writes are 8 data bits |
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172 | |
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173 | //register 7 is DAC SPI Rx (1 byte per RF) |
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174 | |
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175 | //register 8- Converter aux control |
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176 | #define RC_REG8_MASK_RFA 0xFF000000 |
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177 | #define RC_REG8_MASK_RFB 0x00FF0000 |
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178 | #define RC_REG8_MASK_RFC 0x0000FF00 |
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179 | #define RC_REG8_MASK_RFD 0x000000FF |
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180 | |
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181 | #define RC_REG8_MASK_ANTSW_MODE 0x01010101 |
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182 | |
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183 | #define RC_REG8_MASK_RXADC_DCS 0x80808080 |
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184 | #define RC_REG8_MASK_RXADC_DFS 0x40404040 |
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185 | #define RC_REG8_MASK_RXADC_PWDN 0x20202020 |
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186 | #define RC_REG8_MASK_RSSIADC_CLAMP 0x10101010 |
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187 | #define RC_REG8_MASK_RSSIADC_HIZ 0x08080808 |
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188 | #define RC_REG8_MASK_RSSIADC_SLEEP 0x04040404 |
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189 | #define RC_REG8_MASK_DAC_RESET 0x02020202 |
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190 | |
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191 | //register 9- aux status inputs |
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192 | //same per-RF masks as reg8 |
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193 | #define RC_REG9_MASK_DIP_SW 0xF0F0F0F0 |
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194 | #define RC_REG9_MASK_DAC_PLL_LOCK 0x08080808 |
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195 | |
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196 | //register 10 is reserved (implemented as 32-bit RW, not tied to external ports) |
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197 | |
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198 | //easier macros for user code |
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199 | #define RC_RFA RC_REG5_RFSEL_RFA |
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200 | #define RC_RFB RC_REG5_RFSEL_RFB |
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201 | #define RC_RFC RC_REG5_RFSEL_RFC |
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202 | #define RC_RFD RC_REG5_RFSEL_RFD |
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203 | #define RC_ANY_RF RC_REG5_RFSEL_ALL |
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204 | |
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205 | #define RC_TXEN_CTRLSRC RC_REG0_TXEN_CTRLSRC |
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206 | #define RC_RXEN_CTRLSRC RC_REG0_RXEN_CTRLSRC |
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207 | #define RC_RXHP_CTRLSRC RC_REG0_RXHP_CTRLSRC |
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208 | #define RC_SHDN_CTRLSRC RC_REG0_SHDN_CTRLSRC |
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209 | |
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210 | |
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211 | |
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212 | //register 11 masks |
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213 | #define RC_REG11_TXEN 0x80808080 |
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214 | #define RC_REG11_RXEN 0x40404040 |
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215 | #define RC_REG11_RXHP 0x20202020 |
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216 | #define RC_REG11_SHDN 0x10101010 |
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217 | #define RC_REG11_LD 0x08080808 |
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218 | #define RC_REG11_SPI_ACTIVE 0x04040404 |
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219 | #define RC_REG11_24PA_ACTIVE 0x02020202 |
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220 | #define RC_REG11_5PA_ACTIVE 0x01010101 |
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221 | |
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222 | |
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223 | //registers 12-24 are mirror regs for RFA |
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224 | //registers 25-37 are mirror regs for RFB |
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225 | //registers 38-50 are mirror regs for RFC |
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226 | //registers 51-63 are mirror regs for RFD |
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227 | #define RC_SPI_MIRRORREGS_RFA_BASEADDR RC_SLV_REG12_OFFSET |
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228 | #define RC_SPI_MIRRORREGS_RFB_BASEADDR RC_SLV_REG25_OFFSET |
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229 | #define RC_SPI_MIRRORREGS_RFC_BASEADDR RC_SLV_REG38_OFFSET |
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230 | #define RC_SPI_MIRRORREGS_RFD_BASEADDR RC_SLV_REG51_OFFSET |
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231 | |
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232 | #define RC_EEPROM_TXDCO_ADDR_RFA_I 16364 |
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233 | #define RC_EEPROM_TXDCO_ADDR_RFA_Q 16366 |
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234 | #define RC_EEPROM_TXDCO_ADDR_RFB_I 16368 |
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235 | #define RC_EEPROM_TXDCO_ADDR_RFB_Q 16370 |
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236 | |
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237 | /********** Macros **********/ |
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238 | #define radio_controller_setCtrlSrc(ba, rfSel, x) (Xil_Out32(ba+RC_SLV_REG0_OFFSET, \ |
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239 | (Xil_In32(ba+RC_SLV_REG0_OFFSET) & ~(RC_REG0_RXEN & rfSel)) | \ |
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240 | (RC_REG0_TXEN & rfSel) | (RC_REG0_SHDN & rfSel))) |
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241 | |
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242 | |
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243 | #define radio_controller_setClkDiv_SPI(ba, x) (Xil_Out32(ba+RC_SLV_REG4_OFFSET, \ |
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244 | ((Xil_In32(ba+RC_SLV_REG4_OFFSET)&(~RC_REG4_CLKDIV_SPI)) | \ |
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245 | ((x<<RC_REG4_CLKDIV_SPI_SHIFT) & RC_REG4_CLKDIV_SPI)))) |
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246 | |
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247 | #define radio_controller_setClkDiv_TxDelays(ba, x) (Xil_Out32(ba+RC_SLV_REG4_OFFSET, \ |
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248 | ((Xil_In32(ba+RC_SLV_REG4_OFFSET)&(~RC_REG4_CLKDIV_TXDLY)) | \ |
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249 | ((x<<RC_REG4_CLKDIV_TXDLY_SHIFT) & RC_REG4_CLKDIV_TXDLY)))) |
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250 | |
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251 | //TxEn, RxEn and SHDN are mutually exclusive in normal operation, so asserting one here forces the others off for the selected RF paths |
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252 | // TxEn/RxEn are active high, SHDN is active low |
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253 | // TxEn: reg0 <= (current reg0 with selected RxEn deasserted) + (selected TxEn asserted) + (selected SHDN deasserted) |
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254 | #define radio_controller_setMode_Tx(ba, rfSel) (Xil_Out32(ba+RC_SLV_REG0_OFFSET, \ |
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255 | (Xil_In32(ba+RC_SLV_REG0_OFFSET) & ~(RC_REG0_RXEN & rfSel)) | \ |
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256 | (RC_REG0_TXEN & rfSel) | (RC_REG0_SHDN & rfSel))) |
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257 | |
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258 | // RxEn: reg0 <= (current reg0 with selected TxEn deasserted) + (selected TxEn asserted) + (selected SHDN deasserted) |
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259 | #define radio_controller_setMode_Rx(ba, rfSel) (Xil_Out32(ba+RC_SLV_REG0_OFFSET, \ |
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260 | (Xil_In32(ba+RC_SLV_REG0_OFFSET) & ~(RC_REG0_TXEN & rfSel)) | \ |
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261 | (RC_REG0_RXEN & rfSel) | (RC_REG0_SHDN & rfSel))) |
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262 | |
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263 | // Shutdown: reg0 <= (current reg0 with selected Tx, Rx deasserted) + (selected SHDN asserted) |
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264 | #define radio_controller_setMode_shutdown(ba, rfSel) (Xil_Out32(ba+RC_SLV_REG0_OFFSET, \ |
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265 | (Xil_In32(ba+RC_SLV_REG0_OFFSET) & ~((RC_REG0_TXEN | RC_REG0_RXEN | RC_REG0_SHDN) & rfSel)))) |
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266 | |
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267 | // Standby: reg0 <= (current reg0 with selected Tx, Rx, SHDN deasserted) |
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268 | #define radio_controller_setMode_standby(ba, rfSel) (Xil_Out32(ba+RC_SLV_REG0_OFFSET, \ |
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269 | (Xil_In32(ba+RC_SLV_REG0_OFFSET) & ~((RC_REG0_TXEN | RC_REG0_RXEN) & rfSel)) | \ |
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270 | (RC_REG0_SHDN & rfSel))) |
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271 | |
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272 | // Reset: reg0 <= (current reg0 with selected Tx, Rx, SHDN asserted) |
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273 | #define radio_controller_setMode_reset(ba, rfSel) (Xil_Out32(ba+RC_SLV_REG0_OFFSET, \ |
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274 | (Xil_In32(ba+RC_SLV_REG0_OFFSET) & ~(RC_REG0_SHDN & rfSel)) | \ |
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275 | ((RC_REG0_TXEN | RC_REG0_RXEN) & rfSel))) |
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276 | |
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277 | #define radio_controller_SPI_write(ba, rfsel, regaddr, regdata) (Xil_Out32(ba+RC_SLV_REG5_OFFSET, \ |
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278 | (rfsel & RC_REG5_RFSEL_ALL) | \ |
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279 | (regdata & RC_REG5_REGDATA) | \ |
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280 | ((regaddr << RF_REG5_REGADDR_SHIFT) & RC_REG5_REGADDR))) |
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281 | |
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282 | |
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283 | #define radio_controller_setTxDelays(ba, dly_GainRamp, dly_PA, dly_TX, dly_PHY) Xil_Out32(ba+RC_SLV_REG1_OFFSET, ( \ |
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284 | ((dly_GainRamp&0xFF)<<24) | ((dly_PA&0xFF)<<16) | ((dly_TX&0xFF)<<8) | (dly_PHY&0xFF))) |
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285 | |
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286 | #define radio_controller_setTxGainTiming(ba, gainStep, timeStep) Xil_Out32(ba+RC_SLV_REG4_OFFSET, (Xil_In32(ba+RC_SLV_REG4_OFFSET) & (~(0x0000FF00))) | \ |
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287 | ((gainStep&0xF)<<8) | ((timeStep&0xF)<<12)) |
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288 | |
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289 | //DAC SPI macros |
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290 | #define radio_controller_DAC_SPI_write(ba, dacsel, regaddr, regdata) (Xil_Out32(ba+RC_SLV_REG6_OFFSET, \ |
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291 | (dacsel & RC_REG6_DACSEL_ALL) | \ |
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292 | (regdata & RC_REG6_REGDATA) | \ |
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293 | ((regaddr << RC_REG6_REGADDR_SHIFT) & RC_REG6_REGADDR))) |
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294 | |
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295 | #define radio_controller_setClkDiv_DAC_SPI(ba, x) (Xil_Out32(ba+RC_SLV_REG4_OFFSET, \ |
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296 | ((Xil_In32(ba+RC_SLV_REG4_OFFSET)&(~RC_REG4_CLKDIV_DAC_SPI)) | \ |
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297 | ((x<<RC_REG4_CLKDIV_DAC_SPI_SHIFT) & RC_REG4_CLKDIV_DAC_SPI)))) |
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298 | |
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299 | #define RC_24GHZ 0 |
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300 | #define RC_5GHZ 1 |
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301 | |
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302 | #define RC_GAINSRC_SPI 1 |
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303 | #define RC_GAINSRC_REG 2 |
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304 | #define RC_GAINSRC_HW 3 |
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305 | |
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306 | #define RC_CTRLSRC_HW 1 |
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307 | #define RC_CTRLSRC_REG 2 |
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308 | |
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309 | #define RC_RXHP_OFF 0 |
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310 | #define RC_RXHP_ON 1 |
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311 | |
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312 | #define RC_INCLUDED_PARAMS_GAIN_CTRL 1 |
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313 | #define RC_INCLUDED_PARAMS_FILTS 1 |
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314 | #define RC_INCLUDED_PARAMS_MISC 1 |
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315 | #define RC_INCLUDED_PARAMS_CALIBRATION 1 |
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316 | |
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317 | #define RC_PARAMID_TXGAINS_SPI_CTRL_EN 1 |
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318 | #define RC_PARAMID_RXGAINS_SPI_CTRL_EN 2 |
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319 | #define RC_PARAMID_RXGAIN_RF 3 |
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320 | #define RC_PARAMID_RXGAIN_BB 4 |
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321 | #define RC_PARAMID_TXGAIN_RF 5 |
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322 | #define RC_PARAMID_TXGAIN_BB 6 |
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323 | #define RC_PARAMID_RSSI_HIGH_BW_EN 7 |
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324 | #define RC_PARAMID_TXLINEARITY_PADRIVER 8 |
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325 | #define RC_PARAMID_TXLINEARITY_VGA 9 |
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326 | #define RC_PARAMID_TXLINEARITY_UPCONV 10 |
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327 | #define RC_PARAMID_TXLPF_BW 12 |
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328 | #define RC_PARAMID_RXLPF_BW 13 |
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329 | #define RC_PARAMID_RXLPF_BW_FINE 14 |
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330 | #define RC_PARAMID_RXHPF_HIGH_CUTOFF_EN 15 |
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331 | |
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332 | #define RC_INVALID_PARAM -2 |
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333 | #define RC_INVALID_PARAMID -3 |
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334 | #define RC_INVALID_RFSEL -4 |
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335 | #endif /** RADIO_CONTROLLER_H */ |
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