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prog_clk_config_boot.psm

Last change on this file was 4318, checked in by murphpo, 9 years ago
fixed index typo in asm comment
File size: 37.1 KB

Line
1	;;;;;;;;;;;;;;;;;;;;;;;;;;;
2	;Output ports
3	CONSTANT port_TX_UART, 00
4	CONSTANT port_SPI_CLK, 01
5	CONSTANT port_SPI_MOSI, 02
6	CONSTANT port_SPI_CS, 03
7	CONSTANT port_IIC_OUT, 04 ;[0]=clk, [1]=data
8	CONSTANT port_LEDS, 05
9	CONSTANT port_CTRL, 06
10
11	;Bit definitions for port_SPI_CS
12	CONSTANT SPI_CS_SampClkBuf, 01
13	CONSTANT SPI_CS_RFRefClkBuf, 02
14	CONSTANT SPI_CS_ClkModPLL, 04
15
16	;Bit definitions for port_CTRL
17	CONSTANT CONFIG_DONE, 01
18	CONSTANT PLL_REFCLK_MON_EN, 02
19	CONSTANT TX_UART_RESET, 04
20
21	;;;;;;;;;;;;;;;;;;;;;;;;;;;
22	;Input ports
23	CONSTANT port_TX_UART_STATUS, 00
24	CONSTANT port_SPI_MISO, 01
25	CONSTANT port_CM_STATUS, 02
26	CONSTANT port_IIC_IN, 03 ;[0]=clk, [1]=data
27
28	;Bit definitions for port_TX_UART_STATUS
29	CONSTANT TX_UART_STATUS_FULL, 04
30
31	;Bit definitions for port_CM_STATUS
32	CONSTANT CM_STATUS_SW0, 01
33	CONSTANT CM_STATUS_SW1, 02
34	CONSTANT CM_STATUS_SW01, 03
35	CONSTANT CM_STATUS_SW2, 04
36	CONSTANT CM_STATUS_SW_ALL, 07
37	CONSTANT CM_STATUS_PLL_LOCK, 08
38	CONSTANT CM_STATUS_REFCLK_VLD, 10
39
40	;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
41	;IIC EEPROM Contents
42	; 15000:15001 Delimeter bytes == 0xA5CD
43	;
44	; 15002 RF Ref Configs (16 bytes each)
45	; 15002:15017 RF Ref Config No-CM
46	; 15018:15033 RF Ref Config A CM-MMCX
47	; 15034:15049 RF Ref Config B CM-MMCX
48	; 15050:15065 RF Ref Config C CM-MMCX
49	; 15066:15081 RF Ref Config A CM-PLL
50	; 15082:15097 RF Ref Config B CM-PLL
51	; 15098:15113 RF Ref Config C CM-PLL
52	;
53	; 15130 Samp Configs (16 bytes each)
54	; 15130:15145 Samp Config No-CM
55	; 15146:15161 Samp Config A CM-MMCX
56	; 15162:15177 Samp Config B CM-MMCX
57	; 15178:15193 Samp Config C CM-MMCX
58	; 15194:15209 Samp Config A CM-PLL
59	; 15210:15225 Samp Config B CM-PLL
60	; 15226:15241 Samp Config C CM-PLL
61	;
62	; 15258 PLL Configs (80 bytes each)
63	; 15258:15337 PLL Config No-CM
64	; 15338:15417 PLL Config A CM-PLL
65	; 15418:15497 PLL Config B CM-PLL
66	; 15498:15577 PLL Config C CM-PLL
67
68	CONSTANT EEPROM_IIC_ADDR, 50 ; 24AA128 EEPROM dev addr = 0b1010000 = 0x50
69
70	CONSTANT EEPROM_CFG_DELIM_B0, A5
71	CONSTANT EEPROM_CFG_DELIM_B1, CD
72
73	CONSTANT EEPROM_ADDR_CFG_BASE_U, 3A ;1500 = 0x3A98
74	CONSTANT EEPROM_ADDR_CFG_BASE_L, 98
75
76	;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
77	; RF Ref Clk Buffer Config Offsets
78	CONSTANT EEPROM_ADDR_CFG_RFREF_NOCM_U, 3A ;15002 = 0x3A9A
79	CONSTANT EEPROM_ADDR_CFG_RFREF_NOCM_L, 9A
80
81	CONSTANT EEPROM_ADDR_CFG_RFREF_CMMMCX_A_U, 3A ;15018 = 0x3AAA
82	CONSTANT EEPROM_ADDR_CFG_RFREF_CMMMCX_A_L, AA
83	CONSTANT EEPROM_ADDR_CFG_RFREF_CMMMCX_B_U, 3A ;15034 = 0x3ABA
84	CONSTANT EEPROM_ADDR_CFG_RFREF_CMMMCX_B_L, BA
85	CONSTANT EEPROM_ADDR_CFG_RFREF_CMMMCX_C_U, 3A ;15050 = 0x3ACA
86	CONSTANT EEPROM_ADDR_CFG_RFREF_CMMMCX_C_L, CA
87
88	CONSTANT EEPROM_ADDR_CFG_RFREF_CMPLL_A_U, 3A ;15066 = 0x3ADA
89	CONSTANT EEPROM_ADDR_CFG_RFREF_CMPLL_A_L, DA
90	CONSTANT EEPROM_ADDR_CFG_RFREF_CMPLL_B_U, 3A ;15082 = 0x3AEA
91	CONSTANT EEPROM_ADDR_CFG_RFREF_CMPLL_B_L, EA
92	CONSTANT EEPROM_ADDR_CFG_RFREF_CMPLL_C_U, 3A ;15098 = 0x3AFA
93	CONSTANT EEPROM_ADDR_CFG_RFREF_CMPLL_C_L, FA
94
95	;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
96	; Samp Clk Buffer Config Offsets
97	CONSTANT EEPROM_ADDR_CFG_SAMP_NOCM_U, 3B ;15130 = 0x3B1A
98	CONSTANT EEPROM_ADDR_CFG_SAMP_NOCM_L, 1A
99
100	CONSTANT EEPROM_ADDR_CFG_SAMP_CMMMCX_A_U, 3B ;15146 = 0x3B2A
101	CONSTANT EEPROM_ADDR_CFG_SAMP_CMMMCX_A_L, 2A
102	CONSTANT EEPROM_ADDR_CFG_SAMP_CMMMCX_B_U, 3B ;15162 = 0x3B3A
103	CONSTANT EEPROM_ADDR_CFG_SAMP_CMMMCX_B_L, 3A
104	CONSTANT EEPROM_ADDR_CFG_SAMP_CMMMCX_C_U, 3B ;15178 = 0x3B4A
105	CONSTANT EEPROM_ADDR_CFG_SAMP_CMMMCX_C_L, 4A
106
107	CONSTANT EEPROM_ADDR_CFG_SAMP_CMPLL_A_U, 3B ;15194 = 0x3B5A
108	CONSTANT EEPROM_ADDR_CFG_SAMP_CMPLL_A_L, 5A
109	CONSTANT EEPROM_ADDR_CFG_SAMP_CMPLL_B_U, 3B ;15210 = 0x3B6A
110	CONSTANT EEPROM_ADDR_CFG_SAMP_CMPLL_B_L, 6A
111	CONSTANT EEPROM_ADDR_CFG_SAMP_CMPLL_C_U, 3B ;15226 = 0x3B7A
112	CONSTANT EEPROM_ADDR_CFG_SAMP_CMPLL_C_L, 7A
113
114	;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
115	; PLL Config Offsets
116	CONSTANT EEPROM_ADDR_CFG_PLL_NOCM_A_U, 3B ;15258 = 0x3B9A
117	CONSTANT EEPROM_ADDR_CFG_PLL_NOCM_A_L, 9A
118
119	CONSTANT EEPROM_ADDR_CFG_PLL_CMPLL_A_U, 3B ;15338 = 0x3BEA
120	CONSTANT EEPROM_ADDR_CFG_PLL_CMPLL_A_L, EA
121	CONSTANT EEPROM_ADDR_CFG_PLL_CMPLL_B_U, 3C ;15418 = 0x3C3A
122	CONSTANT EEPROM_ADDR_CFG_PLL_CMPLL_B_L, 3A
123	CONSTANT EEPROM_ADDR_CFG_PLL_CMPLL_C_U, 3C ;15338 = 0x3C8A
124	CONSTANT EEPROM_ADDR_CFG_PLL_CMPLL_C_L, 8A
125
126	CONSTANT SPAD_ADDR_CFG_RFREF, 00
127	CONSTANT SPAD_ADDR_CFG_SAMP, 16'd
128	CONSTANT SPAD_ADDR_CFG_PLL, 32'd
129
130	;;;;;;;;;;;;;;;;;;;;;;;;;;;
131
132	; COMPARE sX, sY:
133	; Z C Cond
134	; 0 0 sX > sY
135	; x 1 sX < sY
136	; 1 x sX == sY
137
138	; TEST sX, sY:
139	; Z C Cond
140	; 1 0 (sX bitand sY) == 8'b0
141	; 0 1 (sX bitand sY) has odd number of 1
142
143
144	start: CALL delay_10ms
145	CALL init_scratchpad
146	OUTPUTK 00, port_CTRL
147
148	LOAD sB, msg_init'upper
149	LOAD sA, msg_init'lower
150	CALL send_message
151	OUTPUTK 01, port_LEDS
152
153	;Check for valid config delimeter in EEPROM
154	LOAD s7, EEPROM_ADDR_CFG_BASE_L
155	LOAD s8, EEPROM_ADDR_CFG_BASE_U
156	CALL EEPROM_read_byte
157	COMPARE sD, EEPROM_CFG_DELIM_B0
158	JUMP NZ, config_no_eeprom ;first byte wrong - ignore EEPROM
159	ADD s7, 01
160	ADDCY s8, 00
161	CALL EEPROM_read_byte
162	COMPARE sD, EEPROM_CFG_DELIM_B1
163	JUMP NZ, config_no_eeprom ;second byte wrong - ignore EEPROM
164
165	;Valid delimeter found in EEPROM - use EEPROM contents for clock config
166	config_from_eeprom: LOAD sB, msg_eeprom_det'upper
167	LOAD sA, msg_eeprom_det'lower
168	CALL send_message
169	;
170	INPUT s0, port_CM_STATUS ;read CM switch
171	AND s0, CM_STATUS_SW_ALL ;mask off switch bits
172	LOAD s1, s0 ;make copy
173	AND s1, CM_STATUS_SW01 ;check for sw[1:0]==0x3
174	COMPARE s1, CM_STATUS_SW01 ; 0x3 indicates no clock module is mounted
175	JUMP Z, read_eeprom_cfgs_nocm ; sw[1:0]==0x3 -> no clk module
176
177	;Clock module found!
178	TEST s0, CM_STATUS_SW2 ;check if CM-PLL (sw[2]==0)
179	JUMP Z, read_eeprom_cfgs_cmpll ;sw[2]==0 -> CM-PLL is mounted
180	JUMP read_eeprom_cfgs_cmmmcx ;otherwise CM-MMCX is mounted
181
182	; s1 still has sw[1:0] values
183	; sw[1:0] == 3 already handled above (indicates no clock module)
184	read_eeprom_cfgs_cmpll: LOAD sB, msg_cmpll_det'upper
185	LOAD sA, msg_cmpll_det'lower
186	CALL send_message
187	;
188	COMPARE s1, 00 ; sw[1:0] == [2,1,0] -> configs [A,B,C]
189	JUMP Z, read_eeprom_cfgs_cmpll_C
190	COMPARE s1, CM_STATUS_SW0
191	JUMP Z, read_eeprom_cfgs_cmpll_B
192	JUMP read_eeprom_cfgs_cmpll_A
193
194	read_eeprom_cfgs_cmpll_A: LOAD sB, msg_cfg_A'upper
195	LOAD sA, msg_cfg_A'lower
196	CALL send_message
197	;
198	LOAD s7, EEPROM_ADDR_CFG_RFREF_CMPLL_A_L
199	LOAD s8, EEPROM_ADDR_CFG_RFREF_CMPLL_A_U
200	LOAD s9, SPAD_ADDR_CFG_RFREF
201	LOAD s2, 16'd
202	CALL copy_eeprom_to_scratchpad
203
204	LOAD s7, EEPROM_ADDR_CFG_SAMP_CMPLL_A_L
205	LOAD s8, EEPROM_ADDR_CFG_SAMP_CMPLL_A_U
206	LOAD s9, SPAD_ADDR_CFG_SAMP
207	LOAD s2, 16'd
208	CALL copy_eeprom_to_scratchpad
209	LOAD s7, EEPROM_ADDR_CFG_PLL_CMPLL_A_L
210	LOAD s8, EEPROM_ADDR_CFG_PLL_CMPLL_A_U
211	LOAD s9, SPAD_ADDR_CFG_PLL
212	LOAD s2, 40'd
213	CALL copy_eeprom_to_scratchpad
214	LOAD sF, 01 ;do wait on PLL lock
215	JUMP write_cfg_from_scratchpad
216
217	read_eeprom_cfgs_cmpll_B: LOAD sB, msg_cfg_B'upper
218	LOAD sA, msg_cfg_B'lower
219	CALL send_message
220	;
221	LOAD s7, EEPROM_ADDR_CFG_RFREF_CMPLL_B_L
222	LOAD s8, EEPROM_ADDR_CFG_RFREF_CMPLL_B_U
223	LOAD s9, SPAD_ADDR_CFG_RFREF
224	LOAD s2, 16'd
225	CALL copy_eeprom_to_scratchpad
226	LOAD s7, EEPROM_ADDR_CFG_SAMP_CMPLL_B_L
227	LOAD s8, EEPROM_ADDR_CFG_SAMP_CMPLL_B_U
228	LOAD s9, SPAD_ADDR_CFG_SAMP
229	LOAD s2, 16'd
230	CALL copy_eeprom_to_scratchpad
231	LOAD s7, EEPROM_ADDR_CFG_PLL_CMPLL_B_L
232	LOAD s8, EEPROM_ADDR_CFG_PLL_CMPLL_B_U
233	LOAD s9, SPAD_ADDR_CFG_PLL
234	LOAD s2, 40'd
235	CALL copy_eeprom_to_scratchpad
236	LOAD sF, 01 ;do wait on PLL lock
237	JUMP write_cfg_from_scratchpad
238
239	read_eeprom_cfgs_cmpll_C: LOAD sB, msg_cfg_C'upper
240	LOAD sA, msg_cfg_C'lower
241	CALL send_message
242	;
243	LOAD s7, EEPROM_ADDR_CFG_RFREF_CMPLL_C_L
244	LOAD s8, EEPROM_ADDR_CFG_RFREF_CMPLL_C_U
245	LOAD s9, SPAD_ADDR_CFG_RFREF
246	LOAD s2, 16'd
247	CALL copy_eeprom_to_scratchpad
248	LOAD s7, EEPROM_ADDR_CFG_SAMP_CMPLL_C_L
249	LOAD s8, EEPROM_ADDR_CFG_SAMP_CMPLL_C_U
250	LOAD s9, SPAD_ADDR_CFG_SAMP
251	LOAD s2, 16'd
252	CALL copy_eeprom_to_scratchpad
253	LOAD s7, EEPROM_ADDR_CFG_PLL_CMPLL_C_L
254	LOAD s8, EEPROM_ADDR_CFG_PLL_CMPLL_C_U
255	LOAD s9, SPAD_ADDR_CFG_PLL
256	LOAD s2, 40'd
257	CALL copy_eeprom_to_scratchpad
258	LOAD sF, 01 ;do wait on PLL lock
259	JUMP write_cfg_from_scratchpad
260
261	; s1 still has sw[1:0] values
262	; sw[1:0] == 3 already handled above (indicates no clock module)
263	read_eeprom_cfgs_cmmmcx: LOAD sB, msg_cmmmcx_det'upper
264	LOAD sA, msg_cmmmcx_det'lower
265	CALL send_message
266	;
267	COMPARE s1, 00 ; sw[1:0] == [2,1,0] -> configs [A,B,C]
268	JUMP Z, read_eeprom_cfgs_cmmmcx_C
269	COMPARE s1, CM_STATUS_SW0
270	JUMP Z, read_eeprom_cfgs_cmmmcx_B
271	JUMP read_eeprom_cfgs_cmmmcx_A
272
273	read_eeprom_cfgs_cmmmcx_A: LOAD sB, msg_cfg_A'upper
274	LOAD sA, msg_cfg_A'lower
275	CALL send_message
276	;
277	LOAD s7, EEPROM_ADDR_CFG_RFREF_CMMMCX_A_L
278	LOAD s8, EEPROM_ADDR_CFG_RFREF_CMMMCX_A_U
279	LOAD s9, SPAD_ADDR_CFG_RFREF
280	LOAD s2, 16'd
281	CALL copy_eeprom_to_scratchpad
282	LOAD s7, EEPROM_ADDR_CFG_SAMP_CMMMCX_A_L
283	LOAD s8, EEPROM_ADDR_CFG_SAMP_CMMMCX_A_U
284	LOAD s9, SPAD_ADDR_CFG_SAMP
285	LOAD s2, 16'd
286	CALL copy_eeprom_to_scratchpad
287	LOAD sF, 00 ;don't wait on PLL lock
288	JUMP write_cfg_from_scratchpad
289
290	read_eeprom_cfgs_cmmmcx_B: LOAD sB, msg_cfg_B'upper
291	LOAD sA, msg_cfg_B'lower
292	CALL send_message
293	;
294	LOAD s7, EEPROM_ADDR_CFG_RFREF_CMMMCX_B_L
295	LOAD s8, EEPROM_ADDR_CFG_RFREF_CMMMCX_B_U
296	LOAD s9, SPAD_ADDR_CFG_RFREF
297	LOAD s2, 16'd
298	CALL copy_eeprom_to_scratchpad
299	LOAD s7, EEPROM_ADDR_CFG_SAMP_CMMMCX_B_L
300	LOAD s8, EEPROM_ADDR_CFG_SAMP_CMMMCX_B_U
301	LOAD s9, SPAD_ADDR_CFG_SAMP
302	LOAD s2, 16'd
303	CALL copy_eeprom_to_scratchpad
304	LOAD sF, 00 ;don't wait on PLL lock
305	JUMP write_cfg_from_scratchpad
306
307	read_eeprom_cfgs_cmmmcx_C: LOAD sB, msg_cfg_C'upper
308	LOAD sA, msg_cfg_C'lower
309	CALL send_message
310	;
311	LOAD s7, EEPROM_ADDR_CFG_RFREF_CMMMCX_C_L
312	LOAD s8, EEPROM_ADDR_CFG_RFREF_CMMMCX_C_U
313	LOAD s9, SPAD_ADDR_CFG_RFREF
314	LOAD s2, 16'd
315	CALL copy_eeprom_to_scratchpad
316	LOAD s7, EEPROM_ADDR_CFG_SAMP_CMMMCX_C_L
317	LOAD s8, EEPROM_ADDR_CFG_SAMP_CMMMCX_C_U
318	LOAD s9, SPAD_ADDR_CFG_SAMP
319	LOAD s2, 16'd
320	CALL copy_eeprom_to_scratchpad
321	LOAD sF, 00 ;don't wait on PLL lock
322	JUMP write_cfg_from_scratchpad
323
324	; No clock module mounted
325	; Still write SPI config to PLL pins, just in case the user
326	; left sw[1:0] de-asserted, to avoid unecessary noise/power by PLL
327	; circuit whose outputs are ignored
328	read_eeprom_cfgs_nocm: LOAD sB, msg_nocm_det'upper
329	LOAD sA, msg_nocm_det'lower
330	CALL send_message
331	;
332	LOAD s7, EEPROM_ADDR_CFG_RFREF_NOCM_L
333	LOAD s8, EEPROM_ADDR_CFG_RFREF_NOCM_U
334	LOAD s9, SPAD_ADDR_CFG_RFREF
335	LOAD s2, 16'd
336	CALL copy_eeprom_to_scratchpad
337	LOAD s7, EEPROM_ADDR_CFG_SAMP_NOCM_L
338	LOAD s8, EEPROM_ADDR_CFG_SAMP_NOCM_U
339	LOAD s9, SPAD_ADDR_CFG_SAMP
340	LOAD s2, 16'd
341	CALL copy_eeprom_to_scratchpad
342	LOAD s7, EEPROM_ADDR_CFG_PLL_NOCM_A_L
343	LOAD s8, EEPROM_ADDR_CFG_PLL_NOCM_A_U
344	LOAD s9, SPAD_ADDR_CFG_PLL
345	LOAD s2, 40'd
346	CALL copy_eeprom_to_scratchpad
347	;
348	LOAD sF, 00 ;don't wait on PLL lock
349	JUMP write_cfg_from_scratchpad
350
351	config_no_eeprom: LOAD sB, msg_noeeprom_det'upper
352	LOAD sA, msg_noeeprom_det'lower
353	CALL send_message
354
355	INPUT s0, port_CM_STATUS ;read CM switch
356	AND s0, CM_STATUS_SW_ALL ;mask off switch bits
357	LOAD s1, s0 ;make copy
358	AND s1, CM_STATUS_SW01 ;check for sw[1:0]==0x3
359	COMPARE s1, CM_STATUS_SW01 ; 0x3 indicates no clock module is mounted
360	JUMP Z, read_noeeprom_cfgs_nocm ; sw[1:0]==0x3 -> no clk module
361
362	;Clock module found!
363	TEST s0, CM_STATUS_SW2 ;check if CM-PLL (sw[2]==0)
364	JUMP Z, read_noeeprom_cfgs_cmpll ;sw[2]==0 -> CM-PLL is mounted
365	JUMP read_noeeprom_cfgs_cmmmcx ;otherwise CM-MMCX is mounted
366
367	; No clock module mounted
368	; Still write SPI config to PLL pins, just in case the user
369	; left sw[1:0] de-asserted, to avoid unecessary noise/power by PLL
370	; circuit whose outputs are ignored
371	read_noeeprom_cfgs_nocm: LOAD sB, msg_nocm_det'upper
372	LOAD sA, msg_nocm_det'lower
373	CALL send_message
374	;Copy RF ref configs
375	LOAD s7, cfg_nocm_rfref_addr'lower
376	LOAD s8, cfg_nocm_rfref_addr'upper
377	LOAD s9, cfg_nocm_rfref_data'lower
378	LOAD sA, cfg_nocm_rfref_data'upper
379	LOAD s6, SPAD_ADDR_CFG_RFREF
380	LOAD s5, 16'd
381	CALL copy_tables_to_scratchpad
382	;Copy samp configs
383	LOAD s7, cfg_nocm_samp_addr'lower
384	LOAD s8, cfg_nocm_samp_addr'upper
385	LOAD s9, cfg_nocm_samp_data'lower
386	LOAD sA, cfg_nocm_samp_data'upper
387	LOAD s6, SPAD_ADDR_CFG_SAMP
388	LOAD s5, 16'd
389	CALL copy_tables_to_scratchpad
390	;Copy PLL configs
391	LOAD s7, cfg_nocm_pll_addr'lower
392	LOAD s8, cfg_nocm_pll_addr'upper
393	LOAD s9, cfg_nocm_pll_data'lower
394	LOAD sA, cfg_nocm_pll_data'upper
395	LOAD s6, SPAD_ADDR_CFG_PLL
396	LOAD s5, 40'd
397	CALL copy_tables_to_scratchpad
398	;
399	LOAD sF, 00 ;don't wait on PLL lock
400	JUMP write_cfg_from_scratchpad
401
402	; s1 still has sw[1:0] values
403	; sw[1:0] == 3 already handled above (indicates no clock module)
404	read_noeeprom_cfgs_cmmmcx: LOAD sB, msg_cmmmcx_det'upper
405	LOAD sA, msg_cmmmcx_det'lower
406	CALL send_message
407	;
408	COMPARE s1, 00 ; sw[1:0] == [2,1,0] -> configs [A,B,C]
409	JUMP Z, read_noeeprom_cfgs_cmmmcx_C
410	COMPARE s1, CM_STATUS_SW0
411	JUMP Z, read_noeeprom_cfgs_cmmmcx_B
412	JUMP read_noeeprom_cfgs_cmmmcx_A
413
414	read_noeeprom_cfgs_cmmmcx_A: LOAD sB, msg_cfg_A'upper
415	LOAD sA, msg_cfg_A'lower
416	CALL send_message
417	;Copy RF ref configs
418	LOAD s7, cfg_cmmmcx_A_rfref_addr'lower
419	LOAD s8, cfg_cmmmcx_A_rfref_addr'upper
420	LOAD s9, cfg_cmmmcx_A_rfref_data'lower
421	LOAD sA, cfg_cmmmcx_A_rfref_data'upper
422	LOAD s6, SPAD_ADDR_CFG_RFREF
423	LOAD s5, 16'd
424	CALL copy_tables_to_scratchpad
425	;Copy samp configs
426	LOAD s7, cfg_cmmmcx_A_samp_addr'lower
427	LOAD s8, cfg_cmmmcx_A_samp_addr'upper
428	LOAD s9, cfg_cmmmcx_A_samp_data'lower
429	LOAD sA, cfg_cmmmcx_A_samp_data'upper
430	LOAD s6, SPAD_ADDR_CFG_SAMP
431	LOAD s5, 16'd
432	CALL copy_tables_to_scratchpad
433	;
434	LOAD sF, 00 ;don't wait on PLL lock
435	JUMP write_cfg_from_scratchpad
436
437	read_noeeprom_cfgs_cmmmcx_B: LOAD sB, msg_cfg_B'upper
438	LOAD sA, msg_cfg_B'lower
439	CALL send_message
440	;Copy RF ref configs
441	LOAD s7, cfg_cmmmcx_B_rfref_addr'lower
442	LOAD s8, cfg_cmmmcx_B_rfref_addr'upper
443	LOAD s9, cfg_cmmmcx_B_rfref_data'lower
444	LOAD sA, cfg_cmmmcx_B_rfref_data'upper
445	LOAD s6, SPAD_ADDR_CFG_RFREF
446	LOAD s5, 16'd
447	CALL copy_tables_to_scratchpad
448	;Copy samp configs
449	LOAD s7, cfg_cmmmcx_B_samp_addr'lower
450	LOAD s8, cfg_cmmmcx_B_samp_addr'upper
451	LOAD s9, cfg_cmmmcx_B_samp_data'lower
452	LOAD sA, cfg_cmmmcx_B_samp_data'upper
453	LOAD s6, SPAD_ADDR_CFG_SAMP
454	LOAD s5, 16'd
455	CALL copy_tables_to_scratchpad
456	;
457	LOAD sF, 00 ;don't wait on PLL lock
458	JUMP write_cfg_from_scratchpad
459
460	read_noeeprom_cfgs_cmmmcx_C: LOAD sB, msg_cfg_C'upper
461	LOAD sA, msg_cfg_C'lower
462	CALL send_message
463	;Copy RF ref configs
464	LOAD s7, cfg_cmmmcx_C_rfref_addr'lower
465	LOAD s8, cfg_cmmmcx_C_rfref_addr'upper
466	LOAD s9, cfg_cmmmcx_C_rfref_data'lower
467	LOAD sA, cfg_cmmmcx_C_rfref_data'upper
468	LOAD s6, SPAD_ADDR_CFG_RFREF
469	LOAD s5, 16'd
470	CALL copy_tables_to_scratchpad
471	;Copy samp configs
472	LOAD s7, cfg_cmmmcx_C_samp_addr'lower
473	LOAD s8, cfg_cmmmcx_C_samp_addr'upper
474	LOAD s9, cfg_cmmmcx_C_samp_data'lower
475	LOAD sA, cfg_cmmmcx_C_samp_data'upper
476	LOAD s6, SPAD_ADDR_CFG_SAMP
477	LOAD s5, 16'd
478	CALL copy_tables_to_scratchpad
479	;
480	LOAD sF, 00 ;don't wait on PLL lock
481	JUMP write_cfg_from_scratchpad
482
483
484	; s1 still has sw[1:0] values
485	; sw[1:0] == 3 already handled above (indicates no clock module)
486	read_noeeprom_cfgs_cmpll: LOAD sB, msg_cmpll_det'upper
487	LOAD sA, msg_cmpll_det'lower
488	CALL send_message
489	;
490	COMPARE s1, 00 ; sw[1:0] == [2,1,0] -> configs [A,B,C]
491	JUMP Z, read_noeeprom_cfgs_cmpll_C
492	COMPARE s1, CM_STATUS_SW0
493	JUMP Z, read_noeeprom_cfgs_cmpll_B
494	JUMP read_noeeprom_cfgs_cmpll_A
495
496	read_noeeprom_cfgs_cmpll_A: LOAD sB, msg_cfg_A'upper
497	LOAD sA, msg_cfg_A'lower
498	CALL send_message
499	;Copy RF ref configs
500	LOAD s7, cfg_cmpll_A_rfref_addr'lower
501	LOAD s8, cfg_cmpll_A_rfref_addr'upper
502	LOAD s9, cfg_cmpll_A_rfref_data'lower
503	LOAD sA, cfg_cmpll_A_rfref_data'upper
504	LOAD s6, SPAD_ADDR_CFG_RFREF
505	LOAD s5, 16'd
506	CALL copy_tables_to_scratchpad
507	;Copy samp configs
508	LOAD s7, cfg_cmpll_A_samp_addr'lower
509	LOAD s8, cfg_cmpll_A_samp_addr'upper
510	LOAD s9, cfg_cmpll_A_samp_data'lower
511	LOAD sA, cfg_cmpll_A_samp_data'upper
512	LOAD s6, SPAD_ADDR_CFG_SAMP
513	LOAD s5, 16'd
514	CALL copy_tables_to_scratchpad
515	;Copy PLL configs
516	LOAD s7, cfg_cmpll_A_pll_addr'lower
517	LOAD s8, cfg_cmpll_A_pll_addr'upper
518	LOAD s9, cfg_cmpll_A_pll_data'lower
519	LOAD sA, cfg_cmpll_A_pll_data'upper
520	LOAD s6, SPAD_ADDR_CFG_PLL
521	LOAD s5, 40'd
522	CALL copy_tables_to_scratchpad
523	;
524	LOAD sF, 01 ;do wait on PLL lock
525	JUMP write_cfg_from_scratchpad
526
527	read_noeeprom_cfgs_cmpll_B: LOAD sB, msg_cfg_B'upper
528	LOAD sA, msg_cfg_B'lower
529	CALL send_message
530	;Copy RF ref configs
531	LOAD s7, cfg_cmpll_B_rfref_addr'lower
532	LOAD s8, cfg_cmpll_B_rfref_addr'upper
533	LOAD s9, cfg_cmpll_B_rfref_data'lower
534	LOAD sA, cfg_cmpll_B_rfref_data'upper
535	LOAD s6, SPAD_ADDR_CFG_RFREF
536	LOAD s5, 16'd
537	CALL copy_tables_to_scratchpad
538	;Copy samp configs
539	LOAD s7, cfg_cmpll_B_samp_addr'lower
540	LOAD s8, cfg_cmpll_B_samp_addr'upper
541	LOAD s9, cfg_cmpll_B_samp_data'lower
542	LOAD sA, cfg_cmpll_B_samp_data'upper
543	LOAD s6, SPAD_ADDR_CFG_SAMP
544	LOAD s5, 16'd
545	CALL copy_tables_to_scratchpad
546	;Copy PLL configs
547	LOAD s7, cfg_cmpll_B_pll_addr'lower
548	LOAD s8, cfg_cmpll_B_pll_addr'upper
549	LOAD s9, cfg_cmpll_B_pll_data'lower
550	LOAD sA, cfg_cmpll_B_pll_data'upper
551	LOAD s6, SPAD_ADDR_CFG_PLL
552	LOAD s5, 40'd
553	CALL copy_tables_to_scratchpad
554	;
555	LOAD sF, 01 ;do wait on PLL lock
556	JUMP write_cfg_from_scratchpad
557
558	read_noeeprom_cfgs_cmpll_C: LOAD sB, msg_cfg_C'upper
559	LOAD sA, msg_cfg_C'lower
560	CALL send_message
561	;Copy RF ref configs
562	LOAD s7, cfg_cmpll_C_rfref_addr'lower
563	LOAD s8, cfg_cmpll_C_rfref_addr'upper
564	LOAD s9, cfg_cmpll_C_rfref_data'lower
565	LOAD sA, cfg_cmpll_C_rfref_data'upper
566	LOAD s6, SPAD_ADDR_CFG_RFREF
567	LOAD s5, 16'd
568	CALL copy_tables_to_scratchpad
569	;Copy samp configs
570	LOAD s7, cfg_cmpll_C_samp_addr'lower
571	LOAD s8, cfg_cmpll_C_samp_addr'upper
572	LOAD s9, cfg_cmpll_C_samp_data'lower
573	LOAD sA, cfg_cmpll_C_samp_data'upper
574	LOAD s6, SPAD_ADDR_CFG_SAMP
575	LOAD s5, 16'd
576	CALL copy_tables_to_scratchpad
577	;Copy PLL configs
578	LOAD s7, cfg_cmpll_C_pll_addr'lower
579	LOAD s8, cfg_cmpll_C_pll_addr'upper
580	LOAD s9, cfg_cmpll_C_pll_data'lower
581	LOAD sA, cfg_cmpll_C_pll_data'upper
582	LOAD s6, SPAD_ADDR_CFG_PLL
583	LOAD s5, 40'd
584	CALL copy_tables_to_scratchpad
585	;
586	LOAD sF, 01 ;do wait on PLL lock
587	JUMP write_cfg_from_scratchpad
588
589
590
591	; write_cfg_from_scratchpad: write cfg values from scratchpad to all devices
592	;
593	; Scratchpad contains SPI address/data values to write
594	; RF Ref (16 addr/data values at SPAD_ADDR_CFG_RFREF)
595	; Samp (16 addr/data values at SPAD_ADDR_CFG_SAMP)
596	; PLL (40 addr/data values at SPAD_ADDR_CFG_PLL)
597	;
598	; Addr=0xFF terminates each device's config
599	write_cfg_from_scratchpad: LOAD s0, SPI_CS_RFRefClkBuf
600	LOAD sA, SPAD_ADDR_CFG_RFREF
601	LOAD sB, 16'd
602	CALL write_device_regs
603
604	LOAD s0, SPI_CS_SampClkBuf
605	LOAD sA, SPAD_ADDR_CFG_SAMP
606	LOAD sB, 16'd
607	CALL write_device_regs
608
609	COMPARE sF, 00
610	CALL NZ, wait_for_pll_refclk
611
612	LOAD s0, SPI_CS_ClkModPLL
613	LOAD sA, SPAD_ADDR_CFG_PLL
614	LOAD sB, 40'd
615	CALL write_device_regs
616
617	COMPARE sF, 00
618	JUMP Z, config_complete
619
620	LOAD sB, msg_cm_pll_lock_wait'upper
621	LOAD sA, msg_cm_pll_lock_wait'lower
622	CALL send_message
623
624	CALL wait_for_pll_lock
625
626	config_complete: LOAD sB, msg_config_done'upper
627	LOAD sA, msg_config_done'lower
628	CALL send_message
629	;
630	OUTPUTK 00, port_TX_UART ;Ensure all outputs stay at 0 post-sleep
631	OUTPUTK 00, port_SPI_CLK
632	OUTPUTK 00, port_SPI_MOSI
633	OUTPUTK 00, port_SPI_CS ;PB output is active-high; wrapper inverts
634	OUTPUTK 00, port_IIC_OUT ;00 tri-states both IIC IOBUFTs
635	OUTPUTK 00, port_LEDS
636
637	OUTPUTK CONFIG_DONE, port_CTRL ;asserts PicoBlaze sleep, halting execution
638	JUMP end_loop
639
640	end_loop: JUMP end_loop ;wait forever (wrapper will assert PicoBlaze.sleep)
641
642	;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
643	; Subroutines
644	;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
645
646	;wait_for_pll_refclk: loops until refclk monitor indicates stable refclk input
647	; Regs: modifies s1
648	;
649	wait_for_pll_refclk: LOAD sB, msg_refclk_wait'upper
650	LOAD sA, msg_refclk_wait'lower
651	CALL send_message
652	OUTPUTK PLL_REFCLK_MON_EN, port_CTRL
653	wait_for_pll_refclk_next: INPUT s1, port_CM_STATUS
654	TEST s1, CM_STATUS_REFCLK_VLD
655	JUMP Z, wait_for_pll_refclk_next
656	wait_for_pll_refclk_done: LOAD sB, msg_refclk_valid'upper
657	LOAD sA, msg_refclk_valid'lower
658	CALL send_message
659	RETURN
660
661
662	;write_device_regs: write addr/data values from scratchpad to SPI
663	; Args:
664	; sA: First addr value in scrathpad (values must be addr/data/addr/data...)
665	; sB: Number of addr/data values to write
666	;
667	; sA,sB not preserved
668	;
669	write_device_regs: FETCH s2, (sA) ;retrieve the address byte from the scratcpad
670	COMPARE s2, FF ;check for magic value - addr=0xFF means stop
671	RETURN Z ;return if finished, otherwise continue with byte Tx
672	ADD sA, 01 ;incremenet scratchpad pointer (to corresponding data value)
673	FETCH s1, (sA) ;retrieve the data byte from the scratcpad
674	CALL write_spi_reg ;send byte in s2 to address in s1 via SPI
675	SUB sB, 01
676	RETURN Z ;return if all bytes have been sent
677	ADD sA, 01 ;incremenet scratchpad pointer (to next addr value)
678	JUMP write_device_regs
679
680	;wait_for_pll_lock: loops until PLL STATUS indicates lock
681	; Hardware design must pull STATUS pin high so no-CM and CM-MMCX
682	; configurations complete successfully
683	; Args: None
684	; Reg s0 not preserved
685	;
686	wait_for_pll_lock: INPUT s0, port_CM_STATUS
687	AND s0, CM_STATUS_PLL_LOCK
688	JUMP Z, wait_for_pll_lock
689	LOAD sB, msg_cm_pll_lock_done'upper
690	LOAD sA, msg_cm_pll_lock_done'lower
691	CALL send_message
692	RETURN
693
694	; Copies bytes from IIC EEPROM to scratchpad memory
695	; Args: s7: LSB of starting EEPROM address
696	; s8: MSB of starting EEPROM address
697	; s9: Starting scratchpad address
698	; s2: Number of bytes to copy
699	; Regs: Modifies s0, s1, s2, s5, s7, s8, s9, sD, sF
700	copy_eeprom_to_scratchpad: CALL EEPROM_read_byte ;read eeprom([s8,s7]) into sD
701	STORE sD, (s9) ;save byte to scratchpad
702	SUB s2, 01 ;decrement byte counter
703	RETURN Z ;return when all bytes have been copied
704	ADD s9, 01 ;increment scratchpad address
705	ADD s7, 01 ;incremenet EEPROM address
706	ADDCY s8, 00
707	JUMP copy_eeprom_to_scratchpad
708
709	; copy_tables_to_scratchpad - copies bytes from addr/data tables to scratchpad memory
710	; Iterates for s5 bytes or until an address byte == 0xFF
711	;
712	; Args: s5: Number of addr/data pairs to copy
713	; s6: Starting addresss in scratchpad
714	; s7: LSB of address of table containing SPI address bytes
715	; s8: MSB of address of table containing SPI address bytes
716	; s9: LSB of address of table containing SPI data bytes
717	; sA: MSB of address of table containing SPI data bytes
718	; Regs: modifies s2, s3, s5, s6, s7, s8, s9, sA
719	;
720	; Requires tables use LOAD&RETURN syntax with returned value stored in s2
721
722	copy_tables_to_scratchpad: CALL@ (s8, s7) ;load next addr byte into s2
723	STORE s2, (s6) ;write addr byte to scratchpad
724	LOAD s3, s2 ;make a copy for comparison below
725	ADD s6, 01 ;incremenet scratchpad pointer
726	CALL@ (sA, s9) ;load next data byte into s2
727	STORE s2, (s6) ;write data byte to scratchpad
728	COMPARE s3, FF ;check for magic value indicating last byte
729	RETURN Z ;return if finished, otherwise continue with byte Tx
730	SUB s5, 01
731	RETURN Z ;Return if all requested bytes have been copied
732	ADD s6, 01 ;incremenet scratchpad pointer
733	ADD s7, 01 ;increment addr table pointer
734	ADDCY s8, 00
735	ADD s9, 01 ;increment data table pointer
736	ADDCY sA, 00
737	JUMP copy_tables_to_scratchpad
738
739	; Initialize scratchpad memory with 0xFF at addresses 0:127
740	; Regs: Modifies s0, s1
741	init_scratchpad: LOAD s0, 127'd
742	LOAD s1, FF
743	init_scratchpad_next: STORE s1, (s0) ;Write value of s1 (0xFF) to offset in s0
744	SUB s0, 01
745	JUMP NZ, init_scratchpad_next
746	RETURN
747
748	; EEPROM_read_byte - reads 1 byte from the EEPROM
749	; This routine will read the byte from the 24AA128 EEPROM at the address specified by the [s8,s7]
750	; registers and return it in register 'sD'. [s8,s7] must be an address in the range 000 to 3FFF hex.
751	; Args:
752	; [s8,s7]: Byte address in 0x000 to 0x3FFF
753	; Regs: Modifies s0, s1, s2, s5, s7, s8, s9, sD, sF
754	EEPROM_read_byte: CALL I2C_initialise ;ensure bus state and initialise 'sF'
755	CALL I2C_start ;bus start (S)
756	;
757	LOAD s5, EEPROM_IIC_ADDR ;device base address (7-bits)
758	SL0 s5 ;Write operation (LSB = 0)
759	CALL I2C_Tx_byte ;Transmit address with write
760	CALL I2C_Rx_ACK ;Receive ACK
761	RETURN C ;Return on failure (Carry flag set)
762	;
763	LOAD s5, s8 ;{x, x, byte_addr[13:8]}
764	CALL I2C_Tx_byte
765	CALL I2C_Rx_ACK ;Receive ACK
766	RETURN C ;Return on failure (Carry flag set)
767	;
768	LOAD s5, s7 ;byte_addr[7:0]
769	CALL I2C_Tx_byte
770	CALL I2C_Rx_ACK ;Receive ACK
771	RETURN C ;Return on failure (Carry flag set)
772	;
773	CALL I2C_start ;bus restart (Sr)
774	;
775	LOAD s5, EEPROM_IIC_ADDR ;device base address (7-bits)
776	SL1 s5 ;Read operation (LSB = 1)
777	CALL I2C_Tx_byte ;Transmit address with write
778	CALL I2C_Rx_ACK ;Receive ACK
779	RETURN C ;Return on failure (Carry flag set)
780	;
781	CALL I2C_Rx_byte ;Read data from M24C08
782	LOAD sD, s5
783	;
784	CALL I2C_Tx_NACK ;Transmit NACK to end read operation
785	CALL I2C_stop ;transmit stop (P)
786	RETURN ;with Carry flag reset
787
788
789	;write_spi_reg: Writes 1 byte to SPI
790	; Implements SPI protocol for many ADI devices. Every SPI transaction is 24 bits:
791	; Bits 0- 7: SPI command - all zeros for 1-byte write
792	; Bits 8-15: SPI register address (MSB first)
793	; Bits 16-23: Data byte to write
794	;
795	; This method only implements SPI write and ignores the slave device's MISO signal
796	;
797	; Register usage:
798	; Arg: Chip select value in s0
799	; Arg: Data byte in s1
800	; Arg: Address byte in s2
801	; Internal: s3, s4, s5
802	;
803	; Registers s1, s2 are preserved
804	; Registers s3, s4, s5 are not preserved
805	;
806	; Internal regs:
807	; s3: Data byte currently being transmitted; byte left-shifted in place
808	; s4: Bit counter
809	;
810	write_spi_reg: OUTPUT s0, port_SPI_CS ;Assert the selected chip select
811	LOAD s3, 00 ;Send SPI instruction byte (00 == write 1 byte)
812	CALL write_spi_byte
813	LOAD s3, s2 ;Send SPI register address
814	CALL write_spi_byte
815	LOAD s3, s1 ;Send data byte
816	CALL write_spi_byte
817	OUTPUTK 00, port_SPI_CS ;de-assert all chip selects
818	RETURN
819
820	;write_spi_byte: helper method for write_spi_reg
821	; writes single byte to SPI output
822	; Byte must be passed in s3, s3 will be shifted in-place as bits are sent
823	;
824	; The instruction order here determines the setup/hold times betweek the CLK and MOSI signals
825	; With a 200MHz clk the instruction order below results in:
826	; SPI clk @ 12.5MHz, (3/8) duty cycle (~30ns high, ~50ns low)
827	; MOSI-SCLK setup time = 16ns (approx)
828	; SCLK-MOSI hold time = 60ns (approx)
829	;
830	; These timings provide a large margin from AD9511/AD9512 requirements
831	;
832	write_spi_byte: LOAD s4, 08 ;Load bit counter
833	write_spi_bit: LOAD s5, s3 ;prepare next bit to transmit
834	OUTPUT s5, port_SPI_MOSI ;output data bit to MOSI port (hardware must ignore bits [6:0]!)
835	SLA s3 ;shift data byte, moving next bit to MSB
836	OUTPUTK FF, port_SPI_CLK ;set clk outputs to 1
837	SUB s4, 01 ;decrement bit counter
838	LOAD s0, s0 ;noop
839	OUTPUTK 00, port_SPI_CLK ;set clk outputs to 0 (doesn't touch flags)
840	JUMP NZ, write_spi_bit ;repeat until last bit
841	RETURN
842
843	; 10ms is 200,000 x 50ns (200,000 = 030D40 hex)
844	delay_10ms: LOAD s2, 03
845	LOAD s1, 0D
846	LOAD s0, 40
847	JUMP software_delay
848
849	; 10 cycles per iteration (50ns @ 200MHz)
850	software_delay: LOAD s0, s0 ;pad loop to make it 10 clock cycles (5 instructions)
851	SUB s0, 1'd
852	SUBCY s1, 0'd
853	SUBCY s2, 0'd
854	JUMP NZ, software_delay
855	RETURN
856
857	; send_message - writes string to UART
858	; Message must be stored at address [sB,sA] using standard LOAD&RETURN scheme
859	; String must include trailing NUL character for send_message to terminate
860	send_message: CALL@ (sB, sA)
861	COMPARE s9, 00 ;terminate on NUL character
862	RETURN Z
863	CALL UART_TX
864	ADD sA, 1'd
865	ADDCY sB, 0'd
866	JUMP send_message
867
868	reset_UART_Tx: OUTPUTK TX_UART_RESET, port_CTRL
869	OUTPUTK 00, port_CTRL
870	RETURN
871
872	UART_TX: INPUT s0, port_TX_UART_STATUS ;Check if buffer is full
873	TEST s0, TX_UART_STATUS_FULL
874	JUMP NZ, UART_TX ;wait if full
875	OUTPUT s9, port_TX_UART
876	RETURN
877
878	;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
879	; Define code sections with SPI data and address values
880	; LOAD&RETURN instructions are auto-expanded by the assembler
881	;
882
883	;;;;;;;;;;;;;;;;;;;;;;;
884	; RF ref clock buffer
885	cfg_nocm_rfref_addr: LOAD&RETURN s2, TBL_CFG_NOCM_RFREF_ADDR#
886	cfg_nocm_rfref_data: LOAD&RETURN s2, TBL_CFG_NOCM_RFREF_DATA#
887
888	cfg_cmmmcx_A_rfref_addr: LOAD&RETURN s2, TBL_CFG_CMMMCX_A_RFREF_ADDR#
889	cfg_cmmmcx_A_rfref_data: LOAD&RETURN s2, TBL_CFG_CMMMCX_A_RFREF_DATA#
890
891	cfg_cmmmcx_B_rfref_addr: LOAD&RETURN s2, TBL_CFG_CMMMCX_B_RFREF_ADDR#
892	cfg_cmmmcx_B_rfref_data: LOAD&RETURN s2, TBL_CFG_CMMMCX_B_RFREF_DATA#
893
894	cfg_cmmmcx_C_rfref_addr: LOAD&RETURN s2, TBL_CFG_CMMMCX_C_RFREF_ADDR#
895	cfg_cmmmcx_C_rfref_data: LOAD&RETURN s2, TBL_CFG_CMMMCX_C_RFREF_DATA#
896
897	cfg_cmpll_A_rfref_addr: LOAD&RETURN s2, TBL_CFG_CMPLL_A_RFREF_ADDR#
898	cfg_cmpll_A_rfref_data: LOAD&RETURN s2, TBL_CFG_CMPLL_A_RFREF_DATA#
899
900	cfg_cmpll_B_rfref_addr: LOAD&RETURN s2, TBL_CFG_CMPLL_B_RFREF_ADDR#
901	cfg_cmpll_B_rfref_data: LOAD&RETURN s2, TBL_CFG_CMPLL_B_RFREF_DATA#
902
903	cfg_cmpll_C_rfref_addr: LOAD&RETURN s2, TBL_CFG_CMPLL_C_RFREF_ADDR#
904	cfg_cmpll_C_rfref_data: LOAD&RETURN s2, TBL_CFG_CMPLL_C_RFREF_DATA#
905
906	;;;;;;;;;;;;;;;;;;;;;;;
907	; Sampling clock buffer
908	cfg_nocm_samp_addr: LOAD&RETURN s2, TBL_CFG_NOCM_SAMP_ADDR#
909	cfg_nocm_samp_data: LOAD&RETURN s2, TBL_CFG_NOCM_SAMP_DATA#
910
911	cfg_cmmmcx_A_samp_addr: LOAD&RETURN s2, TBL_CFG_CMMMCX_A_SAMP_ADDR#
912	cfg_cmmmcx_A_samp_data: LOAD&RETURN s2, TBL_CFG_CMMMCX_A_SAMP_DATA#
913
914	cfg_cmmmcx_B_samp_addr: LOAD&RETURN s2, TBL_CFG_CMMMCX_B_SAMP_ADDR#
915	cfg_cmmmcx_B_samp_data: LOAD&RETURN s2, TBL_CFG_CMMMCX_B_SAMP_DATA#
916
917	cfg_cmmmcx_C_samp_addr: LOAD&RETURN s2, TBL_CFG_CMMMCX_C_SAMP_ADDR#
918	cfg_cmmmcx_C_samp_data: LOAD&RETURN s2, TBL_CFG_CMMMCX_C_SAMP_DATA#
919
920	cfg_cmpll_A_samp_addr: LOAD&RETURN s2, TBL_CFG_CMPLL_A_SAMP_ADDR#
921	cfg_cmpll_A_samp_data: LOAD&RETURN s2, TBL_CFG_CMPLL_A_SAMP_DATA#
922
923	cfg_cmpll_B_samp_addr: LOAD&RETURN s2, TBL_CFG_CMPLL_B_SAMP_ADDR#
924	cfg_cmpll_B_samp_data: LOAD&RETURN s2, TBL_CFG_CMPLL_B_SAMP_DATA#
925
926	cfg_cmpll_C_samp_addr: LOAD&RETURN s2, TBL_CFG_CMPLL_C_SAMP_ADDR#
927	cfg_cmpll_C_samp_data: LOAD&RETURN s2, TBL_CFG_CMPLL_C_SAMP_DATA#
928
929	;;;;;;;;;;;;;;;;;;;;;;;
930	; PLL
931	cfg_nocm_pll_addr: LOAD&RETURN s2, TBL_CFG_NOCM_PLL_ADDR#
932	cfg_nocm_pll_data: LOAD&RETURN s2, TBL_CFG_NOCM_PLL_DATA#
933
934	cfg_cmpll_A_pll_addr: LOAD&RETURN s2, TBL_CFG_CMPLL_A_PLL_ADDR#
935	cfg_cmpll_A_pll_data: LOAD&RETURN s2, TBL_CFG_CMPLL_A_PLL_DATA#
936
937	cfg_cmpll_B_pll_addr: LOAD&RETURN s2, TBL_CFG_CMPLL_B_PLL_ADDR#
938	cfg_cmpll_B_pll_data: LOAD&RETURN s2, TBL_CFG_CMPLL_B_PLL_DATA#
939
940	cfg_cmpll_C_pll_addr: LOAD&RETURN s2, TBL_CFG_CMPLL_C_PLL_ADDR#
941	cfg_cmpll_C_pll_data: LOAD&RETURN s2, TBL_CFG_CMPLL_C_PLL_DATA#
942
943	;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
944	; Define strings for UART output
945	STRING str_init1$, " *** WARP v3 Clock Config Core ***"
946	STRING str_init2$, " Program Assembly Date: "
947
948	STRING str_eeprom_det$, "Found config data in EEPROM"
949	STRING str_noeeprom_det$, "No config data in EEPROM - Using Defaults"
950
951	STRING str_nocm_det$, "No Clock Module Detected"
952	STRING str_cmmmcx_det$, "Detected CM-MMCX Module"
953	STRING str_cmpll_det$, "Detected CM-PLL Module"
954
955	STRING str_cfg_A$, "Loading configuration A"
956	STRING str_cfg_B$, "Loading configuration B"
957	STRING str_cfg_C$, "Loading configuration C"
958
959	STRING str_pll_lock_wait$, "Waiting for AD9511 PLL lock..."
960	STRING str_pll_lock_done$, "PLL locked!"
961
962	STRING str_refclk_wait$, "Waiting for valid PLL ref clk......"
963	STRING str_refclk_valid$, "ref clk valid!"
964
965	STRING str_config_done$, "Clock Config Complete - Continuing Boot Process"
966	STRING str_div_line$, "***********************************************"
967
968	msg_init: LOAD&RETURN s9, CR
969	LOAD&RETURN s9, str_div_line$
970	LOAD&RETURN s9, CR
971	LOAD&RETURN s9, str_init1$
972	LOAD&RETURN s9, CR
973	LOAD&RETURN s9, str_init2$
974	LOAD&RETURN s9, datestamp$
975	LOAD&RETURN s9, CR
976	LOAD&RETURN s9, CR
977	LOAD&RETURN s9, NUL
978
979	msg_eeprom_det: LOAD&RETURN s9, str_eeprom_det$
980	LOAD&RETURN s9, CR
981	LOAD&RETURN s9, NUL
982
983	msg_noeeprom_det: LOAD&RETURN s9, str_noeeprom_det$
984	LOAD&RETURN s9, CR
985	LOAD&RETURN s9, NUL
986
987	msg_nocm_det: LOAD&RETURN s9, str_nocm_det$
988	LOAD&RETURN s9, CR
989	LOAD&RETURN s9, NUL
990
991	msg_cfg_A: LOAD&RETURN s9, str_cfg_A$
992	LOAD&RETURN s9, CR
993	LOAD&RETURN s9, NUL
994
995	msg_cfg_B: LOAD&RETURN s9, str_cfg_B$
996	LOAD&RETURN s9, CR
997	LOAD&RETURN s9, NUL
998
999	msg_cfg_C: LOAD&RETURN s9, str_cfg_C$
1000	LOAD&RETURN s9, CR
1001	LOAD&RETURN s9, NUL
1002
1003	msg_cmmmcx_det: LOAD&RETURN s9, str_cmmmcx_det$
1004	LOAD&RETURN s9, CR
1005	LOAD&RETURN s9, NUL
1006
1007	msg_cmpll_det: LOAD&RETURN s9, str_cmpll_det$
1008	LOAD&RETURN s9, CR
1009	LOAD&RETURN s9, NUL
1010
1011
1012	msg_refclk_wait: LOAD&RETURN s9, str_refclk_wait$
1013	LOAD&RETURN s9, NUL
1014
1015	msg_refclk_valid: LOAD&RETURN s9, str_refclk_valid$
1016	LOAD&RETURN s9, CR
1017	LOAD&RETURN s9, NUL
1018
1019	msg_cm_pll_lock_wait: LOAD&RETURN s9, str_pll_lock_wait$
1020	LOAD&RETURN s9, NUL
1021
1022	msg_cm_pll_lock_done: LOAD&RETURN s9, str_pll_lock_done$
1023	LOAD&RETURN s9, CR
1024	LOAD&RETURN s9, CR
1025	LOAD&RETURN s9, NUL
1026
1027	msg_config_done: LOAD&RETURN s9, str_config_done$
1028	LOAD&RETURN s9, CR
1029	LOAD&RETURN s9, str_div_line$
1030	LOAD&RETURN s9, CR
1031	LOAD&RETURN s9, CR
1032	LOAD&RETURN s9, NUL
1033
1034	INCLUDE "i2c_routines.psm"
1035	INCLUDE "clk_config_defaults.psm"

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source: PlatformSupport/CustomPeripherals/pcores/w3_clock_controller_axi_v4_00_a/hdl/verilog/picoblaze_src/prog_clk_config_boot.psm

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