source: PlatformSupport/XBD/boards/Rice_University_WARP_FPGA_V4FX100_v22_ClkBoard/data/Rice_University_WARP_FPGA_V4FX100_v22_ClkBoard_v2_2_0.xbd

# -------------------------------------------------------------
#  Copyright (c) 2009 Rice University
#  All Rights Reserved
#  This code is covered by the Rice-WARP license
#  See http://warp.rice.edu/license/ for details
# -------------------------------------------------------------

ATTRIBUTE VENDOR = Rice University - WARP Project 
ATTRIBUTE SPEC_URL = http://warp.rice.edu/
ATTRIBUTE CONTACT_INFO_URL= http://warp.rice.edu/
ATTRIBUTE NAME = WARP Kits (FPGA/Clock/Radio Boards)
ATTRIBUTE REVISION = FPGA 2.2 / Radio 1.4 / Clock 1.1 (XPS 10 Version)
ATTRIBUTE DESC = Rice University WARP
ATTRIBUTE LONG_DESC = 'This board utilizes a Xilinx Virtex-4 FPGA XC4VFX100-FF1517-11C. The peripherals included thus far are LEDs, Pushbuttons, Hex Displays, SystemACE, DipSW, Clock Board Controller, Serial Port 0 and 1, Trimode Ethernet MAC, 2GB DDR2 SO-DIMM Memory, Radio Controller and Bridges for all 4 slots, Analog Bridge for slot 4, User IO Board bridge for slot 1.'

BEGIN IO_INTERFACE
    ATTRIBUTE IOTYPE = XIL_CLOCK_V1
    ATTRIBUTE INSTANCE = clkgen
    PARAMETER CLK_FREQ = 40000000, IO_IS=clk_freq, RANGE=(40000000) # 40 MHz
    PORT SYSCLK = CLK_40MHZ_OSC, IO_IS=ext_clk
END

# Defines the reset interface.  Currently set to use first push button
BEGIN IO_INTERFACE
    ATTRIBUTE IOTYPE = XIL_RESET_V1
    ATTRIBUTE INSTANCE = rst_0
    PARAMETER RST_POLARITY =1, IO_IS=polarity, VALUE_NOTE=Active HIGH
    PORT INIT =  CONN_INIT_INIT, IO_IS=ext_rst
END

BEGIN IO_INTERFACE
    ATTRIBUTE IOTYPE = WARP_V4_USERIO_V1
    ATTRIBUTE INSTANCE = warp_v4_userio_all
    PARAMETER C_ADDRESS_0 = 0x40, IO_IS = address_0
    PARAMETER C_ADDRESS_1 = 0x42, IO_IS = address_1
    PARAMETER C_I2C_DIVIDER = 0x40, IO_IS = i2c_divider
    
    PORT LED0 = CONN_LEDs_LED0, IO_IS = leds_out[0]
    PORT LED1 = CONN_LEDs_LED1, IO_IS = leds_out[1]
    PORT LED2 = CONN_LEDs_LED2, IO_IS = leds_out[2]
    PORT LED3 = CONN_LEDs_LED3, IO_IS = leds_out[3]
    PORT LED4 = CONN_LEDs_LED4, IO_IS = leds_out[4]
    PORT LED5 = CONN_LEDs_LED5, IO_IS = leds_out[5]
    PORT LED6 = CONN_LEDs_LED6, IO_IS = leds_out[6]
    PORT LED7 = CONN_LEDs_LED7, IO_IS = leds_out[7]
    
    PORT SW_0 = SW_0, IO_IS = dipsw_in[0]
    PORT SW_1 = SW_1, IO_IS = dipsw_in[1]
    PORT SW_2 = SW_2, IO_IS = dipsw_in[2]
    PORT SW_3 = SW_3, IO_IS = dipsw_in[3]

    PORT PUSHU = CONN_PUSHU, IO_IS = pb_in[0]
    PORT PUSHL = CONN_PUSHL, IO_IS = pb_in[1]
    PORT PUSHR = CONN_PUSHR, IO_IS = pb_in[2]
    PORT PUSHC = CONN_PUSHC, IO_IS = pb_in[3]

    PORT SCL = iic_scl, IO_IS = scl
    PORT SDA = iic_sda, IO_IS = sda
END

# This is the serial port 0.
BEGIN IO_INTERFACE
    ATTRIBUTE IOTYPE = XIL_UART_V1
    ATTRIBUTE INSTANCE = rs232_db9
    PORT RXD = CONN_RXD_DB9, IO_IS=serial_in
    PORT TXD = CONN_TXD_DB9, IO_IS=serial_out
END 

# This is the serial port 1.
BEGIN IO_INTERFACE
    ATTRIBUTE IOTYPE = XIL_UART_V1
    ATTRIBUTE INSTANCE = rs232_usb
    PORT RXD = CONN_RXD_USB, IO_IS=serial_in
    PORT TXD = CONN_TXD_USB, IO_IS=serial_out
END 

# SystemACE Compact Flash microprocessor interface
BEGIN IO_INTERFACE
    ATTRIBUTE IOTYPE = XIL_SYSACE_V1
    ATTRIBUTE INSTANCE = sysace_compactflash
    PARAMETER C_MEM_WIDTH =8, IO_IS=mem_data_bus_width  
    PORT X104_5_OUT = sysace_clk, IO_IS=clk_in
    PORT X104_1_OE = sysace_clk_oe_n, IO_IS=clk_enable_n, INITIALVAL = VCC 
    PORT MPA00 = sysace_mpa_0, IO_IS = address[0] 
    PORT MPA01 = sysace_mpa_1, IO_IS = address[1] 
    PORT MPA02 = sysace_mpa_2, IO_IS = address[2] 
    PORT MPA03 = sysace_mpa_3, IO_IS = address[3] 
    PORT MPA04 = sysace_mpa_4, IO_IS = address[4] 
    PORT MPA05 = sysace_mpa_5, IO_IS = address[5] 
    PORT MPA06 = sysace_mpa_6, IO_IS = address[6] 
    PORT MPD00 = sysace_mpd_0, IO_IS = data[0]    
    PORT MPD01 = sysace_mpd_1, IO_IS = data[1]    
    PORT MPD02 = sysace_mpd_2, IO_IS = data[2]    
    PORT MPD03 = sysace_mpd_3, IO_IS = data[3]    
    PORT MPD04 = sysace_mpd_4, IO_IS = data[4]    
    PORT MPD05 = sysace_mpd_5, IO_IS = data[5]    
    PORT MPD06 = sysace_mpd_6, IO_IS = data[6]    
    PORT MPD07 = sysace_mpd_7, IO_IS = data[7]
    PORT MPCE  = sysace_mpce, IO_IS=chip_enable  
    PORT MPOE  = sysace_mpoe, IO_IS=output_enable
    PORT MPWE  = sysace_mpwe, IO_IS=write_enable 
    PORT MPIRQ = sysace_mpirq, IO_IS=intr_out     
END

# Ethernet MAC
BEGIN IO_INTERFACE
    ATTRIBUTE IOTYPE = XIL_TEMAC_V1
    ATTRIBUTE INSTANCE = TriMode_MAC_GMII
    ATTRIBUTE EXCLUSIVE =  Ethernet
    # hard_temac params
    PARAMETER C_PHY_TYPE = 1, IO_IS=C_PHY_TYPE
    PARAMETER C_EMAC1_PRESENT = 0, IO_IS=C_EMAC1_PRESENT
    # plb_temac params
    PARAMETER C_TEMAC_INST = 0, IO_IS=C_TEMAC_INST
    PARAMETER C_TEMAC_BOTH_USED = 0, IO_IS=C_TEMAC_BOTH_USED
    PARAMETER C_NUM_IDELAYCTRL = 2
    PARAMETER C_IDELAYCTRL_LOC = IDELAYCTRL_X1Y5-IDELAYCTRL_X1Y6
    # hard_temac ports
    PORT GMII_TXD_0_7 = GMII_TXD_0_7_s, IO_IS=GMII_TXD_0[7]
    PORT GMII_TXD_0_6 = GMII_TXD_0_6_s, IO_IS=GMII_TXD_0[6]
    PORT GMII_TXD_0_5 = GMII_TXD_0_5_s, IO_IS=GMII_TXD_0[5]
    PORT GMII_TXD_0_4 = GMII_TXD_0_4_s, IO_IS=GMII_TXD_0[4]
    PORT GMII_TXD_0_3 = GMII_TXD_0_3_s, IO_IS=GMII_TXD_0[3]
    PORT GMII_TXD_0_2 = GMII_TXD_0_2_s, IO_IS=GMII_TXD_0[2]
    PORT GMII_TXD_0_1 = GMII_TXD_0_1_s, IO_IS=GMII_TXD_0[1]
    PORT GMII_TXD_0_0 = GMII_TXD_0_0_s, IO_IS=GMII_TXD_0[0]
    PORT GMII_TX_EN_0 = GMII_TX_EN_0_s, IO_IS=GMII_TX_EN_0
    PORT GMII_TX_ER_0 = GMII_TX_ER_0_s, IO_IS=GMII_TX_ER_0
    PORT GMII_TX_CLK_0 = GMII_TX_CLK_0_s, IO_IS=GMII_TX_CLK_0
    PORT GMII_RXD_0_7 = GMII_RXD_0_7_s, IO_IS=GMII_RXD_0[7]
    PORT GMII_RXD_0_6 = GMII_RXD_0_6_s, IO_IS=GMII_RXD_0[6]
    PORT GMII_RXD_0_5 = GMII_RXD_0_5_s, IO_IS=GMII_RXD_0[5]
    PORT GMII_RXD_0_4 = GMII_RXD_0_4_s, IO_IS=GMII_RXD_0[4]
    PORT GMII_RXD_0_3 = GMII_RXD_0_3_s, IO_IS=GMII_RXD_0[3]
    PORT GMII_RXD_0_2 = GMII_RXD_0_2_s, IO_IS=GMII_RXD_0[2]
    PORT GMII_RXD_0_1 = GMII_RXD_0_1_s, IO_IS=GMII_RXD_0[1]
    PORT GMII_RXD_0_0 = GMII_RXD_0_0_s, IO_IS=GMII_RXD_0[0]
    PORT GMII_RX_DV_0 = GMII_RX_DV_0_s, IO_IS=GMII_RX_DV_0
    PORT GMII_RX_ER_0 = GMII_RX_ER_0_s, IO_IS=GMII_RX_ER_0
    PORT GMII_RX_CLK_0 = GMII_RX_CLK_0_s, IO_IS=GMII_RX_CLK_0
    PORT MII_TX_CLK_0 = MII_TX_CLK_0_s, IO_IS=MII_TX_CLK_0
    PORT GMII_COL_0 = GMII_COL_0_s, IO_IS=GMII_COL_0
    PORT GMII_CRS_0 = GMII_CRS_0_s, IO_IS=GMII_CRS_0
    PORT MDIO_0 = MDIO_0_s, IO_IS=MDIO_0
    PORT MDC_0 = MDC_0_s, IO_IS=MDC_0
    # plb_temac ports
    PORT PhyResetN = phy_rst_n_s, IO_IS=PhyResetN
END

# Clock board configurator
BEGIN IO_INTERFACE
    ATTRIBUTE IOTYPE = WARP_CLKBRD_CONFIG_V1
    ATTRIBUTE INSTANCE = clk_board_config

    PORT sys_clk = CLK_100MHZ_OSC
    PORT sys_rst = net_gnd
    PORT cfg_radio_dat_out = clk_board_radio_DO
    PORT cfg_radio_csb_out = clk_board_radio_CS
    PORT cfg_radio_en_out = clk_board_radio_EN
    PORT cfg_radio_clk_out = clk_board_radio_CLK
    PORT cfg_logic_dat_out = clk_board_logic_DO
    PORT cfg_logic_csb_out = clk_board_logic_CS
    PORT cfg_logic_en_out = clk_board_logic_EN
    PORT cfg_logic_clk_out = clk_board_logic_CLK
END

#   # 256MB DDR2 memory
#   BEGIN IO_INTERFACE
#       ATTRIBUTE IOTYPE = XIL_MEMORY_V1
#       ATTRIBUTE INSTANCE = DDR2_SDRAM_256MB
#       ATTRIBUTE EXCLUSIVE = ddr2memory
#       PARAMETER C_MEM_PARTNO = "MT4HTF3264H-667", IO_IS = C_MEM_PARTNO
#       PARAMETER C_BASEADDR = 0x00000000, IO_IS = C_BASEADDR
#       PARAMETER C_HIGHADDR = 0x0fffffff, IO_IS = C_HIGHADDR
#       PARAMETER C_MEM_TYPE = DDR2, IO_IS = C_MEM_TYPE
#       PARAMETER C_NUM_IDELAYCTRL = 4, IO_IS = C_NUM_IDELAYCTRL #4
#       PARAMETER C_IDELAYCTRL_LOC = IDELAYCTRL_X0Y0-IDELAYCTRL_X0Y1-IDELAYCTRL_X2Y1-IDELAYCTRL_X2Y0, IO_IS = C_IDELAYCTRL_LOC
#       PARAMETER C_MEM_DATA_WIDTH = 64, IO_IS = C_MEMD_DATA_WIDTH
#       PARAMETER C_MEM_DQS_WIDTH = 8, IO_IS = C_MEM_DQS_WIDTH
#       PARAMETER C_MEM_DM_WIDTH = 8, IO_IS = C_MEM_DM_WIDTH
#       
#       PORT DDR2_Addr_0 = ddr2_256mb_addr_0, IO_IS = ddr2_address[0]
#       PORT DDR2_Addr_1 = ddr2_256mb_addr_1, IO_IS = ddr2_address[1]
#       PORT DDR2_Addr_2 = ddr2_256mb_addr_2, IO_IS = ddr2_address[2]
#       PORT DDR2_Addr_3 = ddr2_256mb_addr_3, IO_IS = ddr2_address[3]
#       PORT DDR2_Addr_4 = ddr2_256mb_addr_4, IO_IS = ddr2_address[4]
#       PORT DDR2_Addr_5 = ddr2_256mb_addr_5, IO_IS = ddr2_address[5]
#       PORT DDR2_Addr_6 = ddr2_256mb_addr_6, IO_IS = ddr2_address[6]
#       PORT DDR2_Addr_7 = ddr2_256mb_addr_7, IO_IS = ddr2_address[7]
#       PORT DDR2_Addr_8 = ddr2_256mb_addr_8, IO_IS = ddr2_address[8]
#       PORT DDR2_Addr_9 = ddr2_256mb_addr_9, IO_IS = ddr2_address[9]
#       PORT DDR2_Addr_10 = ddr2_256mb_addr_10, IO_IS = ddr2_address[10]
#       PORT DDR2_Addr_11 = ddr2_256mb_addr_11, IO_IS = ddr2_address[11]
#       PORT DDR2_Addr_12 = ddr2_256mb_addr_12, IO_IS = ddr2_address[12]
#       PORT DDR2_BankAddr_0 = ddr2_256mb_bankaddr_0, IO_IS = ddr2_BankAddr[0]
#       PORT DDR2_BankAddr_1 = ddr2_256mb_bankaddr_1, IO_IS = ddr2_BankAddr[1]
#       PORT DDR2_CASn = ddr2_256mb_casn, IO_IS = ddr2_col_addr_select
#       PORT DDR2_CKE_0 = ddr2_256mb_cke_0, IO_IS = ddr2_clk_enable[0]
#   #   PORT DDR2_CKE_1 = ddr2_256mb_cke_1, IO_IS = ddr2_clk_enable[1]
#       PORT DDR2_CSn_0 = ddr2_256mb_csn_0, IO_IS = ddr2_chip_select[0]
#   #   PORT DDR2_CSn_1 = ddr2_256mb_csn_1, IO_IS = ddr2_chip_select[1]
#       PORT DDR2_RASn = ddr2_256mb_rasn, IO_IS = ddr2_row_addr_select
#       PORT DDR2_WEn = ddr2_256mb_wen, IO_IS = ddr2_write_enable
#       PORT DDR2_DM_0 = ddr2_256mb_dm_0, IO_IS = ddr2_data_mask[0]
#       PORT DDR2_DM_1 = ddr2_256mb_dm_1, IO_IS = ddr2_data_mask[1]
#       PORT DDR2_DM_2 = ddr2_256mb_dm_2, IO_IS = ddr2_data_mask[2]
#       PORT DDR2_DM_3 = ddr2_256mb_dm_3, IO_IS = ddr2_data_mask[3]
#       PORT DDR2_DM_4 = ddr2_256mb_dm_4, IO_IS = ddr2_data_mask[4]
#       PORT DDR2_DM_5 = ddr2_256mb_dm_5, IO_IS = ddr2_data_mask[5]
#       PORT DDR2_DM_6 = ddr2_256mb_dm_6, IO_IS = ddr2_data_mask[6]
#       PORT DDR2_DM_7 = ddr2_256mb_dm_7, IO_IS = ddr2_data_mask[7]
#       PORT DDR2_DQS_0 = ddr2_256mb_dqs_0, IO_IS = ddr2_data_strobe[0]
#       PORT DDR2_DQS_1 = ddr2_256mb_dqs_1, IO_IS = ddr2_data_strobe[1]
#       PORT DDR2_DQS_2 = ddr2_256mb_dqs_2, IO_IS = ddr2_data_strobe[2]
#       PORT DDR2_DQS_3 = ddr2_256mb_dqs_3, IO_IS = ddr2_data_strobe[3]
#       PORT DDR2_DQS_4 = ddr2_256mb_dqs_4, IO_IS = ddr2_data_strobe[4]
#       PORT DDR2_DQS_5 = ddr2_256mb_dqs_5, IO_IS = ddr2_data_strobe[5]
#       PORT DDR2_DQS_6 = ddr2_256mb_dqs_6, IO_IS = ddr2_data_strobe[6]
#       PORT DDR2_DQS_7 = ddr2_256mb_dqs_7, IO_IS = ddr2_data_strobe[7]
#       PORT DDR2_DQSn_0 = ddr2_256mb_dqsn_0, IO_IS = ddr2_data_strobe_n[0]
#       PORT DDR2_DQSn_1 = ddr2_256mb_dqsn_1, IO_IS = ddr2_data_strobe_n[1]
#       PORT DDR2_DQSn_2 = ddr2_256mb_dqsn_2, IO_IS = ddr2_data_strobe_n[2]
#       PORT DDR2_DQSn_3 = ddr2_256mb_dqsn_3, IO_IS = ddr2_data_strobe_n[3]
#       PORT DDR2_DQSn_4 = ddr2_256mb_dqsn_4, IO_IS = ddr2_data_strobe_n[4]
#       PORT DDR2_DQSn_5 = ddr2_256mb_dqsn_5, IO_IS = ddr2_data_strobe_n[5]
#       PORT DDR2_DQSn_6 = ddr2_256mb_dqsn_6, IO_IS = ddr2_data_strobe_n[6]
#       PORT DDR2_DQSn_7 = ddr2_256mb_dqsn_7, IO_IS = ddr2_data_strobe_n[7]
#       PORT DDR2_DQ_0 = ddr2_256mb_dq_0, IO_IS = ddr2_data[0]
#       PORT DDR2_DQ_1 = ddr2_256mb_dq_1, IO_IS = ddr2_data[1]
#       PORT DDR2_DQ_2 = ddr2_256mb_dq_2, IO_IS = ddr2_data[2]
#       PORT DDR2_DQ_3 = ddr2_256mb_dq_3, IO_IS = ddr2_data[3]
#       PORT DDR2_DQ_4 = ddr2_256mb_dq_4, IO_IS = ddr2_data[4]
#       PORT DDR2_DQ_5 = ddr2_256mb_dq_5, IO_IS = ddr2_data[5]
#       PORT DDR2_DQ_6 = ddr2_256mb_dq_6, IO_IS = ddr2_data[6]
#       PORT DDR2_DQ_7 = ddr2_256mb_dq_7, IO_IS = ddr2_data[7]
#       PORT DDR2_DQ_8 = ddr2_256mb_dq_8, IO_IS = ddr2_data[8]
#       PORT DDR2_DQ_9 = ddr2_256mb_dq_9, IO_IS = ddr2_data[9]
#       PORT DDR2_DQ_10 = ddr2_256mb_dq_10, IO_IS = ddr2_data[10]
#       PORT DDR2_DQ_11 = ddr2_256mb_dq_11, IO_IS = ddr2_data[11]
#       PORT DDR2_DQ_12 = ddr2_256mb_dq_12, IO_IS = ddr2_data[12]
#       PORT DDR2_DQ_13 = ddr2_256mb_dq_13, IO_IS = ddr2_data[13]
#       PORT DDR2_DQ_14 = ddr2_256mb_dq_14, IO_IS = ddr2_data[14]
#       PORT DDR2_DQ_15 = ddr2_256mb_dq_15, IO_IS = ddr2_data[15]
#       PORT DDR2_DQ_16 = ddr2_256mb_dq_16, IO_IS = ddr2_data[16]
#       PORT DDR2_DQ_17 = ddr2_256mb_dq_17, IO_IS = ddr2_data[17]
#       PORT DDR2_DQ_18 = ddr2_256mb_dq_18, IO_IS = ddr2_data[18]
#       PORT DDR2_DQ_19 = ddr2_256mb_dq_19, IO_IS = ddr2_data[19]
#       PORT DDR2_DQ_20 = ddr2_256mb_dq_20, IO_IS = ddr2_data[20]
#       PORT DDR2_DQ_21 = ddr2_256mb_dq_21, IO_IS = ddr2_data[21]
#       PORT DDR2_DQ_22 = ddr2_256mb_dq_22, IO_IS = ddr2_data[22]
#       PORT DDR2_DQ_23 = ddr2_256mb_dq_23, IO_IS = ddr2_data[23]
#       PORT DDR2_DQ_24 = ddr2_256mb_dq_24, IO_IS = ddr2_data[24]
#       PORT DDR2_DQ_25 = ddr2_256mb_dq_25, IO_IS = ddr2_data[25]
#       PORT DDR2_DQ_26 = ddr2_256mb_dq_26, IO_IS = ddr2_data[26]
#       PORT DDR2_DQ_27 = ddr2_256mb_dq_27, IO_IS = ddr2_data[27]
#       PORT DDR2_DQ_28 = ddr2_256mb_dq_28, IO_IS = ddr2_data[28]
#       PORT DDR2_DQ_29 = ddr2_256mb_dq_29, IO_IS = ddr2_data[29]
#       PORT DDR2_DQ_30 = ddr2_256mb_dq_30, IO_IS = ddr2_data[30]
#       PORT DDR2_DQ_31 = ddr2_256mb_dq_31, IO_IS = ddr2_data[31]
#       PORT DDR2_DQ_32 = ddr2_256mb_dq_32, IO_IS = ddr2_data[32]
#       PORT DDR2_DQ_33 = ddr2_256mb_dq_33, IO_IS = ddr2_data[33]
#       PORT DDR2_DQ_34 = ddr2_256mb_dq_34, IO_IS = ddr2_data[34]
#       PORT DDR2_DQ_35 = ddr2_256mb_dq_35, IO_IS = ddr2_data[35]
#       PORT DDR2_DQ_36 = ddr2_256mb_dq_36, IO_IS = ddr2_data[36]
#       PORT DDR2_DQ_37 = ddr2_256mb_dq_37, IO_IS = ddr2_data[37]
#       PORT DDR2_DQ_38 = ddr2_256mb_dq_38, IO_IS = ddr2_data[38]
#       PORT DDR2_DQ_39 = ddr2_256mb_dq_39, IO_IS = ddr2_data[39]
#       PORT DDR2_DQ_40 = ddr2_256mb_dq_40, IO_IS = ddr2_data[40]
#       PORT DDR2_DQ_41 = ddr2_256mb_dq_41, IO_IS = ddr2_data[41]
#       PORT DDR2_DQ_42 = ddr2_256mb_dq_42, IO_IS = ddr2_data[42]
#       PORT DDR2_DQ_43 = ddr2_256mb_dq_43, IO_IS = ddr2_data[43]
#       PORT DDR2_DQ_44 = ddr2_256mb_dq_44, IO_IS = ddr2_data[44]
#       PORT DDR2_DQ_45 = ddr2_256mb_dq_45, IO_IS = ddr2_data[45]
#       PORT DDR2_DQ_46 = ddr2_256mb_dq_46, IO_IS = ddr2_data[46]
#       PORT DDR2_DQ_47 = ddr2_256mb_dq_47, IO_IS = ddr2_data[47]
#       PORT DDR2_DQ_48 = ddr2_256mb_dq_48, IO_IS = ddr2_data[48]
#       PORT DDR2_DQ_49 = ddr2_256mb_dq_49, IO_IS = ddr2_data[49]
#       PORT DDR2_DQ_50 = ddr2_256mb_dq_50, IO_IS = ddr2_data[50]
#       PORT DDR2_DQ_51 = ddr2_256mb_dq_51, IO_IS = ddr2_data[51]
#       PORT DDR2_DQ_52 = ddr2_256mb_dq_52, IO_IS = ddr2_data[52]
#       PORT DDR2_DQ_53 = ddr2_256mb_dq_53, IO_IS = ddr2_data[53]
#       PORT DDR2_DQ_54 = ddr2_256mb_dq_54, IO_IS = ddr2_data[54]
#       PORT DDR2_DQ_55 = ddr2_256mb_dq_55, IO_IS = ddr2_data[55]
#       PORT DDR2_DQ_56 = ddr2_256mb_dq_56, IO_IS = ddr2_data[56]
#       PORT DDR2_DQ_57 = ddr2_256mb_dq_57, IO_IS = ddr2_data[57]
#       PORT DDR2_DQ_58 = ddr2_256mb_dq_58, IO_IS = ddr2_data[58]
#       PORT DDR2_DQ_59 = ddr2_256mb_dq_59, IO_IS = ddr2_data[59]
#       PORT DDR2_DQ_60 = ddr2_256mb_dq_60, IO_IS = ddr2_data[60]
#       PORT DDR2_DQ_61 = ddr2_256mb_dq_61, IO_IS = ddr2_data[61]
#       PORT DDR2_DQ_62 = ddr2_256mb_dq_62, IO_IS = ddr2_data[62]
#       PORT DDR2_DQ_63 = ddr2_256mb_dq_63, IO_IS = ddr2_data[63]
#   #   PORT DDR2_Sleep = net_gnd, IO_IS = ddr_sleep
#   #   PORT DDR2_WakeUp = net_gnd, IO_IS = ddr_wakeup
#   #   PORT DDR2_Init_done = net_gnd, IO_IS = ddr_init_done
#       PORT DDR2_Clk_0 = ddr2_256mb_clk_0, IO_IS = ddr2_clk[0]
#       PORT DDR2_Clk_1 = ddr2_256mb_clk_1, IO_IS = ddr2_clk[1]
#       PORT DDR2_Clkn_0 = ddr2_256mb_clkn_0, IO_IS = ddr2_clk_n[0]
#       PORT DDR2_Clkn_1 = ddr2_256mb_clkn_1, IO_IS = ddr2_clk_n[1]
#       PORT DDR2_ODT = ddr2_256mb_odt, IO_IS = ddr2_odt
#   END

# 2GB DDR2 memory
BEGIN IO_INTERFACE
    ATTRIBUTE IOTYPE = XIL_MEMORY_V1
    ATTRIBUTE INSTANCE = DDR2_SDRAM_2GB
    ATTRIBUTE EXCLUSIVE = ddr2memory
    PARAMETER C_MEM_PARTNO = "MT16HTF25664H-667", IO_IS = C_MEM_PARTNO
    PARAMETER C_BASEADDR = 0x00000000, IO_IS = C_BASEADDR
    PARAMETER C_HIGHADDR = 0x7fffffff, IO_IS = C_HIGHADDR
    PARAMETER C_MEM_TYPE = DDR2, IO_IS = C_MEM_TYPE
    PARAMETER C_NUM_IDELAYCTRL = 4, IO_IS = C_NUM_IDELAYCTRL #4
    PARAMETER C_IDELAYCTRL_LOC = IDELAYCTRL_X0Y0-IDELAYCTRL_X0Y1-IDELAYCTRL_X2Y1-IDELAYCTRL_X2Y0, IO_IS = C_IDELAYCTRL_LOC
    PARAMETER C_MEM_DATA_WIDTH = 64, IO_IS = C_MEMD_DATA_WIDTH
    PARAMETER C_MEM_DQS_WIDTH = 8, IO_IS = C_MEM_DQS_WIDTH
    PARAMETER C_MEM_DM_WIDTH = 8, IO_IS = C_MEM_DM_WIDTH
    PARAMETER C_MEM_ADDR_WIDTH = 14, IO_IS = C_MEM_ADDR_WIDTH
    PARAMETER C_MEM_BANKADDR_WIDTH = 3, IO_IS = C_MEM_BANKADDR_WIDTH
    
    PORT DDR2_Addr_0 = ddr2_2gb_addr_0, IO_IS = ddr2_address[0]
    PORT DDR2_Addr_1 = ddr2_2gb_addr_1, IO_IS = ddr2_address[1]
    PORT DDR2_Addr_2 = ddr2_2gb_addr_2, IO_IS = ddr2_address[2]
    PORT DDR2_Addr_3 = ddr2_2gb_addr_3, IO_IS = ddr2_address[3]
    PORT DDR2_Addr_4 = ddr2_2gb_addr_4, IO_IS = ddr2_address[4]
    PORT DDR2_Addr_5 = ddr2_2gb_addr_5, IO_IS = ddr2_address[5]
    PORT DDR2_Addr_6 = ddr2_2gb_addr_6, IO_IS = ddr2_address[6]
    PORT DDR2_Addr_7 = ddr2_2gb_addr_7, IO_IS = ddr2_address[7]
    PORT DDR2_Addr_8 = ddr2_2gb_addr_8, IO_IS = ddr2_address[8]
    PORT DDR2_Addr_9 = ddr2_2gb_addr_9, IO_IS = ddr2_address[9]
    PORT DDR2_Addr_10 = ddr2_2gb_addr_10, IO_IS = ddr2_address[10]
    PORT DDR2_Addr_11 = ddr2_2gb_addr_11, IO_IS = ddr2_address[11]
    PORT DDR2_Addr_12 = ddr2_2gb_addr_12, IO_IS = ddr2_address[12]
    PORT DDR2_Addr_13 = ddr2_2gb_addr_13, IO_IS = ddr2_address[13]
    PORT DDR2_BankAddr_0 = ddr2_2gb_bankaddr_0, IO_IS = ddr2_BankAddr[0]
    PORT DDR2_BankAddr_1 = ddr2_2gb_bankaddr_1, IO_IS = ddr2_BankAddr[1]
    PORT DDR2_BankAddr_2 = ddr2_2gb_bankaddr_2, IO_IS = ddr2_BankAddr[2]
    PORT DDR2_CASn = ddr2_2gb_casn, IO_IS = ddr2_col_addr_select
    PORT DDR2_CKE_0 = ddr2_2gb_cke_0, IO_IS = ddr2_clk_enable[0]
    PORT DDR2_CKE_1 = ddr2_2gb_cke_1, IO_IS = ddr2_clk_enable[1]
    PORT DDR2_CSn_0 = ddr2_2gb_csn_0, IO_IS = ddr2_chip_select[0]
    PORT DDR2_CSn_1 = ddr2_2gb_csn_1, IO_IS = ddr2_chip_select[1]
    PORT DDR2_RASn = ddr2_2gb_rasn, IO_IS = ddr2_row_addr_select
    PORT DDR2_WEn = ddr2_2gb_wen, IO_IS = ddr2_write_enable
    PORT DDR2_DM_0 = ddr2_2gb_dm_0, IO_IS = ddr2_data_mask[0]
    PORT DDR2_DM_1 = ddr2_2gb_dm_1, IO_IS = ddr2_data_mask[1]
    PORT DDR2_DM_2 = ddr2_2gb_dm_2, IO_IS = ddr2_data_mask[2]
    PORT DDR2_DM_3 = ddr2_2gb_dm_3, IO_IS = ddr2_data_mask[3]
    PORT DDR2_DM_4 = ddr2_2gb_dm_4, IO_IS = ddr2_data_mask[4]
    PORT DDR2_DM_5 = ddr2_2gb_dm_5, IO_IS = ddr2_data_mask[5]
    PORT DDR2_DM_6 = ddr2_2gb_dm_6, IO_IS = ddr2_data_mask[6]
    PORT DDR2_DM_7 = ddr2_2gb_dm_7, IO_IS = ddr2_data_mask[7]
    PORT DDR2_DQS_0 = ddr2_2gb_dqs_0, IO_IS = ddr2_data_strobe[0]
    PORT DDR2_DQS_1 = ddr2_2gb_dqs_1, IO_IS = ddr2_data_strobe[1]
    PORT DDR2_DQS_2 = ddr2_2gb_dqs_2, IO_IS = ddr2_data_strobe[2]
    PORT DDR2_DQS_3 = ddr2_2gb_dqs_3, IO_IS = ddr2_data_strobe[3]
    PORT DDR2_DQS_4 = ddr2_2gb_dqs_4, IO_IS = ddr2_data_strobe[4]
    PORT DDR2_DQS_5 = ddr2_2gb_dqs_5, IO_IS = ddr2_data_strobe[5]
    PORT DDR2_DQS_6 = ddr2_2gb_dqs_6, IO_IS = ddr2_data_strobe[6]
    PORT DDR2_DQS_7 = ddr2_2gb_dqs_7, IO_IS = ddr2_data_strobe[7]
    PORT DDR2_DQSn_0 = ddr2_2gb_dqsn_0, IO_IS = ddr2_data_strobe_n[0]
    PORT DDR2_DQSn_1 = ddr2_2gb_dqsn_1, IO_IS = ddr2_data_strobe_n[1]
    PORT DDR2_DQSn_2 = ddr2_2gb_dqsn_2, IO_IS = ddr2_data_strobe_n[2]
    PORT DDR2_DQSn_3 = ddr2_2gb_dqsn_3, IO_IS = ddr2_data_strobe_n[3]
    PORT DDR2_DQSn_4 = ddr2_2gb_dqsn_4, IO_IS = ddr2_data_strobe_n[4]
    PORT DDR2_DQSn_5 = ddr2_2gb_dqsn_5, IO_IS = ddr2_data_strobe_n[5]
    PORT DDR2_DQSn_6 = ddr2_2gb_dqsn_6, IO_IS = ddr2_data_strobe_n[6]
    PORT DDR2_DQSn_7 = ddr2_2gb_dqsn_7, IO_IS = ddr2_data_strobe_n[7]
    PORT DDR2_DQ_0 = ddr2_2gb_dq_0, IO_IS = ddr2_data[0]
    PORT DDR2_DQ_1 = ddr2_2gb_dq_1, IO_IS = ddr2_data[1]
    PORT DDR2_DQ_2 = ddr2_2gb_dq_2, IO_IS = ddr2_data[2]
    PORT DDR2_DQ_3 = ddr2_2gb_dq_3, IO_IS = ddr2_data[3]
    PORT DDR2_DQ_4 = ddr2_2gb_dq_4, IO_IS = ddr2_data[4]
    PORT DDR2_DQ_5 = ddr2_2gb_dq_5, IO_IS = ddr2_data[5]
    PORT DDR2_DQ_6 = ddr2_2gb_dq_6, IO_IS = ddr2_data[6]
    PORT DDR2_DQ_7 = ddr2_2gb_dq_7, IO_IS = ddr2_data[7]
    PORT DDR2_DQ_8 = ddr2_2gb_dq_8, IO_IS = ddr2_data[8]
    PORT DDR2_DQ_9 = ddr2_2gb_dq_9, IO_IS = ddr2_data[9]
    PORT DDR2_DQ_10 = ddr2_2gb_dq_10, IO_IS = ddr2_data[10]
    PORT DDR2_DQ_11 = ddr2_2gb_dq_11, IO_IS = ddr2_data[11]
    PORT DDR2_DQ_12 = ddr2_2gb_dq_12, IO_IS = ddr2_data[12]
    PORT DDR2_DQ_13 = ddr2_2gb_dq_13, IO_IS = ddr2_data[13]
    PORT DDR2_DQ_14 = ddr2_2gb_dq_14, IO_IS = ddr2_data[14]
    PORT DDR2_DQ_15 = ddr2_2gb_dq_15, IO_IS = ddr2_data[15]
    PORT DDR2_DQ_16 = ddr2_2gb_dq_16, IO_IS = ddr2_data[16]
    PORT DDR2_DQ_17 = ddr2_2gb_dq_17, IO_IS = ddr2_data[17]
    PORT DDR2_DQ_18 = ddr2_2gb_dq_18, IO_IS = ddr2_data[18]
    PORT DDR2_DQ_19 = ddr2_2gb_dq_19, IO_IS = ddr2_data[19]
    PORT DDR2_DQ_20 = ddr2_2gb_dq_20, IO_IS = ddr2_data[20]
    PORT DDR2_DQ_21 = ddr2_2gb_dq_21, IO_IS = ddr2_data[21]
    PORT DDR2_DQ_22 = ddr2_2gb_dq_22, IO_IS = ddr2_data[22]
    PORT DDR2_DQ_23 = ddr2_2gb_dq_23, IO_IS = ddr2_data[23]
    PORT DDR2_DQ_24 = ddr2_2gb_dq_24, IO_IS = ddr2_data[24]
    PORT DDR2_DQ_25 = ddr2_2gb_dq_25, IO_IS = ddr2_data[25]
    PORT DDR2_DQ_26 = ddr2_2gb_dq_26, IO_IS = ddr2_data[26]
    PORT DDR2_DQ_27 = ddr2_2gb_dq_27, IO_IS = ddr2_data[27]
    PORT DDR2_DQ_28 = ddr2_2gb_dq_28, IO_IS = ddr2_data[28]
    PORT DDR2_DQ_29 = ddr2_2gb_dq_29, IO_IS = ddr2_data[29]
    PORT DDR2_DQ_30 = ddr2_2gb_dq_30, IO_IS = ddr2_data[30]
    PORT DDR2_DQ_31 = ddr2_2gb_dq_31, IO_IS = ddr2_data[31]
    PORT DDR2_DQ_32 = ddr2_2gb_dq_32, IO_IS = ddr2_data[32]
    PORT DDR2_DQ_33 = ddr2_2gb_dq_33, IO_IS = ddr2_data[33]
    PORT DDR2_DQ_34 = ddr2_2gb_dq_34, IO_IS = ddr2_data[34]
    PORT DDR2_DQ_35 = ddr2_2gb_dq_35, IO_IS = ddr2_data[35]
    PORT DDR2_DQ_36 = ddr2_2gb_dq_36, IO_IS = ddr2_data[36]
    PORT DDR2_DQ_37 = ddr2_2gb_dq_37, IO_IS = ddr2_data[37]
    PORT DDR2_DQ_38 = ddr2_2gb_dq_38, IO_IS = ddr2_data[38]
    PORT DDR2_DQ_39 = ddr2_2gb_dq_39, IO_IS = ddr2_data[39]
    PORT DDR2_DQ_40 = ddr2_2gb_dq_40, IO_IS = ddr2_data[40]
    PORT DDR2_DQ_41 = ddr2_2gb_dq_41, IO_IS = ddr2_data[41]
    PORT DDR2_DQ_42 = ddr2_2gb_dq_42, IO_IS = ddr2_data[42]
    PORT DDR2_DQ_43 = ddr2_2gb_dq_43, IO_IS = ddr2_data[43]
    PORT DDR2_DQ_44 = ddr2_2gb_dq_44, IO_IS = ddr2_data[44]
    PORT DDR2_DQ_45 = ddr2_2gb_dq_45, IO_IS = ddr2_data[45]
    PORT DDR2_DQ_46 = ddr2_2gb_dq_46, IO_IS = ddr2_data[46]
    PORT DDR2_DQ_47 = ddr2_2gb_dq_47, IO_IS = ddr2_data[47]
    PORT DDR2_DQ_48 = ddr2_2gb_dq_48, IO_IS = ddr2_data[48]
    PORT DDR2_DQ_49 = ddr2_2gb_dq_49, IO_IS = ddr2_data[49]
    PORT DDR2_DQ_50 = ddr2_2gb_dq_50, IO_IS = ddr2_data[50]
    PORT DDR2_DQ_51 = ddr2_2gb_dq_51, IO_IS = ddr2_data[51]
    PORT DDR2_DQ_52 = ddr2_2gb_dq_52, IO_IS = ddr2_data[52]
    PORT DDR2_DQ_53 = ddr2_2gb_dq_53, IO_IS = ddr2_data[53]
    PORT DDR2_DQ_54 = ddr2_2gb_dq_54, IO_IS = ddr2_data[54]
    PORT DDR2_DQ_55 = ddr2_2gb_dq_55, IO_IS = ddr2_data[55]
    PORT DDR2_DQ_56 = ddr2_2gb_dq_56, IO_IS = ddr2_data[56]
    PORT DDR2_DQ_57 = ddr2_2gb_dq_57, IO_IS = ddr2_data[57]
    PORT DDR2_DQ_58 = ddr2_2gb_dq_58, IO_IS = ddr2_data[58]
    PORT DDR2_DQ_59 = ddr2_2gb_dq_59, IO_IS = ddr2_data[59]
    PORT DDR2_DQ_60 = ddr2_2gb_dq_60, IO_IS = ddr2_data[60]
    PORT DDR2_DQ_61 = ddr2_2gb_dq_61, IO_IS = ddr2_data[61]
    PORT DDR2_DQ_62 = ddr2_2gb_dq_62, IO_IS = ddr2_data[62]
    PORT DDR2_DQ_63 = ddr2_2gb_dq_63, IO_IS = ddr2_data[63]
#   PORT DDR2_Sleep = net_gnd, IO_IS = ddr_sleep
#   PORT DDR2_WakeUp = net_gnd, IO_IS = ddr_wakeup
#   PORT DDR2_Init_done = net_gnd, IO_IS = ddr_init_done
    PORT DDR2_Clk_0 = ddr2_2gb_clk_0, IO_IS = ddr2_clk[0]
    PORT DDR2_Clk_1 = ddr2_2gb_clk_1, IO_IS = ddr2_clk[1]
    PORT DDR2_Clkn_0 = ddr2_2gb_clkn_0, IO_IS = ddr2_clk_n[0]
    PORT DDR2_Clkn_1 = ddr2_2gb_clkn_1, IO_IS = ddr2_clk_n[1]
    PORT DDR2_ODT_0 = ddr2_2gb_odt_0, IO_IS = ddr2_odt[0]
    PORT DDR2_ODT_1 = ddr2_2gb_odt_1, IO_IS = ddr2_odt[1]
END


# Radio Controller
BEGIN IO_INTERFACE
    ATTRIBUTE IOTYPE = WARP_RADIOCONTROLLER_V1
    ATTRIBUTE INSTANCE = radio_controller_0
    ATTRIBUTE ALERT = 'This peripheral and at least one radio_bridge must be enabled to use the WARP radio interfaces.'

    #Common SPI clock and data outputs
    PORT controller_logic_clk = controller_logic_clk
    PORT spi_clk = controller_spi_clk
    PORT data_out = controller_spi_data

    #SPI radio chip selects
    PORT radio1_cs = controller_radio1_cs
    PORT radio2_cs = controller_radio2_cs
    PORT radio3_cs = controller_radio3_cs
    PORT radio4_cs = controller_radio4_cs

    #SPI DAC chip selects
    PORT dac1_cs = controller_dac1_cs
    PORT dac2_cs = controller_dac2_cs
    PORT dac3_cs = controller_dac3_cs
    PORT dac4_cs = controller_dac4_cs

    #######################
    # Slot #1 Radio Ports #
    #######################
    PORT radio1_SHDN = controller_radio1_SHDN
    PORT radio1_TxEn = controller_radio1_TxEn
    PORT radio1_RxEn = controller_radio1_RxEn
    PORT radio1_RxHP = controller_radio1_RxHP
    PORT radio1_LD = controller_radio1_LD
    PORT radio1_24PA = controller_radio1_24PA
    PORT radio1_5PA = controller_radio1_5PA
    PORT radio1_ANTSW0 = controller_radio1_ANTSW0, IO_IS = radio1_antsw[0]
    PORT radio1_ANTSW1 = controller_radio1_ANTSW1, IO_IS = radio1_antsw[1]
    PORT radio1_LED0 = controller_radio1_LED0, IO_IS = radio1_LED[0]
    PORT radio1_LED1 = controller_radio1_LED1, IO_IS = radio1_LED[1]
    PORT radio1_LED2 = controller_radio1_LED2, IO_IS = radio1_LED[2]
    PORT radio1_ADC_RX_DCS = controller_radio1_RX_ADC_DCS
    PORT radio1_ADC_RX_DFS = controller_radio1_RX_ADC_DFS
    PORT radio1_ADC_RX_OTRA = controller_radio1_RX_ADC_OTRA
    PORT radio1_ADC_RX_OTRB = controller_radio1_RX_ADC_OTRB
    PORT radio1_ADC_RX_PWDNA = controller_radio1_RX_ADC_PWDNA
    PORT radio1_ADC_RX_PWDNB = controller_radio1_RX_ADC_PWDNB
    PORT radio1_DIPSW0 = controller_radio1_DIPSW0, IO_IS = radio1_DIPSW[0]
    PORT radio1_DIPSW1 = controller_radio1_DIPSW1, IO_IS = radio1_DIPSW[1]
    PORT radio1_DIPSW2 = controller_radio1_DIPSW2, IO_IS = radio1_DIPSW[2]
    PORT radio1_DIPSW3 = controller_radio1_DIPSW3, IO_IS = radio1_DIPSW[3]
    PORT radio1_RSSI_ADC_CLAMP = controller_radio1_RSSI_ADC_CLAMP
    PORT radio1_RSSI_ADC_HIZ = controller_radio1_RSSI_ADC_HIZ
    PORT radio1_RSSI_ADC_OTR = controller_radio1_RSSI_ADC_OTR
    PORT radio1_RSSI_ADC_SLEEP = controller_radio1_RSSI_ADC_SLEEP
    PORT radio1_RSSI_ADC_D0 = controller_radio1_RSSI_ADC_D0, IO_IS = radio1_RSSI_ADC_D[0]
    PORT radio1_RSSI_ADC_D1 = controller_radio1_RSSI_ADC_D1, IO_IS = radio1_RSSI_ADC_D[1]
    PORT radio1_RSSI_ADC_D2 = controller_radio1_RSSI_ADC_D2, IO_IS = radio1_RSSI_ADC_D[2]
    PORT radio1_RSSI_ADC_D3 = controller_radio1_RSSI_ADC_D3, IO_IS = radio1_RSSI_ADC_D[3]
    PORT radio1_RSSI_ADC_D4 = controller_radio1_RSSI_ADC_D4, IO_IS = radio1_RSSI_ADC_D[4]
    PORT radio1_RSSI_ADC_D5 = controller_radio1_RSSI_ADC_D5, IO_IS = radio1_RSSI_ADC_D[5]
    PORT radio1_RSSI_ADC_D6 = controller_radio1_RSSI_ADC_D6, IO_IS = radio1_RSSI_ADC_D[6]
    PORT radio1_RSSI_ADC_D7 = controller_radio1_RSSI_ADC_D7, IO_IS = radio1_RSSI_ADC_D[7]
    PORT radio1_RSSI_ADC_D8 = controller_radio1_RSSI_ADC_D8, IO_IS = radio1_RSSI_ADC_D[8]
    PORT radio1_RSSI_ADC_D9 = controller_radio1_RSSI_ADC_D9, IO_IS = radio1_RSSI_ADC_D[9]
    PORT radio1_TX_DAC_PLL_LOCK = controller_DAC1_PLL_LOCK
    PORT radio1_TX_DAC_RESET = controller_DAC1_RESET
    PORT radio1_SHDN_external = controller_radio1_SHDN_external
    PORT radio1_TxEn_external = controller_radio1_TxEn_external
    PORT radio1_RxEn_external = controller_radio1_RxEn_external
    PORT radio1_RxHP_external = controller_radio1_RxHP_external
    PORT radio1_TxGain0 = controller_radio1_TxGain0, IO_IS = radio1_TxGain[0]
    PORT radio1_TxGain1 = controller_radio1_TxGain1, IO_IS = radio1_TxGain[1]
    PORT radio1_TxGain2 = controller_radio1_TxGain2, IO_IS = radio1_TxGain[2]
    PORT radio1_TxGain3 = controller_radio1_TxGain3, IO_IS = radio1_TxGain[3]
    PORT radio1_TxGain4 = controller_radio1_TxGain4, IO_IS = radio1_TxGain[4]
    PORT radio1_TxGain5 = controller_radio1_TxGain5, IO_IS = radio1_TxGain[5]
    PORT radio1_TxStart = controller_radio1_TxStart

    #######################
    # Slot #2 Radio Ports #
    #######################
    PORT radio2_SHDN = controller_radio2_SHDN
    PORT radio2_TxEn = controller_radio2_TxEn
    PORT radio2_RxEn = controller_radio2_RxEn
    PORT radio2_RxHP = controller_radio2_RxHP
    PORT radio2_LD = controller_radio2_LD
    PORT radio2_24PA = controller_radio2_24PA
    PORT radio2_5PA = controller_radio2_5PA
    PORT radio2_ANTSW0 = controller_radio2_ANTSW0, IO_IS = radio2_antsw[0]
    PORT radio2_ANTSW1 = controller_radio2_ANTSW1, IO_IS = radio2_antsw[1]
    PORT radio2_LED0 = controller_radio2_LED0, IO_IS = radio2_LED[0]
    PORT radio2_LED1 = controller_radio2_LED1, IO_IS = radio2_LED[1]
    PORT radio2_LED2 = controller_radio2_LED2, IO_IS = radio2_LED[2]
    PORT radio2_ADC_RX_DCS = controller_radio2_RX_ADC_DCS
    PORT radio2_ADC_RX_DFS = controller_radio2_RX_ADC_DFS
    PORT radio2_ADC_RX_OTRA = controller_radio2_RX_ADC_OTRA
    PORT radio2_ADC_RX_OTRB = controller_radio2_RX_ADC_OTRB
    PORT radio2_ADC_RX_PWDNA = controller_radio2_RX_ADC_PWDNA
    PORT radio2_ADC_RX_PWDNB = controller_radio2_RX_ADC_PWDNB
    PORT radio2_DIPSW0 = controller_radio2_DIPSW0, IO_IS = radio2_DIPSW[0]
    PORT radio2_DIPSW1 = controller_radio2_DIPSW1, IO_IS = radio2_DIPSW[1]
    PORT radio2_DIPSW2 = controller_radio2_DIPSW2, IO_IS = radio2_DIPSW[2]
    PORT radio2_DIPSW3 = controller_radio2_DIPSW3, IO_IS = radio2_DIPSW[3]
    PORT radio2_RSSI_ADC_CLAMP = controller_radio2_RSSI_ADC_CLAMP
    PORT radio2_RSSI_ADC_HIZ = controller_radio2_RSSI_ADC_HIZ
    PORT radio2_RSSI_ADC_OTR = controller_radio2_RSSI_ADC_OTR
    PORT radio2_RSSI_ADC_SLEEP = controller_radio2_RSSI_ADC_SLEEP
    PORT radio2_RSSI_ADC_D0 = controller_radio2_RSSI_ADC_D0, IO_IS = radio2_RSSI_ADC_D[0]
    PORT radio2_RSSI_ADC_D1 = controller_radio2_RSSI_ADC_D1, IO_IS = radio2_RSSI_ADC_D[1]
    PORT radio2_RSSI_ADC_D2 = controller_radio2_RSSI_ADC_D2, IO_IS = radio2_RSSI_ADC_D[2]
    PORT radio2_RSSI_ADC_D3 = controller_radio2_RSSI_ADC_D3, IO_IS = radio2_RSSI_ADC_D[3]
    PORT radio2_RSSI_ADC_D4 = controller_radio2_RSSI_ADC_D4, IO_IS = radio2_RSSI_ADC_D[4]
    PORT radio2_RSSI_ADC_D5 = controller_radio2_RSSI_ADC_D5, IO_IS = radio2_RSSI_ADC_D[5]
    PORT radio2_RSSI_ADC_D6 = controller_radio2_RSSI_ADC_D6, IO_IS = radio2_RSSI_ADC_D[6]
    PORT radio2_RSSI_ADC_D7 = controller_radio2_RSSI_ADC_D7, IO_IS = radio2_RSSI_ADC_D[7]
    PORT radio2_RSSI_ADC_D8 = controller_radio2_RSSI_ADC_D8, IO_IS = radio2_RSSI_ADC_D[8]
    PORT radio2_RSSI_ADC_D9 = controller_radio2_RSSI_ADC_D9, IO_IS = radio2_RSSI_ADC_D[9]
    PORT radio2_TX_DAC_PLL_LOCK = controller_DAC2_PLL_LOCK
    PORT radio2_TX_DAC_RESET = controller_DAC2_RESET
    PORT radio2_SHDN_external = controller_radio2_SHDN_external
    PORT radio2_TxEn_external = controller_radio2_TxEn_external
    PORT radio2_RxEn_external = controller_radio2_RxEn_external
    PORT radio2_RxHP_external = controller_radio2_RxHP_external
    PORT radio2_TxGain0 = controller_radio2_TxGain0, IO_IS = radio2_TxGain[0]
    PORT radio2_TxGain1 = controller_radio2_TxGain1, IO_IS = radio2_TxGain[1]
    PORT radio2_TxGain2 = controller_radio2_TxGain2, IO_IS = radio2_TxGain[2]
    PORT radio2_TxGain3 = controller_radio2_TxGain3, IO_IS = radio2_TxGain[3]
    PORT radio2_TxGain4 = controller_radio2_TxGain4, IO_IS = radio2_TxGain[4]
    PORT radio2_TxGain5 = controller_radio2_TxGain5, IO_IS = radio2_TxGain[5]
    PORT radio2_TxStart = controller_radio2_TxStart

    #######################
    # Slot #3 Radio Ports #
    #######################
    PORT radio3_SHDN = controller_radio3_SHDN
    PORT radio3_TxEn = controller_radio3_TxEn
    PORT radio3_RxEn = controller_radio3_RxEn
    PORT radio3_RxHP = controller_radio3_RxHP
    PORT radio3_LD = controller_radio3_LD
    PORT radio3_24PA = controller_radio3_24PA
    PORT radio3_5PA = controller_radio3_5PA
    PORT radio3_ANTSW0 = controller_radio3_ANTSW0, IO_IS = radio3_antsw[0]
    PORT radio3_ANTSW1 = controller_radio3_ANTSW1, IO_IS = radio3_antsw[1]
    PORT radio3_LED0 = controller_radio3_LED0, IO_IS = radio3_LED[0]
    PORT radio3_LED1 = controller_radio3_LED1, IO_IS = radio3_LED[1]
    PORT radio3_LED2 = controller_radio3_LED2, IO_IS = radio3_LED[2]
    PORT radio3_ADC_RX_DCS = controller_radio3_RX_ADC_DCS
    PORT radio3_ADC_RX_DFS = controller_radio3_RX_ADC_DFS
    PORT radio3_ADC_RX_OTRA = controller_radio3_RX_ADC_OTRA
    PORT radio3_ADC_RX_OTRB = controller_radio3_RX_ADC_OTRB
    PORT radio3_ADC_RX_PWDNA = controller_radio3_RX_ADC_PWDNA
    PORT radio3_ADC_RX_PWDNB = controller_radio3_RX_ADC_PWDNB
    PORT radio3_DIPSW0 = controller_radio3_DIPSW0, IO_IS = radio3_DIPSW[0]
    PORT radio3_DIPSW1 = controller_radio3_DIPSW1, IO_IS = radio3_DIPSW[1]
    PORT radio3_DIPSW2 = controller_radio3_DIPSW2, IO_IS = radio3_DIPSW[2]
    PORT radio3_DIPSW3 = controller_radio3_DIPSW3, IO_IS = radio3_DIPSW[3]
    PORT radio3_RSSI_ADC_CLAMP = controller_radio3_RSSI_ADC_CLAMP
    PORT radio3_RSSI_ADC_HIZ = controller_radio3_RSSI_ADC_HIZ
    PORT radio3_RSSI_ADC_OTR = controller_radio3_RSSI_ADC_OTR
    PORT radio3_RSSI_ADC_SLEEP = controller_radio3_RSSI_ADC_SLEEP
    PORT radio3_RSSI_ADC_D0 = controller_radio3_RSSI_ADC_D0, IO_IS = radio3_RSSI_ADC_D[0]
    PORT radio3_RSSI_ADC_D1 = controller_radio3_RSSI_ADC_D1, IO_IS = radio3_RSSI_ADC_D[1]
    PORT radio3_RSSI_ADC_D2 = controller_radio3_RSSI_ADC_D2, IO_IS = radio3_RSSI_ADC_D[2]
    PORT radio3_RSSI_ADC_D3 = controller_radio3_RSSI_ADC_D3, IO_IS = radio3_RSSI_ADC_D[3]
    PORT radio3_RSSI_ADC_D4 = controller_radio3_RSSI_ADC_D4, IO_IS = radio3_RSSI_ADC_D[4]
    PORT radio3_RSSI_ADC_D5 = controller_radio3_RSSI_ADC_D5, IO_IS = radio3_RSSI_ADC_D[5]
    PORT radio3_RSSI_ADC_D6 = controller_radio3_RSSI_ADC_D6, IO_IS = radio3_RSSI_ADC_D[6]
    PORT radio3_RSSI_ADC_D7 = controller_radio3_RSSI_ADC_D7, IO_IS = radio3_RSSI_ADC_D[7]
    PORT radio3_RSSI_ADC_D8 = controller_radio3_RSSI_ADC_D8, IO_IS = radio3_RSSI_ADC_D[8]
    PORT radio3_RSSI_ADC_D9 = controller_radio3_RSSI_ADC_D9, IO_IS = radio3_RSSI_ADC_D[9]
    PORT radio3_TX_DAC_PLL_LOCK = controller_DAC3_PLL_LOCK
    PORT radio3_TX_DAC_RESET = controller_DAC3_RESET
    PORT radio3_SHDN_external = controller_radio3_SHDN_external
    PORT radio3_TxEn_external = controller_radio3_TxEn_external
    PORT radio3_RxEn_external = controller_radio3_RxEn_external
    PORT radio3_RxHP_external = controller_radio3_RxHP_external
    PORT radio3_TxGain0 = controller_radio3_TxGain0, IO_IS = radio3_TxGain[0]
    PORT radio3_TxGain1 = controller_radio3_TxGain1, IO_IS = radio3_TxGain[1]
    PORT radio3_TxGain2 = controller_radio3_TxGain2, IO_IS = radio3_TxGain[2]
    PORT radio3_TxGain3 = controller_radio3_TxGain3, IO_IS = radio3_TxGain[3]
    PORT radio3_TxGain4 = controller_radio3_TxGain4, IO_IS = radio3_TxGain[4]
    PORT radio3_TxGain5 = controller_radio3_TxGain5, IO_IS = radio3_TxGain[5]
    PORT radio3_TxStart = controller_radio3_TxStart

    #######################
    # Slot #4 Radio Ports #
    #######################
    PORT radio4_SHDN = controller_radio4_SHDN
    PORT radio4_TxEn = controller_radio4_TxEn
    PORT radio4_RxEn = controller_radio4_RxEn
    PORT radio4_RxHP = controller_radio4_RxHP
    PORT radio4_LD = controller_radio4_LD
    PORT radio4_24PA = controller_radio4_24PA
    PORT radio4_5PA = controller_radio4_5PA
    PORT radio4_ANTSW0 = controller_radio4_ANTSW0, IO_IS = radio4_antsw[0]
    PORT radio4_ANTSW1 = controller_radio4_ANTSW1, IO_IS = radio4_antsw[1]
    PORT radio4_LED0 = controller_radio4_LED0, IO_IS = radio4_LED[0]
    PORT radio4_LED1 = controller_radio4_LED1, IO_IS = radio4_LED[1]
    PORT radio4_LED2 = controller_radio4_LED2, IO_IS = radio4_LED[2]
    PORT radio4_ADC_RX_DCS = controller_radio4_RX_ADC_DCS
    PORT radio4_ADC_RX_DFS = controller_radio4_RX_ADC_DFS
    PORT radio4_ADC_RX_OTRA = controller_radio4_RX_ADC_OTRA
    PORT radio4_ADC_RX_OTRB = controller_radio4_RX_ADC_OTRB
    PORT radio4_ADC_RX_PWDNA = controller_radio4_RX_ADC_PWDNA
    PORT radio4_ADC_RX_PWDNB = controller_radio4_RX_ADC_PWDNB
    PORT radio4_DIPSW0 = controller_radio4_DIPSW0, IO_IS = radio4_DIPSW[0]
    PORT radio4_DIPSW1 = controller_radio4_DIPSW1, IO_IS = radio4_DIPSW[1]
    PORT radio4_DIPSW2 = controller_radio4_DIPSW2, IO_IS = radio4_DIPSW[2]
    PORT radio4_DIPSW3 = controller_radio4_DIPSW3, IO_IS = radio4_DIPSW[3]
    PORT radio4_RSSI_ADC_CLAMP = controller_radio4_RSSI_ADC_CLAMP
    PORT radio4_RSSI_ADC_HIZ = controller_radio4_RSSI_ADC_HIZ
    PORT radio4_RSSI_ADC_OTR = controller_radio4_RSSI_ADC_OTR
    PORT radio4_RSSI_ADC_SLEEP = controller_radio4_RSSI_ADC_SLEEP
    PORT radio4_RSSI_ADC_D0 = controller_radio4_RSSI_ADC_D0, IO_IS = radio4_RSSI_ADC_D[0]
    PORT radio4_RSSI_ADC_D1 = controller_radio4_RSSI_ADC_D1, IO_IS = radio4_RSSI_ADC_D[1]
    PORT radio4_RSSI_ADC_D2 = controller_radio4_RSSI_ADC_D2, IO_IS = radio4_RSSI_ADC_D[2]
    PORT radio4_RSSI_ADC_D3 = controller_radio4_RSSI_ADC_D3, IO_IS = radio4_RSSI_ADC_D[3]
    PORT radio4_RSSI_ADC_D4 = controller_radio4_RSSI_ADC_D4, IO_IS = radio4_RSSI_ADC_D[4]
    PORT radio4_RSSI_ADC_D5 = controller_radio4_RSSI_ADC_D5, IO_IS = radio4_RSSI_ADC_D[5]
    PORT radio4_RSSI_ADC_D6 = controller_radio4_RSSI_ADC_D6, IO_IS = radio4_RSSI_ADC_D[6]
    PORT radio4_RSSI_ADC_D7 = controller_radio4_RSSI_ADC_D7, IO_IS = radio4_RSSI_ADC_D[7]
    PORT radio4_RSSI_ADC_D8 = controller_radio4_RSSI_ADC_D8, IO_IS = radio4_RSSI_ADC_D[8]
    PORT radio4_RSSI_ADC_D9 = controller_radio4_RSSI_ADC_D9, IO_IS = radio4_RSSI_ADC_D[9]
    PORT radio4_TX_DAC_PLL_LOCK = controller_DAC4_PLL_LOCK
    PORT radio4_TX_DAC_RESET = controller_DAC4_RESET
    PORT radio4_SHDN_external = controller_radio4_SHDN_external
    PORT radio4_TxEn_external = controller_radio4_TxEn_external
    PORT radio4_RxEn_external = controller_radio4_RxEn_external
    PORT radio4_RxHP_external = controller_radio4_RxHP_external
    PORT radio4_TxGain0 = controller_radio4_TxGain0, IO_IS = radio4_TxGain[0]
    PORT radio4_TxGain1 = controller_radio4_TxGain1, IO_IS = radio4_TxGain[1]
    PORT radio4_TxGain2 = controller_radio4_TxGain2, IO_IS = radio4_TxGain[2]
    PORT radio4_TxGain3 = controller_radio4_TxGain3, IO_IS = radio4_TxGain[3]
    PORT radio4_TxGain4 = controller_radio4_TxGain4, IO_IS = radio4_TxGain[4]
    PORT radio4_TxGain5 = controller_radio4_TxGain5, IO_IS = radio4_TxGain[5]
    PORT radio4_TxStart = controller_radio4_TxStart
END

#Radio Controller -> Radio Board Bridge for Slot #1
BEGIN IO_INTERFACE
    ATTRIBUTE IOTYPE = WARP_RADIOBRIDGE_V1
    ATTRIBUTE INSTANCE = radio_bridge_slot_1
    ATTRIBUTE EXCLUSIVE = slot1
    ATTRIBUTE ALERT = 'Enable this peripheral only if a radio board is mounted in daughtercard slot 1.'

    PORT    converter_clock_out = radio1_conv_clk_p

    PORT    radio_b0 = radio1_b0, IO_IS = radioGain[0]
    PORT    radio_b1 = radio1_b1, IO_IS = radioGain[1]
    PORT    radio_b2 = radio1_b2, IO_IS = radioGain[2]
    PORT    radio_b3 = radio1_b3, IO_IS = radioGain[3]
    PORT    radio_b4 = radio1_b4, IO_IS = radioGain[4]
    PORT    radio_b5 = radio1_b5, IO_IS = radioGain[5]
    PORT    radio_b6 = radio1_b6, IO_IS = radioGain[6]

    PORT    radio_ADC_I0 = radio1_ADC_I0, IO_IS = radioADCI[0]
    PORT    radio_ADC_I1 = radio1_ADC_I1, IO_IS = radioADCI[1]
    PORT    radio_ADC_I2 = radio1_ADC_I2, IO_IS = radioADCI[2]
    PORT    radio_ADC_I3 = radio1_ADC_I3, IO_IS = radioADCI[3]
    PORT    radio_ADC_I4 = radio1_ADC_I4, IO_IS = radioADCI[4]
    PORT    radio_ADC_I5 = radio1_ADC_I5, IO_IS = radioADCI[5]
    PORT    radio_ADC_I6 = radio1_ADC_I6, IO_IS = radioADCI[6]
    PORT    radio_ADC_I7 = radio1_ADC_I7, IO_IS = radioADCI[7]
    PORT    radio_ADC_I8 = radio1_ADC_I8, IO_IS = radioADCI[8]
    PORT    radio_ADC_I9 = radio1_ADC_I9, IO_IS = radioADCI[9]
    PORT    radio_ADC_I10 = radio1_ADC_I10, IO_IS = radioADCI[10]
    PORT    radio_ADC_I11 = radio1_ADC_I11, IO_IS = radioADCI[11]
    PORT    radio_ADC_I12 = radio1_ADC_I12, IO_IS = radioADCI[12]
    PORT    radio_ADC_I13 = radio1_ADC_I13, IO_IS = radioADCI[13]

    PORT    radio_ADC_Q0 = radio1_ADC_Q0, IO_IS = radioADCQ[0]
    PORT    radio_ADC_Q1 = radio1_ADC_Q1, IO_IS = radioADCQ[1]
    PORT    radio_ADC_Q2 = radio1_ADC_Q2, IO_IS = radioADCQ[2]
    PORT    radio_ADC_Q3 = radio1_ADC_Q3, IO_IS = radioADCQ[3]
    PORT    radio_ADC_Q4 = radio1_ADC_Q4, IO_IS = radioADCQ[4]
    PORT    radio_ADC_Q5 = radio1_ADC_Q5, IO_IS = radioADCQ[5]
    PORT    radio_ADC_Q6 = radio1_ADC_Q6, IO_IS = radioADCQ[6]
    PORT    radio_ADC_Q7 = radio1_ADC_Q7, IO_IS = radioADCQ[7]
    PORT    radio_ADC_Q8 = radio1_ADC_Q8, IO_IS = radioADCQ[8]
    PORT    radio_ADC_Q9 = radio1_ADC_Q9, IO_IS = radioADCQ[9]
    PORT    radio_ADC_Q10 = radio1_ADC_Q10, IO_IS = radioADCQ[10]
    PORT    radio_ADC_Q11 = radio1_ADC_Q11, IO_IS = radioADCQ[11]
    PORT    radio_ADC_Q12 = radio1_ADC_Q12, IO_IS = radioADCQ[12]
    PORT    radio_ADC_Q13 = radio1_ADC_Q13, IO_IS = radioADCQ[13]

    PORT    radio_DAC_I0 = radio1_DAC_I0, IO_IS = radioDACI[0]
    PORT    radio_DAC_I1 = radio1_DAC_I1, IO_IS = radioDACI[1]
    PORT    radio_DAC_I2 = radio1_DAC_I2, IO_IS = radioDACI[2]
    PORT    radio_DAC_I3 = radio1_DAC_I3, IO_IS = radioDACI[3]
    PORT    radio_DAC_I4 = radio1_DAC_I4, IO_IS = radioDACI[4]
    PORT    radio_DAC_I5 = radio1_DAC_I5, IO_IS = radioDACI[5]
    PORT    radio_DAC_I6 = radio1_DAC_I6, IO_IS = radioDACI[6]
    PORT    radio_DAC_I7 = radio1_DAC_I7, IO_IS = radioDACI[7]
    PORT    radio_DAC_I8 = radio1_DAC_I8, IO_IS = radioDACI[8]
    PORT    radio_DAC_I9 = radio1_DAC_I9, IO_IS = radioDACI[9]
    PORT    radio_DAC_I10 = radio1_DAC_I10, IO_IS = radioDACI[10]
    PORT    radio_DAC_I11 = radio1_DAC_I11, IO_IS = radioDACI[11]
    PORT    radio_DAC_I12 = radio1_DAC_I12, IO_IS = radioDACI[12]
    PORT    radio_DAC_I13 = radio1_DAC_I13, IO_IS = radioDACI[13]
    PORT    radio_DAC_I14 = radio1_DAC_I14, IO_IS = radioDACI[14]
    PORT    radio_DAC_I15 = radio1_DAC_I15, IO_IS = radioDACI[15]

    PORT    radio_DAC_Q0 = radio1_DAC_Q0, IO_IS = radioDACQ[0]
    PORT    radio_DAC_Q1 = radio1_DAC_Q1, IO_IS = radioDACQ[1]
    PORT    radio_DAC_Q2 = radio1_DAC_Q2, IO_IS = radioDACQ[2]
    PORT    radio_DAC_Q3 = radio1_DAC_Q3, IO_IS = radioDACQ[3]
    PORT    radio_DAC_Q4 = radio1_DAC_Q4, IO_IS = radioDACQ[4]
    PORT    radio_DAC_Q5 = radio1_DAC_Q5, IO_IS = radioDACQ[5]
    PORT    radio_DAC_Q6 = radio1_DAC_Q6, IO_IS = radioDACQ[6]
    PORT    radio_DAC_Q7 = radio1_DAC_Q7, IO_IS = radioDACQ[7]
    PORT    radio_DAC_Q8 = radio1_DAC_Q8, IO_IS = radioDACQ[8]
    PORT    radio_DAC_Q9 = radio1_DAC_Q9, IO_IS = radioDACQ[9]
    PORT    radio_DAC_Q10 = radio1_DAC_Q10, IO_IS = radioDACQ[10]
    PORT    radio_DAC_Q11 = radio1_DAC_Q11, IO_IS = radioDACQ[11]
    PORT    radio_DAC_Q12 = radio1_DAC_Q12, IO_IS = radioDACQ[12]
    PORT    radio_DAC_Q13 = radio1_DAC_Q13, IO_IS = radioDACQ[13]
    PORT    radio_DAC_Q14 = radio1_DAC_Q14, IO_IS = radioDACQ[14]
    PORT    radio_DAC_Q15 = radio1_DAC_Q15, IO_IS = radioDACQ[15]

    ##########################################
    #Radio Controller <-> Radio Bridge Ports #
    ##########################################
    PORT    controller_logic_clk = controller_logic_clk
    PORT    controller_spi_clk = controller_spi_clk 
    PORT    controller_spi_data = controller_spi_data 
    PORT    controller_radio_cs = controller_radio1_cs 
    PORT    controller_dac_cs = controller_dac1_cs 
    PORT    controller_SHDN = controller_radio1_SHDN 
    PORT    controller_TxEn = controller_radio1_TxEn 
    PORT    controller_RxEn = controller_radio1_RxEn 
    PORT    controller_RxHP = controller_radio1_RxHP 
    PORT    controller_24PA = controller_radio1_24PA 
    PORT    controller_5PA = controller_radio1_5PA 
    PORT    controller_ANTSW0 = controller_radio1_ANTSW0, IO_IS = c2b_ANTSW[0]
    PORT    controller_ANTSW1 = controller_radio1_ANTSW1, IO_IS = c2b_ANTSW[1] 
    PORT    controller_LED0 = controller_radio1_LED0, IO_IS = c2b_LED[0]
    PORT    controller_LED1 = controller_radio1_LED1, IO_IS = c2b_LED[1]
    PORT    controller_LED2 = controller_radio1_LED2, IO_IS = c2b_LED[2]
    PORT    controller_RX_ADC_DCS = controller_radio1_RX_ADC_DCS
    PORT    controller_RX_ADC_DFS = controller_radio1_RX_ADC_DFS
    PORT    controller_RX_ADC_PWDNA = controller_radio1_RX_ADC_PWDNA
    PORT    controller_RX_ADC_PWDNB = controller_radio1_RX_ADC_PWDNB
    PORT    controller_DIPSW0 = controller_radio1_DIPSW0, IO_IS = c2b_DIPSW[0]
    PORT    controller_DIPSW1 = controller_radio1_DIPSW1, IO_IS = c2b_DIPSW[1]
    PORT    controller_DIPSW2 = controller_radio1_DIPSW2, IO_IS = c2b_DIPSW[2]
    PORT    controller_DIPSW3 = controller_radio1_DIPSW3, IO_IS = c2b_DIPSW[3]
    PORT    controller_RSSI_ADC_CLAMP = controller_radio1_RSSI_ADC_CLAMP
    PORT    controller_RSSI_ADC_HIZ = controller_radio1_RSSI_ADC_HIZ
    PORT    controller_RSSI_ADC_SLEEP = controller_radio1_RSSI_ADC_SLEEP
    PORT    controller_RSSI_ADC_D0 = controller_radio1_RSSI_ADC_D0, IO_IS = c2b_RSSI_ADC_D[0]
    PORT    controller_RSSI_ADC_D1 = controller_radio1_RSSI_ADC_D1, IO_IS = c2b_RSSI_ADC_D[1]
    PORT    controller_RSSI_ADC_D2 = controller_radio1_RSSI_ADC_D2, IO_IS = c2b_RSSI_ADC_D[2]
    PORT    controller_RSSI_ADC_D3 = controller_radio1_RSSI_ADC_D3, IO_IS = c2b_RSSI_ADC_D[3]
    PORT    controller_RSSI_ADC_D4 = controller_radio1_RSSI_ADC_D4, IO_IS = c2b_RSSI_ADC_D[4]
    PORT    controller_RSSI_ADC_D5 = controller_radio1_RSSI_ADC_D5, IO_IS = c2b_RSSI_ADC_D[5]
    PORT    controller_RSSI_ADC_D6 = controller_radio1_RSSI_ADC_D6, IO_IS = c2b_RSSI_ADC_D[6]
    PORT    controller_RSSI_ADC_D7 = controller_radio1_RSSI_ADC_D7, IO_IS = c2b_RSSI_ADC_D[7]
    PORT    controller_RSSI_ADC_D8 = controller_radio1_RSSI_ADC_D8, IO_IS = c2b_RSSI_ADC_D[8]
    PORT    controller_RSSI_ADC_D9 = controller_radio1_RSSI_ADC_D9, IO_IS = c2b_RSSI_ADC_D[9]
    PORT    controller_LD = controller_radio1_LD
    PORT    controller_RX_ADC_OTRA = controller_radio1_RX_ADC_OTRA
    PORT    controller_RX_ADC_OTRB = controller_radio1_RX_ADC_OTRB
    PORT    controller_RSSI_ADC_OTR = controller_radio1_RSSI_ADC_OTR
    PORT    controller_dac_PLL_LOCK = controller_dac1_PLL_LOCK
    PORT    controller_dac_RESET = controller_dac1_RESET
    PORT    user_Tx_gain0 = controller_radio1_TxGain0, IO_IS = userTxG[0]
    PORT    user_Tx_gain1 = controller_radio1_TxGain1, IO_IS = userTxG[1]
    PORT    user_Tx_gain2 = controller_radio1_TxGain2, IO_IS = userTxG[2]
    PORT    user_Tx_gain3 = controller_radio1_TxGain3, IO_IS = userTxG[3]
    PORT    user_Tx_gain4 = controller_radio1_TxGain4, IO_IS = userTxG[4]
    PORT    user_Tx_gain5 = controller_radio1_TxGain5, IO_IS = userTxG[5]
    PORT    controller_TxStart = controller_radio1_TxStart
    PORT    controller_SHDN_external = controller_radio1_SHDN_external
    PORT    controller_RxEn_external = controller_radio1_RxEn_external
    PORT    controller_TxEn_external = controller_radio1_TxEn_external
    PORT    controller_RxHP_external = controller_radio1_RxHP_external


    #####################################
    #Radio Bridge <-> Radio Board Ports #
    #####################################
    PORT    dac_spi_data = dac1_spi_data
    PORT    dac_spi_cs = dac1_spi_cs
    PORT    dac_spi_clk = dac1_spi_clk
    PORT    radio_spi_clk = radio1_spi_clk
    PORT    radio_spi_data = radio1_spi_data
    PORT    radio_spi_cs = radio1_spi_cs
    PORT    radio_SHDN = radio1_SHDN
    PORT    radio_TxEn = radio1_TxEn
    PORT    radio_RxEn = radio1_RxEn
    PORT    radio_RxHP = radio1_RxHP
    PORT    radio_24PA = radio1_24PA
    PORT    radio_5PA = radio1_5PA
    PORT    radio_ANTSW0 = radio1_ANTSW0, IO_IS = b2r_ANTSW[0]
    PORT    radio_ANTSW1 = radio1_ANTSW1, IO_IS = b2r_ANTSW[1]
    PORT    radio_LED0 = radio1_LED0, IO_IS = b2r_LED[0]
    PORT    radio_LED1 = radio1_LED1, IO_IS = b2r_LED[1]
    PORT    radio_LED2 = radio1_LED2, IO_IS = b2r_LED[2]
    PORT    radio_RX_ADC_DCS = radio1_RX_ADC_DCS
    PORT    radio_RX_ADC_DFS = radio1_RX_ADC_DFS
    PORT    radio_RX_ADC_PWDNA = radio1_RX_ADC_PWDNA
    PORT    radio_RX_ADC_PWDNB = radio1_RX_ADC_PWDNB
    PORT    radio_DIPSW0 = radio1_DIPSW0, IO_IS = b2r_DIPSW[0]
    PORT    radio_DIPSW1 = radio1_DIPSW1, IO_IS = b2r_DIPSW[1]
    PORT    radio_DIPSW2 = radio1_DIPSW2, IO_IS = b2r_DIPSW[2]
    PORT    radio_DIPSW3 = radio1_DIPSW3, IO_IS = b2r_DIPSW[3]
    PORT    radio_RSSI_ADC_clk = radio1_RSSI_ADC_clk
    PORT    radio_RSSI_ADC_CLAMP = radio1_RSSI_ADC_CLAMP
    PORT    radio_RSSI_ADC_HIZ = radio1_RSSI_ADC_HIZ
    PORT    radio_RSSI_ADC_SLEEP = radio1_RSSI_ADC_SLEEP
    PORT    radio_RSSI_ADC_D0 = radio1_RSSI_ADC_D0, IO_IS = b2r_RSSI_ADC_D[0]
    PORT    radio_RSSI_ADC_D1 = radio1_RSSI_ADC_D1, IO_IS = b2r_RSSI_ADC_D[1]
    PORT    radio_RSSI_ADC_D2 = radio1_RSSI_ADC_D2, IO_IS = b2r_RSSI_ADC_D[2]
    PORT    radio_RSSI_ADC_D3 = radio1_RSSI_ADC_D3, IO_IS = b2r_RSSI_ADC_D[3]
    PORT    radio_RSSI_ADC_D4 = radio1_RSSI_ADC_D4, IO_IS = b2r_RSSI_ADC_D[4]
    PORT    radio_RSSI_ADC_D5 = radio1_RSSI_ADC_D5, IO_IS = b2r_RSSI_ADC_D[5]
    PORT    radio_RSSI_ADC_D6 = radio1_RSSI_ADC_D6, IO_IS = b2r_RSSI_ADC_D[6]
    PORT    radio_RSSI_ADC_D7 = radio1_RSSI_ADC_D7, IO_IS = b2r_RSSI_ADC_D[7]
    PORT    radio_RSSI_ADC_D8 = radio1_RSSI_ADC_D8, IO_IS = b2r_RSSI_ADC_D[8]
    PORT    radio_RSSI_ADC_D9 = radio1_RSSI_ADC_D9, IO_IS = b2r_RSSI_ADC_D[9]
    PORT    radio_LD = radio1_LD
    PORT    radio_RX_ADC_OTRA = radio1_RX_ADC_OTRA
    PORT    radio_RX_ADC_OTRB = radio1_RX_ADC_OTRB
    PORT    radio_RSSI_ADC_OTR = radio1_RSSI_ADC_OTR
    PORT    radio_dac_PLL_LOCK = radio1_dac1_PLL_LOCK
    PORT    radio_dac_RESET = radio1_dac1_RESET

    PORT    user_EEPROM_IO_T = DQ1_T_user_EEPROM_IO_T
    PORT    user_EEPROM_IO_O = DQ1_O_user_EEPROM_IO_O
    PORT    user_EEPROM_IO_I = DQ1_I_user_EEPROM_IO_I
    PORT    radio_EEPROM_IO = radio1_EEPROM_IO
END

#Radio Controller -> Radio Board Bridge for Slot #2
BEGIN IO_INTERFACE
    ATTRIBUTE IOTYPE = WARP_RADIOBRIDGE_V1
    ATTRIBUTE INSTANCE = radio_bridge_slot_2
    ATTRIBUTE EXCLUSIVE = slot2
    ATTRIBUTE ALERT = 'Enable this peripheral only if a radio board is mounted in daughtercard slot 2.'

    PORT    converter_clock_out = radio2_conv_clk_p

    PORT    radio_b0 = radio2_b0, IO_IS = radioGain[0]
    PORT    radio_b1 = radio2_b1, IO_IS = radioGain[1]
    PORT    radio_b2 = radio2_b2, IO_IS = radioGain[2]
    PORT    radio_b3 = radio2_b3, IO_IS = radioGain[3]
    PORT    radio_b4 = radio2_b4, IO_IS = radioGain[4]
    PORT    radio_b5 = radio2_b5, IO_IS = radioGain[5]
    PORT    radio_b6 = radio2_b6, IO_IS = radioGain[6]

    PORT    radio_ADC_I0 = radio2_ADC_I0, IO_IS = radioADCI[0]
    PORT    radio_ADC_I1 = radio2_ADC_I1, IO_IS = radioADCI[1]
    PORT    radio_ADC_I2 = radio2_ADC_I2, IO_IS = radioADCI[2]
    PORT    radio_ADC_I3 = radio2_ADC_I3, IO_IS = radioADCI[3]
    PORT    radio_ADC_I4 = radio2_ADC_I4, IO_IS = radioADCI[4]
    PORT    radio_ADC_I5 = radio2_ADC_I5, IO_IS = radioADCI[5]
    PORT    radio_ADC_I6 = radio2_ADC_I6, IO_IS = radioADCI[6]
    PORT    radio_ADC_I7 = radio2_ADC_I7, IO_IS = radioADCI[7]
    PORT    radio_ADC_I8 = radio2_ADC_I8, IO_IS = radioADCI[8]
    PORT    radio_ADC_I9 = radio2_ADC_I9, IO_IS = radioADCI[9]
    PORT    radio_ADC_I10 = radio2_ADC_I10, IO_IS = radioADCI[10]
    PORT    radio_ADC_I11 = radio2_ADC_I11, IO_IS = radioADCI[11]
    PORT    radio_ADC_I12 = radio2_ADC_I12, IO_IS = radioADCI[12]
    PORT    radio_ADC_I13 = radio2_ADC_I13, IO_IS = radioADCI[13]

    PORT    radio_ADC_Q0 = radio2_ADC_Q0, IO_IS = radioADCQ[0]
    PORT    radio_ADC_Q1 = radio2_ADC_Q1, IO_IS = radioADCQ[1]
    PORT    radio_ADC_Q2 = radio2_ADC_Q2, IO_IS = radioADCQ[2]
    PORT    radio_ADC_Q3 = radio2_ADC_Q3, IO_IS = radioADCQ[3]
    PORT    radio_ADC_Q4 = radio2_ADC_Q4, IO_IS = radioADCQ[4]
    PORT    radio_ADC_Q5 = radio2_ADC_Q5, IO_IS = radioADCQ[5]
    PORT    radio_ADC_Q6 = radio2_ADC_Q6, IO_IS = radioADCQ[6]
    PORT    radio_ADC_Q7 = radio2_ADC_Q7, IO_IS = radioADCQ[7]
    PORT    radio_ADC_Q8 = radio2_ADC_Q8, IO_IS = radioADCQ[8]
    PORT    radio_ADC_Q9 = radio2_ADC_Q9, IO_IS = radioADCQ[9]
    PORT    radio_ADC_Q10 = radio2_ADC_Q10, IO_IS = radioADCQ[10]
    PORT    radio_ADC_Q11 = radio2_ADC_Q11, IO_IS = radioADCQ[11]
    PORT    radio_ADC_Q12 = radio2_ADC_Q12, IO_IS = radioADCQ[12]
    PORT    radio_ADC_Q13 = radio2_ADC_Q13, IO_IS = radioADCQ[13]

    PORT    radio_DAC_I0 = radio2_DAC_I0, IO_IS = radioDACI[0]
    PORT    radio_DAC_I1 = radio2_DAC_I1, IO_IS = radioDACI[1]
    PORT    radio_DAC_I2 = radio2_DAC_I2, IO_IS = radioDACI[2]
    PORT    radio_DAC_I3 = radio2_DAC_I3, IO_IS = radioDACI[3]
    PORT    radio_DAC_I4 = radio2_DAC_I4, IO_IS = radioDACI[4]
    PORT    radio_DAC_I5 = radio2_DAC_I5, IO_IS = radioDACI[5]
    PORT    radio_DAC_I6 = radio2_DAC_I6, IO_IS = radioDACI[6]
    PORT    radio_DAC_I7 = radio2_DAC_I7, IO_IS = radioDACI[7]
    PORT    radio_DAC_I8 = radio2_DAC_I8, IO_IS = radioDACI[8]
    PORT    radio_DAC_I9 = radio2_DAC_I9, IO_IS = radioDACI[9]
    PORT    radio_DAC_I10 = radio2_DAC_I10, IO_IS = radioDACI[10]
    PORT    radio_DAC_I11 = radio2_DAC_I11, IO_IS = radioDACI[11]
    PORT    radio_DAC_I12 = radio2_DAC_I12, IO_IS = radioDACI[12]
    PORT    radio_DAC_I13 = radio2_DAC_I13, IO_IS = radioDACI[13]
    PORT    radio_DAC_I14 = radio2_DAC_I14, IO_IS = radioDACI[14]
    PORT    radio_DAC_I15 = radio2_DAC_I15, IO_IS = radioDACI[15]

    PORT    radio_DAC_Q0 = radio2_DAC_Q0, IO_IS = radioDACQ[0]
    PORT    radio_DAC_Q1 = radio2_DAC_Q1, IO_IS = radioDACQ[1]
    PORT    radio_DAC_Q2 = radio2_DAC_Q2, IO_IS = radioDACQ[2]
    PORT    radio_DAC_Q3 = radio2_DAC_Q3, IO_IS = radioDACQ[3]
    PORT    radio_DAC_Q4 = radio2_DAC_Q4, IO_IS = radioDACQ[4]
    PORT    radio_DAC_Q5 = radio2_DAC_Q5, IO_IS = radioDACQ[5]
    PORT    radio_DAC_Q6 = radio2_DAC_Q6, IO_IS = radioDACQ[6]
    PORT    radio_DAC_Q7 = radio2_DAC_Q7, IO_IS = radioDACQ[7]
    PORT    radio_DAC_Q8 = radio2_DAC_Q8, IO_IS = radioDACQ[8]
    PORT    radio_DAC_Q9 = radio2_DAC_Q9, IO_IS = radioDACQ[9]
    PORT    radio_DAC_Q10 = radio2_DAC_Q10, IO_IS = radioDACQ[10]
    PORT    radio_DAC_Q11 = radio2_DAC_Q11, IO_IS = radioDACQ[11]
    PORT    radio_DAC_Q12 = radio2_DAC_Q12, IO_IS = radioDACQ[12]
    PORT    radio_DAC_Q13 = radio2_DAC_Q13, IO_IS = radioDACQ[13]
    PORT    radio_DAC_Q14 = radio2_DAC_Q14, IO_IS = radioDACQ[14]
    PORT    radio_DAC_Q15 = radio2_DAC_Q15, IO_IS = radioDACQ[15]

    ##########################################
    #Radio Controller <-> Radio Bridge Ports #
    ##########################################
    PORT    controller_logic_clk = controller_logic_clk
    PORT    controller_spi_clk = controller_spi_clk 
    PORT    controller_spi_data = controller_spi_data 
    PORT    controller_radio_cs = controller_radio2_cs 
    PORT    controller_dac_cs = controller_dac2_cs 
    PORT    controller_SHDN = controller_radio2_SHDN 
    PORT    controller_TxEn = controller_radio2_TxEn 
    PORT    controller_RxEn = controller_radio2_RxEn 
    PORT    controller_RxHP = controller_radio2_RxHP 
    PORT    controller_24PA = controller_radio2_24PA 
    PORT    controller_5PA = controller_radio2_5PA 
    PORT    controller_ANTSW0 = controller_radio2_ANTSW0, IO_IS = c2b_ANTSW[0]
    PORT    controller_ANTSW1 = controller_radio2_ANTSW1, IO_IS = c2b_ANTSW[1] 
    PORT    controller_LED0 = controller_radio2_LED0, IO_IS = c2b_LED[0]
    PORT    controller_LED1 = controller_radio2_LED1, IO_IS = c2b_LED[1]
    PORT    controller_LED2 = controller_radio2_LED2, IO_IS = c2b_LED[2]
    PORT    controller_RX_ADC_DCS = controller_radio2_RX_ADC_DCS
    PORT    controller_RX_ADC_DFS = controller_radio2_RX_ADC_DFS
    PORT    controller_RX_ADC_PWDNA = controller_radio2_RX_ADC_PWDNA
    PORT    controller_RX_ADC_PWDNB = controller_radio2_RX_ADC_PWDNB
    PORT    controller_DIPSW0 = controller_radio2_DIPSW0, IO_IS = c2b_DIPSW[0]
    PORT    controller_DIPSW1 = controller_radio2_DIPSW1, IO_IS = c2b_DIPSW[1]
    PORT    controller_DIPSW2 = controller_radio2_DIPSW2, IO_IS = c2b_DIPSW[2]
    PORT    controller_DIPSW3 = controller_radio2_DIPSW3, IO_IS = c2b_DIPSW[3]
    PORT    controller_RSSI_ADC_CLAMP = controller_radio2_RSSI_ADC_CLAMP
    PORT    controller_RSSI_ADC_HIZ = controller_radio2_RSSI_ADC_HIZ
    PORT    controller_RSSI_ADC_SLEEP = controller_radio2_RSSI_ADC_SLEEP
    PORT    controller_RSSI_ADC_D0 = controller_radio2_RSSI_ADC_D0, IO_IS = c2b_RSSI_ADC_D[0]
    PORT    controller_RSSI_ADC_D1 = controller_radio2_RSSI_ADC_D1, IO_IS = c2b_RSSI_ADC_D[1]
    PORT    controller_RSSI_ADC_D2 = controller_radio2_RSSI_ADC_D2, IO_IS = c2b_RSSI_ADC_D[2]
    PORT    controller_RSSI_ADC_D3 = controller_radio2_RSSI_ADC_D3, IO_IS = c2b_RSSI_ADC_D[3]
    PORT    controller_RSSI_ADC_D4 = controller_radio2_RSSI_ADC_D4, IO_IS = c2b_RSSI_ADC_D[4]
    PORT    controller_RSSI_ADC_D5 = controller_radio2_RSSI_ADC_D5, IO_IS = c2b_RSSI_ADC_D[5]
    PORT    controller_RSSI_ADC_D6 = controller_radio2_RSSI_ADC_D6, IO_IS = c2b_RSSI_ADC_D[6]
    PORT    controller_RSSI_ADC_D7 = controller_radio2_RSSI_ADC_D7, IO_IS = c2b_RSSI_ADC_D[7]
    PORT    controller_RSSI_ADC_D8 = controller_radio2_RSSI_ADC_D8, IO_IS = c2b_RSSI_ADC_D[8]
    PORT    controller_RSSI_ADC_D9 = controller_radio2_RSSI_ADC_D9, IO_IS = c2b_RSSI_ADC_D[9]
    PORT    controller_LD = controller_radio2_LD
    PORT    controller_RX_ADC_OTRA = controller_radio2_RX_ADC_OTRA
    PORT    controller_RX_ADC_OTRB = controller_radio2_RX_ADC_OTRB
    PORT    controller_RSSI_ADC_OTR = controller_radio2_RSSI_ADC_OTR
    PORT    controller_dac_PLL_LOCK = controller_dac2_PLL_LOCK
    PORT    controller_dac_RESET = controller_dac2_RESET
    PORT    user_Tx_gain0 = controller_radio2_TxGain0, IO_IS = userTxG[0]
    PORT    user_Tx_gain1 = controller_radio2_TxGain1, IO_IS = userTxG[1]
    PORT    user_Tx_gain2 = controller_radio2_TxGain2, IO_IS = userTxG[2]
    PORT    user_Tx_gain3 = controller_radio2_TxGain3, IO_IS = userTxG[3]
    PORT    user_Tx_gain4 = controller_radio2_TxGain4, IO_IS = userTxG[4]
    PORT    user_Tx_gain5 = controller_radio2_TxGain5, IO_IS = userTxG[5]
    PORT    controller_TxStart = controller_radio2_TxStart
    PORT    controller_SHDN_external = controller_radio2_SHDN_external
    PORT    controller_RxEn_external = controller_radio2_RxEn_external
    PORT    controller_TxEn_external = controller_radio2_TxEn_external
    PORT    controller_RxHP_external = controller_radio2_RxHP_external

    #####################################
    #Radio Bridge <-> Radio Board Ports #
    #####################################
    PORT    dac_spi_data = dac2_spi_data
    PORT    dac_spi_cs = dac2_spi_cs
    PORT    dac_spi_clk = dac2_spi_clk
    PORT    radio_spi_clk = radio2_spi_clk
    PORT    radio_spi_data = radio2_spi_data
    PORT    radio_spi_cs = radio2_spi_cs
    PORT    radio_SHDN = radio2_SHDN
    PORT    radio_TxEn = radio2_TxEn
    PORT    radio_RxEn = radio2_RxEn
    PORT    radio_RxHP = radio2_RxHP
    PORT    radio_24PA = radio2_24PA
    PORT    radio_5PA = radio2_5PA
    PORT    radio_ANTSW0 = radio2_ANTSW0, IO_IS = b2r_ANTSW[0]
    PORT    radio_ANTSW1 = radio2_ANTSW1, IO_IS = b2r_ANTSW[1]
    PORT    radio_LED0 = radio2_LED0, IO_IS = b2r_LED[0]
    PORT    radio_LED1 = radio2_LED1, IO_IS = b2r_LED[1]
    PORT    radio_LED2 = radio2_LED2, IO_IS = b2r_LED[2]
    PORT    radio_RX_ADC_DCS = radio2_RX_ADC_DCS
    PORT    radio_RX_ADC_DFS = radio2_RX_ADC_DFS
    PORT    radio_RX_ADC_PWDNA = radio2_RX_ADC_PWDNA
    PORT    radio_RX_ADC_PWDNB = radio2_RX_ADC_PWDNB
    PORT    radio_DIPSW0 = radio2_DIPSW0, IO_IS = b2r_DIPSW[0]
    PORT    radio_DIPSW1 = radio2_DIPSW1, IO_IS = b2r_DIPSW[1]
    PORT    radio_DIPSW2 = radio2_DIPSW2, IO_IS = b2r_DIPSW[2]
    PORT    radio_DIPSW3 = radio2_DIPSW3, IO_IS = b2r_DIPSW[3]
    PORT    radio_RSSI_ADC_clk = radio2_RSSI_ADC_clk
    PORT    radio_RSSI_ADC_CLAMP = radio2_RSSI_ADC_CLAMP
    PORT    radio_RSSI_ADC_HIZ = radio2_RSSI_ADC_HIZ
    PORT    radio_RSSI_ADC_SLEEP = radio2_RSSI_ADC_SLEEP
    PORT    radio_RSSI_ADC_D0 = radio2_RSSI_ADC_D0, IO_IS = b2r_RSSI_ADC_D[0]
    PORT    radio_RSSI_ADC_D1 = radio2_RSSI_ADC_D1, IO_IS = b2r_RSSI_ADC_D[1]
    PORT    radio_RSSI_ADC_D2 = radio2_RSSI_ADC_D2, IO_IS = b2r_RSSI_ADC_D[2]
    PORT    radio_RSSI_ADC_D3 = radio2_RSSI_ADC_D3, IO_IS = b2r_RSSI_ADC_D[3]
    PORT    radio_RSSI_ADC_D4 = radio2_RSSI_ADC_D4, IO_IS = b2r_RSSI_ADC_D[4]
    PORT    radio_RSSI_ADC_D5 = radio2_RSSI_ADC_D5, IO_IS = b2r_RSSI_ADC_D[5]
    PORT    radio_RSSI_ADC_D6 = radio2_RSSI_ADC_D6, IO_IS = b2r_RSSI_ADC_D[6]
    PORT    radio_RSSI_ADC_D7 = radio2_RSSI_ADC_D7, IO_IS = b2r_RSSI_ADC_D[7]
    PORT    radio_RSSI_ADC_D8 = radio2_RSSI_ADC_D8, IO_IS = b2r_RSSI_ADC_D[8]
    PORT    radio_RSSI_ADC_D9 = radio2_RSSI_ADC_D9, IO_IS = b2r_RSSI_ADC_D[9]
    PORT    radio_LD = radio2_LD
    PORT    radio_RX_ADC_OTRA = radio2_RX_ADC_OTRA
    PORT    radio_RX_ADC_OTRB = radio2_RX_ADC_OTRB
    PORT    radio_RSSI_ADC_OTR = radio2_RSSI_ADC_OTR
    PORT    radio_dac_PLL_LOCK = radio2_dac2_PLL_LOCK
    PORT    radio_dac_RESET = radio2_dac2_RESET

    PORT    user_EEPROM_IO_T = DQ2_T_user_EEPROM_IO_T
    PORT    user_EEPROM_IO_O = DQ2_O_user_EEPROM_IO_O
    PORT    user_EEPROM_IO_I = DQ2_I_user_EEPROM_IO_I
    PORT    radio_EEPROM_IO = radio2_EEPROM_IO
END

#Radio Controller -> Radio Board Bridge for Slot #3
BEGIN IO_INTERFACE
    ATTRIBUTE IOTYPE = WARP_RADIOBRIDGE_V1
    ATTRIBUTE INSTANCE = radio_bridge_slot_3
    ATTRIBUTE EXCLUSIVE = slot3
    ATTRIBUTE ALERT = 'Enable this peripheral only if a radio board is mounted in daughtercard slot 3.'

    PORT    converter_clock_out = radio3_conv_clk_p

    PORT    radio_b0 = radio3_b0, IO_IS = radioGain[0]
    PORT    radio_b1 = radio3_b1, IO_IS = radioGain[1]
    PORT    radio_b2 = radio3_b2, IO_IS = radioGain[2]
    PORT    radio_b3 = radio3_b3, IO_IS = radioGain[3]
    PORT    radio_b4 = radio3_b4, IO_IS = radioGain[4]
    PORT    radio_b5 = radio3_b5, IO_IS = radioGain[5]
    PORT    radio_b6 = radio3_b6, IO_IS = radioGain[6]

    PORT    radio_ADC_I0 = radio3_ADC_I0, IO_IS = radioADCI[0]
    PORT    radio_ADC_I1 = radio3_ADC_I1, IO_IS = radioADCI[1]
    PORT    radio_ADC_I2 = radio3_ADC_I2, IO_IS = radioADCI[2]
    PORT    radio_ADC_I3 = radio3_ADC_I3, IO_IS = radioADCI[3]
    PORT    radio_ADC_I4 = radio3_ADC_I4, IO_IS = radioADCI[4]
    PORT    radio_ADC_I5 = radio3_ADC_I5, IO_IS = radioADCI[5]
    PORT    radio_ADC_I6 = radio3_ADC_I6, IO_IS = radioADCI[6]
    PORT    radio_ADC_I7 = radio3_ADC_I7, IO_IS = radioADCI[7]
    PORT    radio_ADC_I8 = radio3_ADC_I8, IO_IS = radioADCI[8]
    PORT    radio_ADC_I9 = radio3_ADC_I9, IO_IS = radioADCI[9]
    PORT    radio_ADC_I10 = radio3_ADC_I10, IO_IS = radioADCI[10]
    PORT    radio_ADC_I11 = radio3_ADC_I11, IO_IS = radioADCI[11]
    PORT    radio_ADC_I12 = radio3_ADC_I12, IO_IS = radioADCI[12]
    PORT    radio_ADC_I13 = radio3_ADC_I13, IO_IS = radioADCI[13]

    PORT    radio_ADC_Q0 = radio3_ADC_Q0, IO_IS = radioADCQ[0]
    PORT    radio_ADC_Q1 = radio3_ADC_Q1, IO_IS = radioADCQ[1]
    PORT    radio_ADC_Q2 = radio3_ADC_Q2, IO_IS = radioADCQ[2]
    PORT    radio_ADC_Q3 = radio3_ADC_Q3, IO_IS = radioADCQ[3]
    PORT    radio_ADC_Q4 = radio3_ADC_Q4, IO_IS = radioADCQ[4]
    PORT    radio_ADC_Q5 = radio3_ADC_Q5, IO_IS = radioADCQ[5]
    PORT    radio_ADC_Q6 = radio3_ADC_Q6, IO_IS = radioADCQ[6]
    PORT    radio_ADC_Q7 = radio3_ADC_Q7, IO_IS = radioADCQ[7]
    PORT    radio_ADC_Q8 = radio3_ADC_Q8, IO_IS = radioADCQ[8]
    PORT    radio_ADC_Q9 = radio3_ADC_Q9, IO_IS = radioADCQ[9]
    PORT    radio_ADC_Q10 = radio3_ADC_Q10, IO_IS = radioADCQ[10]
    PORT    radio_ADC_Q11 = radio3_ADC_Q11, IO_IS = radioADCQ[11]
    PORT    radio_ADC_Q12 = radio3_ADC_Q12, IO_IS = radioADCQ[12]
    PORT    radio_ADC_Q13 = radio3_ADC_Q13, IO_IS = radioADCQ[13]

    PORT    radio_DAC_I0 = radio3_DAC_I0, IO_IS = radioDACI[0]
    PORT    radio_DAC_I1 = radio3_DAC_I1, IO_IS = radioDACI[1]
    PORT    radio_DAC_I2 = radio3_DAC_I2, IO_IS = radioDACI[2]
    PORT    radio_DAC_I3 = radio3_DAC_I3, IO_IS = radioDACI[3]
    PORT    radio_DAC_I4 = radio3_DAC_I4, IO_IS = radioDACI[4]
    PORT    radio_DAC_I5 = radio3_DAC_I5, IO_IS = radioDACI[5]
    PORT    radio_DAC_I6 = radio3_DAC_I6, IO_IS = radioDACI[6]
    PORT    radio_DAC_I7 = radio3_DAC_I7, IO_IS = radioDACI[7]
    PORT    radio_DAC_I8 = radio3_DAC_I8, IO_IS = radioDACI[8]
    PORT    radio_DAC_I9 = radio3_DAC_I9, IO_IS = radioDACI[9]
    PORT    radio_DAC_I10 = radio3_DAC_I10, IO_IS = radioDACI[10]
    PORT    radio_DAC_I11 = radio3_DAC_I11, IO_IS = radioDACI[11]
    PORT    radio_DAC_I12 = radio3_DAC_I12, IO_IS = radioDACI[12]
    PORT    radio_DAC_I13 = radio3_DAC_I13, IO_IS = radioDACI[13]
    PORT    radio_DAC_I14 = radio3_DAC_I14, IO_IS = radioDACI[14]
    PORT    radio_DAC_I15 = radio3_DAC_I15, IO_IS = radioDACI[15]

    PORT    radio_DAC_Q0 = radio3_DAC_Q0, IO_IS = radioDACQ[0]
    PORT    radio_DAC_Q1 = radio3_DAC_Q1, IO_IS = radioDACQ[1]
    PORT    radio_DAC_Q2 = radio3_DAC_Q2, IO_IS = radioDACQ[2]
    PORT    radio_DAC_Q3 = radio3_DAC_Q3, IO_IS = radioDACQ[3]
    PORT    radio_DAC_Q4 = radio3_DAC_Q4, IO_IS = radioDACQ[4]
    PORT    radio_DAC_Q5 = radio3_DAC_Q5, IO_IS = radioDACQ[5]
    PORT    radio_DAC_Q6 = radio3_DAC_Q6, IO_IS = radioDACQ[6]
    PORT    radio_DAC_Q7 = radio3_DAC_Q7, IO_IS = radioDACQ[7]
    PORT    radio_DAC_Q8 = radio3_DAC_Q8, IO_IS = radioDACQ[8]
    PORT    radio_DAC_Q9 = radio3_DAC_Q9, IO_IS = radioDACQ[9]
    PORT    radio_DAC_Q10 = radio3_DAC_Q10, IO_IS = radioDACQ[10]
    PORT    radio_DAC_Q11 = radio3_DAC_Q11, IO_IS = radioDACQ[11]
    PORT    radio_DAC_Q12 = radio3_DAC_Q12, IO_IS = radioDACQ[12]
    PORT    radio_DAC_Q13 = radio3_DAC_Q13, IO_IS = radioDACQ[13]
    PORT    radio_DAC_Q14 = radio3_DAC_Q14, IO_IS = radioDACQ[14]
    PORT    radio_DAC_Q15 = radio3_DAC_Q15, IO_IS = radioDACQ[15]

    ##########################################
    #Radio Controller <-> Radio Bridge Ports #
    ##########################################
    PORT    controller_logic_clk = controller_logic_clk
    PORT    controller_spi_clk = controller_spi_clk 
    PORT    controller_spi_data = controller_spi_data 
    PORT    controller_radio_cs = controller_radio3_cs 
    PORT    controller_dac_cs = controller_dac3_cs 
    PORT    controller_SHDN = controller_radio3_SHDN 
    PORT    controller_TxEn = controller_radio3_TxEn 
    PORT    controller_RxEn = controller_radio3_RxEn 
    PORT    controller_RxHP = controller_radio3_RxHP 
    PORT    controller_24PA = controller_radio3_24PA 
    PORT    controller_5PA = controller_radio3_5PA 
    PORT    controller_ANTSW0 = controller_radio3_ANTSW0, IO_IS = c2b_ANTSW[0]
    PORT    controller_ANTSW1 = controller_radio3_ANTSW1, IO_IS = c2b_ANTSW[1] 
    PORT    controller_LED0 = controller_radio3_LED0, IO_IS = c2b_LED[0]
    PORT    controller_LED1 = controller_radio3_LED1, IO_IS = c2b_LED[1]
    PORT    controller_LED2 = controller_radio3_LED2, IO_IS = c2b_LED[2]
    PORT    controller_RX_ADC_DCS = controller_radio3_RX_ADC_DCS
    PORT    controller_RX_ADC_DFS = controller_radio3_RX_ADC_DFS
    PORT    controller_RX_ADC_PWDNA = controller_radio3_RX_ADC_PWDNA
    PORT    controller_RX_ADC_PWDNB = controller_radio3_RX_ADC_PWDNB
    PORT    controller_DIPSW0 = controller_radio3_DIPSW0, IO_IS = c2b_DIPSW[0]
    PORT    controller_DIPSW1 = controller_radio3_DIPSW1, IO_IS = c2b_DIPSW[1]
    PORT    controller_DIPSW2 = controller_radio3_DIPSW2, IO_IS = c2b_DIPSW[2]
    PORT    controller_DIPSW3 = controller_radio3_DIPSW3, IO_IS = c2b_DIPSW[3]
    PORT    controller_RSSI_ADC_CLAMP = controller_radio3_RSSI_ADC_CLAMP
    PORT    controller_RSSI_ADC_HIZ = controller_radio3_RSSI_ADC_HIZ
    PORT    controller_RSSI_ADC_SLEEP = controller_radio3_RSSI_ADC_SLEEP
    PORT    controller_RSSI_ADC_D0 = controller_radio3_RSSI_ADC_D0, IO_IS = c2b_RSSI_ADC_D[0]
    PORT    controller_RSSI_ADC_D1 = controller_radio3_RSSI_ADC_D1, IO_IS = c2b_RSSI_ADC_D[1]
    PORT    controller_RSSI_ADC_D2 = controller_radio3_RSSI_ADC_D2, IO_IS = c2b_RSSI_ADC_D[2]
    PORT    controller_RSSI_ADC_D3 = controller_radio3_RSSI_ADC_D3, IO_IS = c2b_RSSI_ADC_D[3]
    PORT    controller_RSSI_ADC_D4 = controller_radio3_RSSI_ADC_D4, IO_IS = c2b_RSSI_ADC_D[4]
    PORT    controller_RSSI_ADC_D5 = controller_radio3_RSSI_ADC_D5, IO_IS = c2b_RSSI_ADC_D[5]
    PORT    controller_RSSI_ADC_D6 = controller_radio3_RSSI_ADC_D6, IO_IS = c2b_RSSI_ADC_D[6]
    PORT    controller_RSSI_ADC_D7 = controller_radio3_RSSI_ADC_D7, IO_IS = c2b_RSSI_ADC_D[7]
    PORT    controller_RSSI_ADC_D8 = controller_radio3_RSSI_ADC_D8, IO_IS = c2b_RSSI_ADC_D[8]
    PORT    controller_RSSI_ADC_D9 = controller_radio3_RSSI_ADC_D9, IO_IS = c2b_RSSI_ADC_D[9]
    PORT    controller_LD = controller_radio3_LD
    PORT    controller_RX_ADC_OTRA = controller_radio3_RX_ADC_OTRA
    PORT    controller_RX_ADC_OTRB = controller_radio3_RX_ADC_OTRB
    PORT    controller_RSSI_ADC_OTR = controller_radio3_RSSI_ADC_OTR
    PORT    controller_dac_PLL_LOCK = controller_dac3_PLL_LOCK
    PORT    controller_dac_RESET = controller_dac3_RESET
    PORT    user_Tx_gain0 = controller_radio3_TxGain0, IO_IS = userTxG[0]
    PORT    user_Tx_gain1 = controller_radio3_TxGain1, IO_IS = userTxG[1]
    PORT    user_Tx_gain2 = controller_radio3_TxGain2, IO_IS = userTxG[2]
    PORT    user_Tx_gain3 = controller_radio3_TxGain3, IO_IS = userTxG[3]
    PORT    user_Tx_gain4 = controller_radio3_TxGain4, IO_IS = userTxG[4]
    PORT    user_Tx_gain5 = controller_radio3_TxGain5, IO_IS = userTxG[5]
    PORT    controller_TxStart = controller_radio3_TxStart
    PORT    controller_SHDN_external = controller_radio3_SHDN_external
    PORT    controller_RxEn_external = controller_radio3_RxEn_external
    PORT    controller_TxEn_external = controller_radio3_TxEn_external
    PORT    controller_RxHP_external = controller_radio3_RxHP_external

    #####################################
    #Radio Bridge <-> Radio Board Ports #
    #####################################
    PORT    dac_spi_data = dac3_spi_data
    PORT    dac_spi_cs = dac3_spi_cs
    PORT    dac_spi_clk = dac3_spi_clk
    PORT    radio_spi_clk = radio3_spi_clk
    PORT    radio_spi_data = radio3_spi_data
    PORT    radio_spi_cs = radio3_spi_cs
    PORT    radio_SHDN = radio3_SHDN
    PORT    radio_TxEn = radio3_TxEn
    PORT    radio_RxEn = radio3_RxEn
    PORT    radio_RxHP = radio3_RxHP
    PORT    radio_24PA = radio3_24PA
    PORT    radio_5PA = radio3_5PA
    PORT    radio_ANTSW0 = radio3_ANTSW0, IO_IS = b2r_ANTSW[0]
    PORT    radio_ANTSW1 = radio3_ANTSW1, IO_IS = b2r_ANTSW[1]
    PORT    radio_LED0 = radio3_LED0, IO_IS = b2r_LED[0]
    PORT    radio_LED1 = radio3_LED1, IO_IS = b2r_LED[1]
    PORT    radio_LED2 = radio3_LED2, IO_IS = b2r_LED[2]
    PORT    radio_RX_ADC_DCS = radio3_RX_ADC_DCS
    PORT    radio_RX_ADC_DFS = radio3_RX_ADC_DFS
    PORT    radio_RX_ADC_PWDNA = radio3_RX_ADC_PWDNA
    PORT    radio_RX_ADC_PWDNB = radio3_RX_ADC_PWDNB
    PORT    radio_DIPSW0 = radio3_DIPSW0, IO_IS = b2r_DIPSW[0]
    PORT    radio_DIPSW1 = radio3_DIPSW1, IO_IS = b2r_DIPSW[1]
    PORT    radio_DIPSW2 = radio3_DIPSW2, IO_IS = b2r_DIPSW[2]
    PORT    radio_DIPSW3 = radio3_DIPSW3, IO_IS = b2r_DIPSW[3]
    PORT    radio_RSSI_ADC_clk = radio3_RSSI_ADC_clk
    PORT    radio_RSSI_ADC_CLAMP = radio3_RSSI_ADC_CLAMP
    PORT    radio_RSSI_ADC_HIZ = radio3_RSSI_ADC_HIZ
    PORT    radio_RSSI_ADC_SLEEP = radio3_RSSI_ADC_SLEEP
    PORT    radio_RSSI_ADC_D0 = radio3_RSSI_ADC_D0, IO_IS = b2r_RSSI_ADC_D[0]
    PORT    radio_RSSI_ADC_D1 = radio3_RSSI_ADC_D1, IO_IS = b2r_RSSI_ADC_D[1]
    PORT    radio_RSSI_ADC_D2 = radio3_RSSI_ADC_D2, IO_IS = b2r_RSSI_ADC_D[2]
    PORT    radio_RSSI_ADC_D3 = radio3_RSSI_ADC_D3, IO_IS = b2r_RSSI_ADC_D[3]
    PORT    radio_RSSI_ADC_D4 = radio3_RSSI_ADC_D4, IO_IS = b2r_RSSI_ADC_D[4]
    PORT    radio_RSSI_ADC_D5 = radio3_RSSI_ADC_D5, IO_IS = b2r_RSSI_ADC_D[5]
    PORT    radio_RSSI_ADC_D6 = radio3_RSSI_ADC_D6, IO_IS = b2r_RSSI_ADC_D[6]
    PORT    radio_RSSI_ADC_D7 = radio3_RSSI_ADC_D7, IO_IS = b2r_RSSI_ADC_D[7]
    PORT    radio_RSSI_ADC_D8 = radio3_RSSI_ADC_D8, IO_IS = b2r_RSSI_ADC_D[8]
    PORT    radio_RSSI_ADC_D9 = radio3_RSSI_ADC_D9, IO_IS = b2r_RSSI_ADC_D[9]
    PORT    radio_LD = radio3_LD
    PORT    radio_RX_ADC_OTRA = radio3_RX_ADC_OTRA
    PORT    radio_RX_ADC_OTRB = radio3_RX_ADC_OTRB
    PORT    radio_RSSI_ADC_OTR = radio3_RSSI_ADC_OTR
    PORT    radio_dac_PLL_LOCK = radio3_dac3_PLL_LOCK
    PORT    radio_dac_RESET = radio3_dac3_RESET

    PORT    user_EEPROM_IO_T = DQ3_T_user_EEPROM_IO_T
    PORT    user_EEPROM_IO_O = DQ3_O_user_EEPROM_IO_O
    PORT    user_EEPROM_IO_I = DQ3_I_user_EEPROM_IO_I
    PORT    radio_EEPROM_IO = radio3_EEPROM_IO
END

#Radio Controller -> Radio Board Bridge for Slot #4
BEGIN IO_INTERFACE
    ATTRIBUTE IOTYPE = WARP_RADIOBRIDGE_V1
    ATTRIBUTE INSTANCE = radio_bridge_slot_4
    ATTRIBUTE EXCLUSIVE = slot4
    ATTRIBUTE ALERT = 'Enable this peripheral only if a radio board is mounted in daughtercard slot 4.'

    PORT    converter_clock_out = radio4_conv_clk_p

    PORT    radio_b0 = radio4_b0, IO_IS = radioGain[0]
    PORT    radio_b1 = radio4_b1, IO_IS = radioGain[1]
    PORT    radio_b2 = radio4_b2, IO_IS = radioGain[2]
    PORT    radio_b3 = radio4_b3, IO_IS = radioGain[3]
    PORT    radio_b4 = radio4_b4, IO_IS = radioGain[4]
    PORT    radio_b5 = radio4_b5, IO_IS = radioGain[5]
    PORT    radio_b6 = radio4_b6, IO_IS = radioGain[6]

    PORT    radio_ADC_I0 = radio4_ADC_I0, IO_IS = radioADCI[0]
    PORT    radio_ADC_I1 = radio4_ADC_I1, IO_IS = radioADCI[1]
    PORT    radio_ADC_I2 = radio4_ADC_I2, IO_IS = radioADCI[2]
    PORT    radio_ADC_I3 = radio4_ADC_I3, IO_IS = radioADCI[3]
    PORT    radio_ADC_I4 = radio4_ADC_I4, IO_IS = radioADCI[4]
    PORT    radio_ADC_I5 = radio4_ADC_I5, IO_IS = radioADCI[5]
    PORT    radio_ADC_I6 = radio4_ADC_I6, IO_IS = radioADCI[6]
    PORT    radio_ADC_I7 = radio4_ADC_I7, IO_IS = radioADCI[7]
    PORT    radio_ADC_I8 = radio4_ADC_I8, IO_IS = radioADCI[8]
    PORT    radio_ADC_I9 = radio4_ADC_I9, IO_IS = radioADCI[9]
    PORT    radio_ADC_I10 = radio4_ADC_I10, IO_IS = radioADCI[10]
    PORT    radio_ADC_I11 = radio4_ADC_I11, IO_IS = radioADCI[11]
    PORT    radio_ADC_I12 = radio4_ADC_I12, IO_IS = radioADCI[12]
    PORT    radio_ADC_I13 = radio4_ADC_I13, IO_IS = radioADCI[13]

    PORT    radio_ADC_Q0 = radio4_ADC_Q0, IO_IS = radioADCQ[0]
    PORT    radio_ADC_Q1 = radio4_ADC_Q1, IO_IS = radioADCQ[1]
    PORT    radio_ADC_Q2 = radio4_ADC_Q2, IO_IS = radioADCQ[2]
    PORT    radio_ADC_Q3 = radio4_ADC_Q3, IO_IS = radioADCQ[3]
    PORT    radio_ADC_Q4 = radio4_ADC_Q4, IO_IS = radioADCQ[4]
    PORT    radio_ADC_Q5 = radio4_ADC_Q5, IO_IS = radioADCQ[5]
    PORT    radio_ADC_Q6 = radio4_ADC_Q6, IO_IS = radioADCQ[6]
    PORT    radio_ADC_Q7 = radio4_ADC_Q7, IO_IS = radioADCQ[7]
    PORT    radio_ADC_Q8 = radio4_ADC_Q8, IO_IS = radioADCQ[8]
    PORT    radio_ADC_Q9 = radio4_ADC_Q9, IO_IS = radioADCQ[9]
    PORT    radio_ADC_Q10 = radio4_ADC_Q10, IO_IS = radioADCQ[10]
    PORT    radio_ADC_Q11 = radio4_ADC_Q11, IO_IS = radioADCQ[11]
    PORT    radio_ADC_Q12 = radio4_ADC_Q12, IO_IS = radioADCQ[12]
    PORT    radio_ADC_Q13 = radio4_ADC_Q13, IO_IS = radioADCQ[13]

    PORT    radio_DAC_I0 = radio4_DAC_I0, IO_IS = radioDACI[0]
    PORT    radio_DAC_I1 = radio4_DAC_I1, IO_IS = radioDACI[1]
    PORT    radio_DAC_I2 = radio4_DAC_I2, IO_IS = radioDACI[2]
    PORT    radio_DAC_I3 = radio4_DAC_I3, IO_IS = radioDACI[3]
    PORT    radio_DAC_I4 = radio4_DAC_I4, IO_IS = radioDACI[4]
    PORT    radio_DAC_I5 = radio4_DAC_I5, IO_IS = radioDACI[5]
    PORT    radio_DAC_I6 = radio4_DAC_I6, IO_IS = radioDACI[6]
    PORT    radio_DAC_I7 = radio4_DAC_I7, IO_IS = radioDACI[7]
    PORT    radio_DAC_I8 = radio4_DAC_I8, IO_IS = radioDACI[8]
    PORT    radio_DAC_I9 = radio4_DAC_I9, IO_IS = radioDACI[9]
    PORT    radio_DAC_I10 = radio4_DAC_I10, IO_IS = radioDACI[10]
    PORT    radio_DAC_I11 = radio4_DAC_I11, IO_IS = radioDACI[11]
    PORT    radio_DAC_I12 = radio4_DAC_I12, IO_IS = radioDACI[12]
    PORT    radio_DAC_I13 = radio4_DAC_I13, IO_IS = radioDACI[13]
    PORT    radio_DAC_I14 = radio4_DAC_I14, IO_IS = radioDACI[14]
    PORT    radio_DAC_I15 = radio4_DAC_I15, IO_IS = radioDACI[15]

    PORT    radio_DAC_Q0 = radio4_DAC_Q0, IO_IS = radioDACQ[0]
    PORT    radio_DAC_Q1 = radio4_DAC_Q1, IO_IS = radioDACQ[1]
    PORT    radio_DAC_Q2 = radio4_DAC_Q2, IO_IS = radioDACQ[2]
    PORT    radio_DAC_Q3 = radio4_DAC_Q3, IO_IS = radioDACQ[3]
    PORT    radio_DAC_Q4 = radio4_DAC_Q4, IO_IS = radioDACQ[4]
    PORT    radio_DAC_Q5 = radio4_DAC_Q5, IO_IS = radioDACQ[5]
    PORT    radio_DAC_Q6 = radio4_DAC_Q6, IO_IS = radioDACQ[6]
    PORT    radio_DAC_Q7 = radio4_DAC_Q7, IO_IS = radioDACQ[7]
    PORT    radio_DAC_Q8 = radio4_DAC_Q8, IO_IS = radioDACQ[8]
    PORT    radio_DAC_Q9 = radio4_DAC_Q9, IO_IS = radioDACQ[9]
    PORT    radio_DAC_Q10 = radio4_DAC_Q10, IO_IS = radioDACQ[10]
    PORT    radio_DAC_Q11 = radio4_DAC_Q11, IO_IS = radioDACQ[11]
    PORT    radio_DAC_Q12 = radio4_DAC_Q12, IO_IS = radioDACQ[12]
    PORT    radio_DAC_Q13 = radio4_DAC_Q13, IO_IS = radioDACQ[13]
    PORT    radio_DAC_Q14 = radio4_DAC_Q14, IO_IS = radioDACQ[14]
    PORT    radio_DAC_Q15 = radio4_DAC_Q15, IO_IS = radioDACQ[15]

    ##########################################
    #Radio Controller <-> Radio Bridge Ports #
    ##########################################
    PORT    controller_logic_clk = controller_logic_clk
    PORT    controller_spi_clk = controller_spi_clk 
    PORT    controller_spi_data = controller_spi_data 
    PORT    controller_radio_cs = controller_radio4_cs 
    PORT    controller_dac_cs = controller_dac4_cs 
    PORT    controller_SHDN = controller_radio4_SHDN 
    PORT    controller_TxEn = controller_radio4_TxEn 
    PORT    controller_RxEn = controller_radio4_RxEn 
    PORT    controller_RxHP = controller_radio4_RxHP 
    PORT    controller_24PA = controller_radio4_24PA 
    PORT    controller_5PA = controller_radio4_5PA 
    PORT    controller_ANTSW0 = controller_radio4_ANTSW0, IO_IS = c2b_ANTSW[0]
    PORT    controller_ANTSW1 = controller_radio4_ANTSW1, IO_IS = c2b_ANTSW[1] 
    PORT    controller_LED0 = controller_radio4_LED0, IO_IS = c2b_LED[0]
    PORT    controller_LED1 = controller_radio4_LED1, IO_IS = c2b_LED[1]
    PORT    controller_LED2 = controller_radio4_LED2, IO_IS = c2b_LED[2]
    PORT    controller_RX_ADC_DCS = controller_radio4_RX_ADC_DCS
    PORT    controller_RX_ADC_DFS = controller_radio4_RX_ADC_DFS
    PORT    controller_RX_ADC_PWDNA = controller_radio4_RX_ADC_PWDNA
    PORT    controller_RX_ADC_PWDNB = controller_radio4_RX_ADC_PWDNB
    PORT    controller_DIPSW0 = controller_radio4_DIPSW0, IO_IS = c2b_DIPSW[0]
    PORT    controller_DIPSW1 = controller_radio4_DIPSW1, IO_IS = c2b_DIPSW[1]
    PORT    controller_DIPSW2 = controller_radio4_DIPSW2, IO_IS = c2b_DIPSW[2]
    PORT    controller_DIPSW3 = controller_radio4_DIPSW3, IO_IS = c2b_DIPSW[3]
    PORT    controller_RSSI_ADC_CLAMP = controller_radio4_RSSI_ADC_CLAMP
    PORT    controller_RSSI_ADC_HIZ = controller_radio4_RSSI_ADC_HIZ
    PORT    controller_RSSI_ADC_SLEEP = controller_radio4_RSSI_ADC_SLEEP
    PORT    controller_RSSI_ADC_D0 = controller_radio4_RSSI_ADC_D0, IO_IS = c2b_RSSI_ADC_D[0]
    PORT    controller_RSSI_ADC_D1 = controller_radio4_RSSI_ADC_D1, IO_IS = c2b_RSSI_ADC_D[1]
    PORT    controller_RSSI_ADC_D2 = controller_radio4_RSSI_ADC_D2, IO_IS = c2b_RSSI_ADC_D[2]
    PORT    controller_RSSI_ADC_D3 = controller_radio4_RSSI_ADC_D3, IO_IS = c2b_RSSI_ADC_D[3]
    PORT    controller_RSSI_ADC_D4 = controller_radio4_RSSI_ADC_D4, IO_IS = c2b_RSSI_ADC_D[4]
    PORT    controller_RSSI_ADC_D5 = controller_radio4_RSSI_ADC_D5, IO_IS = c2b_RSSI_ADC_D[5]
    PORT    controller_RSSI_ADC_D6 = controller_radio4_RSSI_ADC_D6, IO_IS = c2b_RSSI_ADC_D[6]
    PORT    controller_RSSI_ADC_D7 = controller_radio4_RSSI_ADC_D7, IO_IS = c2b_RSSI_ADC_D[7]
    PORT    controller_RSSI_ADC_D8 = controller_radio4_RSSI_ADC_D8, IO_IS = c2b_RSSI_ADC_D[8]
    PORT    controller_RSSI_ADC_D9 = controller_radio4_RSSI_ADC_D9, IO_IS = c2b_RSSI_ADC_D[9]
    PORT    controller_LD = controller_radio4_LD
    PORT    controller_RX_ADC_OTRA = controller_radio4_RX_ADC_OTRA
    PORT    controller_RX_ADC_OTRB = controller_radio4_RX_ADC_OTRB
    PORT    controller_RSSI_ADC_OTR = controller_radio4_RSSI_ADC_OTR
    PORT    controller_dac_PLL_LOCK = controller_dac4_PLL_LOCK
    PORT    controller_dac_RESET = controller_dac4_RESET
    PORT    user_Tx_gain0 = controller_radio4_TxGain0, IO_IS = userTxG[0]
    PORT    user_Tx_gain1 = controller_radio4_TxGain1, IO_IS = userTxG[1]
    PORT    user_Tx_gain2 = controller_radio4_TxGain2, IO_IS = userTxG[2]
    PORT    user_Tx_gain3 = controller_radio4_TxGain3, IO_IS = userTxG[3]
    PORT    user_Tx_gain4 = controller_radio4_TxGain4, IO_IS = userTxG[4]
    PORT    user_Tx_gain5 = controller_radio4_TxGain5, IO_IS = userTxG[5]
    PORT    controller_TxStart = controller_radio4_TxStart
    PORT    controller_SHDN_external = controller_radio4_SHDN_external
    PORT    controller_RxEn_external = controller_radio4_RxEn_external
    PORT    controller_TxEn_external = controller_radio4_TxEn_external
    PORT    controller_RxHP_external = controller_radio4_RxHP_external

    #####################################
    #Radio Bridge <-> Radio Board Ports #
    #####################################
    PORT    dac_spi_data = dac4_spi_data
    PORT    dac_spi_cs = dac4_spi_cs
    PORT    dac_spi_clk = dac4_spi_clk
    PORT    radio_spi_clk = radio4_spi_clk
    PORT    radio_spi_data = radio4_spi_data
    PORT    radio_spi_cs = radio4_spi_cs
    PORT    radio_SHDN = radio4_SHDN
    PORT    radio_TxEn = radio4_TxEn
    PORT    radio_RxEn = radio4_RxEn
    PORT    radio_RxHP = radio4_RxHP
    PORT    radio_24PA = radio4_24PA
    PORT    radio_5PA = radio4_5PA
    PORT    radio_ANTSW0 = radio4_ANTSW0, IO_IS = b2r_ANTSW[0]
    PORT    radio_ANTSW1 = radio4_ANTSW1, IO_IS = b2r_ANTSW[1]
    PORT    radio_LED0 = radio4_LED0, IO_IS = b2r_LED[0]
    PORT    radio_LED1 = radio4_LED1, IO_IS = b2r_LED[1]
    PORT    radio_LED2 = radio4_LED2, IO_IS = b2r_LED[2]
    PORT    radio_RX_ADC_DCS = radio4_RX_ADC_DCS
    PORT    radio_RX_ADC_DFS = radio4_RX_ADC_DFS
    PORT    radio_RX_ADC_PWDNA = radio4_RX_ADC_PWDNA
    PORT    radio_RX_ADC_PWDNB = radio4_RX_ADC_PWDNB
    PORT    radio_DIPSW0 = radio4_DIPSW0, IO_IS = b2r_DIPSW[0]
    PORT    radio_DIPSW1 = radio4_DIPSW1, IO_IS = b2r_DIPSW[1]
    PORT    radio_DIPSW2 = radio4_DIPSW2, IO_IS = b2r_DIPSW[2]
    PORT    radio_DIPSW3 = radio4_DIPSW3, IO_IS = b2r_DIPSW[3]
    PORT    radio_RSSI_ADC_clk = radio4_RSSI_ADC_clk
    PORT    radio_RSSI_ADC_CLAMP = radio4_RSSI_ADC_CLAMP
    PORT    radio_RSSI_ADC_HIZ = radio4_RSSI_ADC_HIZ
    PORT    radio_RSSI_ADC_SLEEP = radio4_RSSI_ADC_SLEEP
    PORT    radio_RSSI_ADC_D0 = radio4_RSSI_ADC_D0, IO_IS = b2r_RSSI_ADC_D[0]
    PORT    radio_RSSI_ADC_D1 = radio4_RSSI_ADC_D1, IO_IS = b2r_RSSI_ADC_D[1]
    PORT    radio_RSSI_ADC_D2 = radio4_RSSI_ADC_D2, IO_IS = b2r_RSSI_ADC_D[2]
    PORT    radio_RSSI_ADC_D3 = radio4_RSSI_ADC_D3, IO_IS = b2r_RSSI_ADC_D[3]
    PORT    radio_RSSI_ADC_D4 = radio4_RSSI_ADC_D4, IO_IS = b2r_RSSI_ADC_D[4]
    PORT    radio_RSSI_ADC_D5 = radio4_RSSI_ADC_D5, IO_IS = b2r_RSSI_ADC_D[5]
    PORT    radio_RSSI_ADC_D6 = radio4_RSSI_ADC_D6, IO_IS = b2r_RSSI_ADC_D[6]
    PORT    radio_RSSI_ADC_D7 = radio4_RSSI_ADC_D7, IO_IS = b2r_RSSI_ADC_D[7]
    PORT    radio_RSSI_ADC_D8 = radio4_RSSI_ADC_D8, IO_IS = b2r_RSSI_ADC_D[8]
    PORT    radio_RSSI_ADC_D9 = radio4_RSSI_ADC_D9, IO_IS = b2r_RSSI_ADC_D[9]
    PORT    radio_LD = radio4_LD
    PORT    radio_RX_ADC_OTRA = radio4_RX_ADC_OTRA
    PORT    radio_RX_ADC_OTRB = radio4_RX_ADC_OTRB
    PORT    radio_RSSI_ADC_OTR = radio4_RSSI_ADC_OTR
    PORT    radio_dac_PLL_LOCK = radio4_dac4_PLL_LOCK
    PORT    radio_dac_RESET = radio4_dac4_RESET

    PORT    user_EEPROM_IO_T = DQ4_T_user_EEPROM_IO_T
    PORT    user_EEPROM_IO_O = DQ4_O_user_EEPROM_IO_O
    PORT    user_EEPROM_IO_I = DQ4_I_user_EEPROM_IO_I
    PORT    radio_EEPROM_IO = radio4_EEPROM_IO
END

BEGIN IO_INTERFACE
    ATTRIBUTE IOTYPE = WARP_ANALOGBRIDGE_V1
    ATTRIBUTE INSTANCE = analog_bridge_slot_4
    ATTRIBUTE EXCLUSIVE = slot4
    ATTRIBUTE ALERT = 'Enable this peripheral only if a analog board is mounted in daughtercard slot 4.'
    
    PORT    clock_out = analog4_clock_out

    PORT    analog_DAC1_A0 = analog4_DAC1_A0, IO_IS = analogDAC1A[0]
    PORT    analog_DAC1_A1 = analog4_DAC1_A1, IO_IS = analogDAC1A[1]
    PORT    analog_DAC1_A2 = analog4_DAC1_A2, IO_IS = analogDAC1A[2]
    PORT    analog_DAC1_A3 = analog4_DAC1_A3, IO_IS = analogDAC1A[3]
    PORT    analog_DAC1_A4 = analog4_DAC1_A4, IO_IS = analogDAC1A[4]
    PORT    analog_DAC1_A5 = analog4_DAC1_A5, IO_IS = analogDAC1A[5]
    PORT    analog_DAC1_A6 = analog4_DAC1_A6, IO_IS = analogDAC1A[6]
    PORT    analog_DAC1_A7 = analog4_DAC1_A7, IO_IS = analogDAC1A[7]
    PORT    analog_DAC1_A8 = analog4_DAC1_A8, IO_IS = analogDAC1A[8]
    PORT    analog_DAC1_A9 = analog4_DAC1_A9, IO_IS = analogDAC1A[9]
    PORT    analog_DAC1_A10 = analog4_DAC1_A10, IO_IS = analogDAC1A[10]
    PORT    analog_DAC1_A11 = analog4_DAC1_A11, IO_IS = analogDAC1A[11]
    PORT    analog_DAC1_A12 = analog4_DAC1_A12, IO_IS = analogDAC1A[12]
    PORT    analog_DAC1_A13 = analog4_DAC1_A13, IO_IS = analogDAC1A[13]

    PORT    analog_DAC1_B0 = analog4_DAC1_B0, IO_IS = analogDAC1B[0]
    PORT    analog_DAC1_B1 = analog4_DAC1_B1, IO_IS = analogDAC1B[1]
    PORT    analog_DAC1_B2 = analog4_DAC1_B2, IO_IS = analogDAC1B[2]
    PORT    analog_DAC1_B3 = analog4_DAC1_B3, IO_IS = analogDAC1B[3]
    PORT    analog_DAC1_B4 = analog4_DAC1_B4, IO_IS = analogDAC1B[4]
    PORT    analog_DAC1_B5 = analog4_DAC1_B5, IO_IS = analogDAC1B[5]
    PORT    analog_DAC1_B6 = analog4_DAC1_B6, IO_IS = analogDAC1B[6]
    PORT    analog_DAC1_B7 = analog4_DAC1_B7, IO_IS = analogDAC1B[7]
    PORT    analog_DAC1_B8 = analog4_DAC1_B8, IO_IS = analogDAC1B[8]
    PORT    analog_DAC1_B9 = analog4_DAC1_B9, IO_IS = analogDAC1B[9]
    PORT    analog_DAC1_B10 = analog4_DAC1_B10, IO_IS = analogDAC1B[10]
    PORT    analog_DAC1_B11 = analog4_DAC1_B11, IO_IS = analogDAC1B[11]
    PORT    analog_DAC1_B12 = analog4_DAC1_B12, IO_IS = analogDAC1B[12]
    PORT    analog_DAC1_B13 = analog4_DAC1_B13, IO_IS = analogDAC1B[13]

    PORT    analog_DAC2_A0 = analog4_DAC2_A0, IO_IS = analogDAC2A[0]
    PORT    analog_DAC2_A1 = analog4_DAC2_A1, IO_IS = analogDAC2A[1]
    PORT    analog_DAC2_A2 = analog4_DAC2_A2, IO_IS = analogDAC2A[2]
    PORT    analog_DAC2_A3 = analog4_DAC2_A3, IO_IS = analogDAC2A[3]
    PORT    analog_DAC2_A4 = analog4_DAC2_A4, IO_IS = analogDAC2A[4]
    PORT    analog_DAC2_A5 = analog4_DAC2_A5, IO_IS = analogDAC2A[5]
    PORT    analog_DAC2_A6 = analog4_DAC2_A6, IO_IS = analogDAC2A[6]
    PORT    analog_DAC2_A7 = analog4_DAC2_A7, IO_IS = analogDAC2A[7]
    PORT    analog_DAC2_A8 = analog4_DAC2_A8, IO_IS = analogDAC2A[8]
    PORT    analog_DAC2_A9 = analog4_DAC2_A9, IO_IS = analogDAC2A[9]
    PORT    analog_DAC2_A10 = analog4_DAC2_A10, IO_IS = analogDAC2A[10]
    PORT    analog_DAC2_A11 = analog4_DAC2_A11, IO_IS = analogDAC2A[11]
    PORT    analog_DAC2_A12 = analog4_DAC2_A12, IO_IS = analogDAC2A[12]
    PORT    analog_DAC2_A13 = analog4_DAC2_A13, IO_IS = analogDAC2A[13]

    PORT    analog_DAC2_B0 = analog4_DAC2_B0, IO_IS = analogDAC2B[0]
    PORT    analog_DAC2_B1 = analog4_DAC2_B1, IO_IS = analogDAC2B[1]
    PORT    analog_DAC2_B2 = analog4_DAC2_B2, IO_IS = analogDAC2B[2]
    PORT    analog_DAC2_B3 = analog4_DAC2_B3, IO_IS = analogDAC2B[3]
    PORT    analog_DAC2_B4 = analog4_DAC2_B4, IO_IS = analogDAC2B[4]
    PORT    analog_DAC2_B5 = analog4_DAC2_B5, IO_IS = analogDAC2B[5]
    PORT    analog_DAC2_B6 = analog4_DAC2_B6, IO_IS = analogDAC2B[6]
    PORT    analog_DAC2_B7 = analog4_DAC2_B7, IO_IS = analogDAC2B[7]
    PORT    analog_DAC2_B8 = analog4_DAC2_B8, IO_IS = analogDAC2B[8]
    PORT    analog_DAC2_B9 = analog4_DAC2_B9, IO_IS = analogDAC2B[9]
    PORT    analog_DAC2_B10 = analog4_DAC2_B10, IO_IS = analogDAC2B[10]
    PORT    analog_DAC2_B11 = analog4_DAC2_B11, IO_IS = analogDAC2B[11]
    PORT    analog_DAC2_B12 = analog4_DAC2_B12, IO_IS = analogDAC2B[12]
    PORT    analog_DAC2_B13 = analog4_DAC2_B13, IO_IS = analogDAC2B[13]

    PORT    analog_DAC1_sleep = analog4_DAC1_sleep
    PORT    analog_DAC2_sleep = analog4_DAC2_sleep

    PORT    analog_ADC_A0 = analog4_ADC_A0, IO_IS = analogADCA[0]
    PORT    analog_ADC_A1 = analog4_ADC_A1, IO_IS = analogADCA[1]
    PORT    analog_ADC_A2 = analog4_ADC_A2, IO_IS = analogADCA[2]
    PORT    analog_ADC_A3 = analog4_ADC_A3, IO_IS = analogADCA[3]
    PORT    analog_ADC_A4 = analog4_ADC_A4, IO_IS = analogADCA[4]
    PORT    analog_ADC_A5 = analog4_ADC_A5, IO_IS = analogADCA[5]
    PORT    analog_ADC_A6 = analog4_ADC_A6, IO_IS = analogADCA[6]
    PORT    analog_ADC_A7 = analog4_ADC_A7, IO_IS = analogADCA[7]
    PORT    analog_ADC_A8 = analog4_ADC_A8, IO_IS = analogADCA[8]
    PORT    analog_ADC_A9 = analog4_ADC_A9, IO_IS = analogADCA[9]
    PORT    analog_ADC_A10 = analog4_ADC_A10, IO_IS = analogADCA[10]
    PORT    analog_ADC_A11 = analog4_ADC_A11, IO_IS = analogADCA[11]
    PORT    analog_ADC_A12 = analog4_ADC_A12, IO_IS = analogADCA[12]
    PORT    analog_ADC_A13 = analog4_ADC_A13, IO_IS = analogADCA[13]

    PORT    analog_ADC_B0 = analog4_ADC_B0, IO_IS = analogADCB[0]
    PORT    analog_ADC_B1 = analog4_ADC_B1, IO_IS = analogADCB[1]
    PORT    analog_ADC_B2 = analog4_ADC_B2, IO_IS = analogADCB[2]
    PORT    analog_ADC_B3 = analog4_ADC_B3, IO_IS = analogADCB[3]
    PORT    analog_ADC_B4 = analog4_ADC_B4, IO_IS = analogADCB[4]
    PORT    analog_ADC_B5 = analog4_ADC_B5, IO_IS = analogADCB[5]
    PORT    analog_ADC_B6 = analog4_ADC_B6, IO_IS = analogADCB[6]
    PORT    analog_ADC_B7 = analog4_ADC_B7, IO_IS = analogADCB[7]
    PORT    analog_ADC_B8 = analog4_ADC_B8, IO_IS = analogADCB[8]
    PORT    analog_ADC_B9 = analog4_ADC_B9, IO_IS = analogADCB[9]
    PORT    analog_ADC_B10 = analog4_ADC_B10, IO_IS = analogADCB[10]
    PORT    analog_ADC_B11 = analog4_ADC_B11, IO_IS = analogADCB[11]
    PORT    analog_ADC_B12 = analog4_ADC_B12, IO_IS = analogADCB[12]
    PORT    analog_ADC_B13 = analog4_ADC_B13, IO_IS = analogADCB[13]

    PORT    analog_ADC_DFS = analog4_ADC_DFS
    PORT    analog_ADC_DCS = analog4_ADC_DCS
    PORT    analog_ADC_pdwnA = analog4_ADC_pdwnA
    PORT    analog_ADC_pdwnB = analog4_ADC_pdwnB
    PORT    analog_ADC_otrA = analog4_ADC_otrA
    PORT    analog_ADC_otrB = analog4_ADC_otrB
    
    PORT    analog_LED0 = analog4_LED0, IO_IS = analogLED[0]
    PORT    analog_LED1 = analog4_LED1, IO_IS = analogLED[1]
    PORT    analog_LED2 = analog4_LED2, IO_IS = analogLED[2]
    
END

# One user I/O board controller handles a single board
#  The user can enabled up to four controllers (one per slot)
BEGIN IO_INTERFACE
    ATTRIBUTE IOTYPE = XIL_USERIOBOARD_V1
    ATTRIBUTE INSTANCE = user_io_board_controller_slot1
    ATTRIBUTE EXCLUSIVE = slot1

    #Hardware reset input (same as software reset)
    PORT reset = userio_board_slot1_reset, IO_IS = userio_board_reset

    #LCD SPI interface
    PORT sdi = user_ioboard_slot1_sdi, IO_IS = userio_board_sdi
    PORT scl = userio_board_slot1_scl, IO_IS = userio_board_scl
    PORT resetlcd = userio_board_slot1_resetlcd, IO_IS = userio_board_resetlcd
    PORT cs = userio_board_slot1_cs, IO_IS = userio_board_cs

    #Buzzer output
    PORT buzzer = userio_board_slot1_buzzer, IO_IS = userio_board_buzzer

    #Trackball I/O
    PORT trackball_yscn = userio_board_slot1_trackball_yscn, IO_IS = userio_board_trackball_yscn
    PORT trackball_sel1 = userio_board_slot1_trackball_sel1, IO_IS = userio_board_trackball_sel1
    PORT trackball_xscn = userio_board_slot1_trackball_xscn, IO_IS = userio_board_trackball_xscn
    PORT trackball_sel2 = userio_board_slot1_trackball_sel2, IO_IS = userio_board_trackball_sel2
    PORT trackball_oyn = userio_board_slot1_trackball_oyn, IO_IS = userio_board_trackball_oyn
    PORT trackball_oy = userio_board_slot1_trackball_oy, IO_IS = userio_board_trackball_oy
    PORT trackball_oxn = userio_board_slot1_trackball_oxn, IO_IS = userio_board_trackball_oxn
    PORT trackball_ox = userio_board_slot1_trackball_ox, IO_IS = userio_board_trackball_ox

    #Eight LEDs
    PORT leds_0 = userio_board_slot1_leds_0, IO_IS = userio_board_leds[0]
    PORT leds_1 = userio_board_slot1_leds_1, IO_IS = userio_board_leds[1]
    PORT leds_2 = userio_board_slot1_leds_2, IO_IS = userio_board_leds[2]
    PORT leds_3 = userio_board_slot1_leds_3, IO_IS = userio_board_leds[3]
    PORT leds_4 = userio_board_slot1_leds_4, IO_IS = userio_board_leds[4]
    PORT leds_5 = userio_board_slot1_leds_5, IO_IS = userio_board_leds[5]
    PORT leds_6 = userio_board_slot1_leds_6, IO_IS = userio_board_leds[6]
    PORT leds_7 = userio_board_slot1_leds_7, IO_IS = userio_board_leds[7]

    #DIP switch
    PORT dip_switch_0 = userio_board_slot1_dip_switch_0, IO_IS = userio_board_dip_switch[0]
    PORT dip_switch_1 = userio_board_slot1_dip_switch_1, IO_IS = userio_board_dip_switch[1]
    PORT dip_switch_2 = userio_board_slot1_dip_switch_2, IO_IS = userio_board_dip_switch[2]
    PORT dip_switch_3 = userio_board_slot1_dip_switch_3, IO_IS = userio_board_dip_switch[3]

    #Six small push buttons
    PORT buttons_small_0 = userio_board_slot1_buttons_small_0, IO_IS = userio_board_buttons_small[0]
    PORT buttons_small_1 = userio_board_slot1_buttons_small_1, IO_IS = userio_board_buttons_small[1]
    PORT buttons_small_2 = userio_board_slot1_buttons_small_2, IO_IS = userio_board_buttons_small[2]
    PORT buttons_small_3 = userio_board_slot1_buttons_small_3, IO_IS = userio_board_buttons_small[3]
    PORT buttons_small_4 = userio_board_slot1_buttons_small_4, IO_IS = userio_board_buttons_small[4]
    PORT buttons_small_5 = userio_board_slot1_buttons_small_5, IO_IS = userio_board_buttons_small[5]

    #Two big push buttons
    PORT buttons_big_0 = userio_board_slot1_buttons_big_0, IO_IS = userio_board_buttons_big[0]
    PORT buttons_big_1 = userio_board_slot1_buttons_big_1, IO_IS = userio_board_buttons_big[1]
END

# EEPROM Serial Number and Memory interface
BEGIN IO_INTERFACE
    ATTRIBUTE IOTYPE = WARP_EEPROM_V1
    ATTRIBUTE INSTANCE = eeprom_controller
    PORT DQ0   = EEPROM_0_DQ0, INITIALVAL = VCC
#   PORT DQ0_T = 
#   PORT DQ0_O = 
#   PORT DQ0_I =

#   PORT DQ1   =
    PORT DQ1_T = DQ1_T_user_EEPROM_IO_T
    PORT DQ1_O = DQ1_O_user_EEPROM_IO_O
    PORT DQ1_I = DQ1_I_user_EEPROM_IO_I, INITIALVAL = VCC

#   PORT DQ2   =
    PORT DQ2_T = DQ2_T_user_EEPROM_IO_T
    PORT DQ2_O = DQ2_O_user_EEPROM_IO_O
    PORT DQ2_I = DQ2_I_user_EEPROM_IO_I, INITIALVAL = VCC

#   PORT DQ3   =
    PORT DQ3_T = DQ3_T_user_EEPROM_IO_T
    PORT DQ3_O = DQ3_O_user_EEPROM_IO_O
    PORT DQ3_I = DQ3_I_user_EEPROM_IO_I, INITIALVAL = VCC

#   PORT DQ4   =
    PORT DQ4_T = DQ4_T_user_EEPROM_IO_T
    PORT DQ4_O = DQ4_O_user_EEPROM_IO_O
    PORT DQ4_I = DQ4_I_user_EEPROM_IO_I, INITIALVAL = VCC

#   PORT DQ5   =
#   PORT DQ5_T =
#   PORT DQ5_O =
    PORT DQ5_I = "net_vcc"

#   PORT DQ6   =
#   PORT DQ6_T =
#   PORT DQ6_O =
    PORT DQ6_I = "net_vcc"

#   PORT DQ7   =
#   PORT DQ7_T =
#   PORT DQ7_O =
    PORT DQ7_I = "net_vcc"
END


# This is the FPGA definition. First characterize the processor.
BEGIN FPGA
    ATTRIBUTE INSTANCE = fpga_0
    ATTRIBUTE FAMILY = virtex4
    ATTRIBUTE DEVICE =  XC4VFX100
    ATTRIBUTE PACKAGE =  FF1517
    ATTRIBUTE SPEED_GRADE = -11
    ATTRIBUTE JTAG_POSITION = 2 #SysaceCF is in position 1

### Clock ###  Use the same port connection names as defined above.
    PORT CLK_100 = CLK_100MHZ_OSC, UCF_NET_STRING=("LOC=AM21", "IOSTANDARD = LVTTL")
    PORT CLK_40 = CLK_40MHZ_OSC, UCF_NET_STRING=("LOC=AN20", "IOSTANDARD = LVTTL")
#   PORT CLK_1 = CLK_X_OSC, UCF_NET_STRING=("LOC=AL20", "IOSTANDARD = LVTTL")

### RESET ### #Down push button
    PORT RESET = CONN_INIT_INIT, UCF_NET_STRING=("LOC=M21", "IOSTANDARD = LVCMOS25") 

### LED ###
    PORT LED0 = CONN_LEDs_LED0, UCF_NET_STRING=("LOC=N24", "IOSTANDARD = LVCMOS25")
    PORT LED1 = CONN_LEDs_LED1, UCF_NET_STRING=("LOC=N20", "IOSTANDARD = LVCMOS25")
    PORT LED2 = CONN_LEDs_LED2, UCF_NET_STRING=("LOC=L18", "IOSTANDARD = LVCMOS25")
    PORT LED3 = CONN_LEDs_LED3, UCF_NET_STRING=("LOC=N18", "IOSTANDARD = LVCMOS25")
    PORT LED4 = CONN_LEDs_LED4, UCF_NET_STRING=("LOC=M18", "IOSTANDARD = LVCMOS25")
    PORT LED5 = CONN_LEDs_LED5, UCF_NET_STRING=("LOC=M25", "IOSTANDARD = LVCMOS25")
    PORT LED6 = CONN_LEDs_LED6, UCF_NET_STRING=("LOC=N19", "IOSTANDARD = LVCMOS25")
    PORT LED7 = CONN_LEDs_LED7, UCF_NET_STRING=("LOC=P19", "IOSTANDARD = LVCMOS25")

### PUSH BUTTONS ###
    PORT PUSHU = CONN_PUSHU, UCF_NET_STRING=("LOC=N23", "IOSTANDARD = LVCMOS25")
    PORT PUSHL = CONN_PUSHL, UCF_NET_STRING=("LOC=N22", "IOSTANDARD = LVCMOS25")
    PORT PUSHR = CONN_PUSHR, UCF_NET_STRING=("LOC=M23", "IOSTANDARD = LVCMOS25")
    PORT PUSHC = CONN_PUSHC, UCF_NET_STRING=("LOC=L23", "IOSTANDARD = LVCMOS25")

### IO Expander ###
    PORT IIC_CLK   = iic_scl, UCF_NET_STRING=("LOC=AK17", "IOSTANDARD = LVTTL")
    PORT IIC_DATA  = iic_sda, UCF_NET_STRING=("LOC=AL18", "IOSTANDARD = LVTTL")

### UART #0 ###
    PORT RXD_DB9 = CONN_RXD_DB9, UCF_NET_STRING=("LOC=L24", "IOSTANDARD = LVCMOS25")
    PORT TXD_DB9 = CONN_TXD_DB9, UCF_NET_STRING=("LOC=K24", "IOSTANDARD = LVCMOS25")

### UART #1 ###
    PORT RXD_USB = CONN_RXD_USB, UCF_NET_STRING=("LOC=C23", "IOSTANDARD = LVTTL")
    PORT TXD_USB = CONN_TXD_USB, UCF_NET_STRING=("LOC=AA23", "IOSTANDARD = LVTTL")

### SYSACE FLASH ###
    PORT SYSACE_CLK = sysace_clk, UCF_NET_STRING=("LOC=AJ21", "IOSTANDARD = LVTTL") # Input CLK
    PORT MPA00 = sysace_mpa_0, UCF_NET_STRING=("LOC=AJ16", "IOSTANDARD = LVTTL")
    PORT MPA01 = sysace_mpa_1, UCF_NET_STRING=("LOC=AH17", "IOSTANDARD = LVTTL")
    PORT MPA02 = sysace_mpa_2, UCF_NET_STRING=("LOC=AN18", "IOSTANDARD = LVTTL")
    PORT MPA03 = sysace_mpa_3, UCF_NET_STRING=("LOC=AL19", "IOSTANDARD = LVTTL")
    PORT MPA04 = sysace_mpa_4, UCF_NET_STRING=("LOC=AM16", "IOSTANDARD = LVTTL")
    PORT MPA05 = sysace_mpa_5, UCF_NET_STRING=("LOC=AJ19", "IOSTANDARD = LVTTL")
    PORT MPA06 = sysace_mpa_6, UCF_NET_STRING=("LOC=AL16", "IOSTANDARD = LVTTL")
    PORT MPD00 = sysace_mpd_0, UCF_NET_STRING=("LOC=AR17", "IOSTANDARD = LVTTL")
    PORT MPD01 = sysace_mpd_1, UCF_NET_STRING=("LOC=AP17", "IOSTANDARD = LVTTL")
    PORT MPD02 = sysace_mpd_2, UCF_NET_STRING=("LOC=AM18", "IOSTANDARD = LVTTL")
    PORT MPD03 = sysace_mpd_3, UCF_NET_STRING=("LOC=AK19", "IOSTANDARD = LVTTL")
    PORT MPD04 = sysace_mpd_4, UCF_NET_STRING=("LOC=AJ20", "IOSTANDARD = LVTTL")
    PORT MPD05 = sysace_mpd_5, UCF_NET_STRING=("LOC=AN17", "IOSTANDARD = LVTTL")
    PORT MPD06 = sysace_mpd_6, UCF_NET_STRING=("LOC=AM17", "IOSTANDARD = LVTTL")
    PORT MPD07 = sysace_mpd_7, UCF_NET_STRING=("LOC=AH15", "IOSTANDARD = LVTTL")
    PORT MPCE  = sysace_mpce, UCF_NET_STRING=("LOC=AK16", "IOSTANDARD = LVTTL")
    PORT MPOE  = sysace_mpoe, UCF_NET_STRING=("LOC=AJ17", "IOSTANDARD = LVTTL")
    PORT MPWE  = sysace_mpwe, UCF_NET_STRING=("LOC=AR18", "IOSTANDARD = LVTTL")
    PORT MPIRQ = sysace_mpirq, UCF_NET_STRING=("LOC=AG17", "IOSTANDARD = LVTTL")

### 4 Dip Switchs ###
    PORT SW_0 = SW_0, UCF_NET_STRING=("LOC=M17", "IOSTANDARD = LVCMOS25") 
    PORT SW_1 = SW_1, UCF_NET_STRING=("LOC=R18", "IOSTANDARD = LVCMOS25") 
    PORT SW_2 = SW_2, UCF_NET_STRING=("LOC=P17", "IOSTANDARD = LVCMOS25") 
    PORT SW_3 = SW_3, UCF_NET_STRING=("LOC=M16", "IOSTANDARD = LVCMOS25") 

### TEMAC ###
    # hard_temac ports
    PORT GMII_TXD_0_7 = GMII_TXD_0_7_s, UCF_NET_STRING=("LOC = K16", "IOSTANDARD = LVCMOS25")
    PORT GMII_TXD_0_6 = GMII_TXD_0_6_s, UCF_NET_STRING=("LOC = H17", "IOSTANDARD = LVCMOS25")
    PORT GMII_TXD_0_5 = GMII_TXD_0_5_s, UCF_NET_STRING=("LOC = J17", "IOSTANDARD = LVCMOS25")
    PORT GMII_TXD_0_4 = GMII_TXD_0_4_s, UCF_NET_STRING=("LOC = J16", "IOSTANDARD = LVCMOS25")
    PORT GMII_TXD_0_3 = GMII_TXD_0_3_s, UCF_NET_STRING=("LOC = G15", "IOSTANDARD = LVCMOS25")
    PORT GMII_TXD_0_2 = GMII_TXD_0_2_s, UCF_NET_STRING=("LOC = K17", "IOSTANDARD = LVCMOS25")
    PORT GMII_TXD_0_1 = GMII_TXD_0_1_s, UCF_NET_STRING=("LOC = E17", "IOSTANDARD = LVCMOS25")
    PORT GMII_TXD_0_0 = GMII_TXD_0_0_s, UCF_NET_STRING=("LOC = D17", "IOSTANDARD = LVCMOS25")
    PORT GMII_TX_EN_0 = GMII_TX_EN_0_s, UCF_NET_STRING=("LOC = C18", "IOSTANDARD = LVCMOS25")
    PORT GMII_TX_ER_0 = GMII_TX_ER_0_s, UCF_NET_STRING=("LOC = K18", "IOSTANDARD = LVCMOS25")
    PORT GMII_TX_CLK_0 = GMII_TX_CLK_0_s, UCF_NET_STRING=("LOC = F21", "IOSTANDARD = LVCMOS25")
    PORT GMII_RXD_0_7 = GMII_RXD_0_7_s, UCF_NET_STRING=("LOC = G21", "IOBDELAY=NONE", "IOSTANDARD = LVCMOS25")
    PORT GMII_RXD_0_6 = GMII_RXD_0_6_s, UCF_NET_STRING=("LOC = E23", "IOBDELAY=NONE", "IOSTANDARD = LVCMOS25")
    PORT GMII_RXD_0_5 = GMII_RXD_0_5_s, UCF_NET_STRING=("LOC = G23", "IOBDELAY=NONE", "IOSTANDARD = LVCMOS25")
    PORT GMII_RXD_0_4 = GMII_RXD_0_4_s, UCF_NET_STRING=("LOC = J24", "IOBDELAY=NONE", "IOSTANDARD = LVCMOS25")
    PORT GMII_RXD_0_3 = GMII_RXD_0_3_s, UCF_NET_STRING=("LOC = H22", "IOBDELAY=NONE", "IOSTANDARD = LVCMOS25")
    PORT GMII_RXD_0_2 = GMII_RXD_0_2_s, UCF_NET_STRING=("LOC = E22", "IOBDELAY=NONE", "IOSTANDARD = LVCMOS25")
    PORT GMII_RXD_0_1 = GMII_RXD_0_1_s, UCF_NET_STRING=("LOC = E21", "IOBDELAY=NONE", "IOSTANDARD = LVCMOS25")
    PORT GMII_RXD_0_0 = GMII_RXD_0_0_s, UCF_NET_STRING=("LOC = K23", "IOBDELAY=NONE", "IOSTANDARD = LVCMOS25")
    PORT GMII_RX_DV_0 = GMII_RX_DV_0_s, UCF_NET_STRING=("LOC = H23", "IOBDELAY=NONE", "IOSTANDARD = LVCMOS25")
    PORT GMII_RX_ER_0 = GMII_RX_ER_0_s, UCF_NET_STRING=("LOC = F23", "IOBDELAY=NONE", "IOSTANDARD = LVCMOS25")
    PORT GMII_RX_CLK_0 = GMII_RX_CLK_0_s, UCF_NET_STRING=("LOC = J22", "IOSTANDARD = LVCMOS25")
    PORT MII_TX_CLK_0 = MII_TX_CLK_0_s, UCF_NET_STRING=("LOC = G22", "PERIOD = 40 ns", "MAXSKEW= 1.0 ns", "IOSTANDARD = LVCMOS25")
    PORT GMII_COL_0 = GMII_COL_0_s, UCF_NET_STRING=("LOC = G17", "IOBDELAY=NONE", "IOSTANDARD = LVCMOS25")
    PORT GMII_CRS_0 = GMII_CRS_0_s, UCF_NET_STRING=("LOC = H24", "IOBDELAY=NONE", "IOSTANDARD = LVCMOS25")
    PORT MDIO_0 = MDIO_0_s, UCF_NET_STRING=("LOC = L16", "IOSTANDARD = LVCMOS25")
    PORT MDC_0 = MDC_0_s, UCF_NET_STRING=("LOC = H15", "IOSTANDARD = LVCMOS25")
    # plb_temac ports
    PORT PhyResetN = phy_rst_n_s, UCF_NET_STRING=("LOC = C17", "TIG", "IOSTANDARD = LVCMOS25")

### Clock Board Configurator ###
    PORT clk_board_radio_DO = clk_board_radio_DO, UCF_NET_STRING=("LOC=AN19", "IOSTANDARD=LVTTL", "SLEW = SLOW")
    PORT clk_board_radio_CS = clk_board_radio_CS, UCF_NET_STRING=("LOC=AP19", "IOSTANDARD=LVTTL", "SLEW = SLOW")
    PORT clk_board_radio_EN = clk_board_radio_EN, UCF_NET_STRING=("LOC=AR19", "IOSTANDARD=LVTTL", "SLEW = SLOW")
    PORT clk_board_radio_CLK = clk_board_radio_CLK, UCF_NET_STRING=("LOC=AM20", "IOSTANDARD=LVTTL", "SLEW = SLOW")
    PORT clk_board_logic_DO = clk_board_logic_DO, UCF_NET_STRING=("LOC=AR21", "IOSTANDARD=LVTTL", "SLEW = SLOW")
    PORT clk_board_logic_CS = clk_board_logic_CS, UCF_NET_STRING=("LOC=AL21", "IOSTANDARD=LVTTL", "SLEW = SLOW")
    PORT clk_board_logic_EN = clk_board_logic_EN, UCF_NET_STRING=("LOC=AK21", "IOSTANDARD=LVTTL", "SLEW = SLOW")
    PORT clk_board_logic_CLK = clk_board_logic_CLK, UCF_NET_STRING=("LOC=AN22", "IOSTANDARD=LVTTL", "SLEW = SLOW")

#   ### DDR2 256MB ###
#       PORT ddr2_256mb_ODT = ddr2_256mb_odt, UCF_NET_STRING=("LOC=AT16", "IOSTANDARD = SSTL18_I")
#       PORT ddr2_256mb_ADDR0 = ddr2_256mb_addr_0, UCF_NET_STRING=("LOC=AH13", "IOSTANDARD = SSTL18_I")
#       PORT ddr2_256mb_ADDR1 = ddr2_256mb_addr_1, UCF_NET_STRING=("LOC=AR16", "IOSTANDARD = SSTL18_I")
#       PORT ddr2_256mb_ADDR2 = ddr2_256mb_addr_2, UCF_NET_STRING=("LOC=AH14", "IOSTANDARD = SSTL18_I")
#       PORT ddr2_256mb_ADDR3 = ddr2_256mb_addr_3, UCF_NET_STRING=("LOC=AU13", "IOSTANDARD = SSTL18_I")
#       PORT ddr2_256mb_ADDR4 = ddr2_256mb_addr_4, UCF_NET_STRING=("LOC=AP25", "IOSTANDARD = SSTL18_I")
#       PORT ddr2_256mb_ADDR5 = ddr2_256mb_addr_5, UCF_NET_STRING=("LOC=AN30", "IOSTANDARD = SSTL18_I")
#       PORT ddr2_256mb_ADDR6 = ddr2_256mb_addr_6, UCF_NET_STRING=("LOC=AR29", "IOSTANDARD = SSTL18_I")
#       PORT ddr2_256mb_ADDR7 = ddr2_256mb_addr_7, UCF_NET_STRING=("LOC=AT29", "IOSTANDARD = SSTL18_I")
#       PORT ddr2_256mb_ADDR8 = ddr2_256mb_addr_8, UCF_NET_STRING=("LOC=AL30", "IOSTANDARD = SSTL18_I")
#       PORT ddr2_256mb_ADDR9 = ddr2_256mb_addr_9, UCF_NET_STRING=("LOC=AP30", "IOSTANDARD = SSTL18_I")
#       PORT ddr2_256mb_ADDR10 = ddr2_256mb_addr_10, UCF_NET_STRING=("LOC=AM30", "IOSTANDARD = SSTL18_I")
#       PORT ddr2_256mb_ADDR11 = ddr2_256mb_addr_11, UCF_NET_STRING=("LOC=AL29", "IOSTANDARD = SSTL18_I")
#       PORT ddr2_256mb_ADDR12 = ddr2_256mb_addr_12, UCF_NET_STRING=("LOC=AN29", "IOSTANDARD = SSTL18_I")
#       PORT ddr2_256mb_BANKADDR0 = ddr2_256mb_bankaddr_0, UCF_NET_STRING=("LOC=AP14", "IOSTANDARD = SSTL18_I")
#       PORT ddr2_256mb_BANKADDR1 = ddr2_256mb_bankaddr_1, UCF_NET_STRING=("LOC=AN13", "IOSTANDARD = SSTL18_I")
#       PORT ddr2_256mb_CASN = ddr2_256mb_casn, UCF_NET_STRING=("LOC=AU12", "IOSTANDARD = SSTL18_I")
#   #   PORT ddr2_256mb_CKE1 = ddr2_256mb_cke_1, UCF_NET_STRING=("LOC=AK11", "IOSTANDARD = SSTL18_I")
#       PORT ddr2_256mb_CKE0 = ddr2_256mb_cke_0, UCF_NET_STRING=("LOC=AP16", "IOSTANDARD = SSTL18_I")
#   #   PORT ddr2_256mb_CSN1 = ddr2_256mb_csn_1, UCF_NET_STRING=("LOC=AT13", "IOSTANDARD = SSTL18_I")
#       PORT ddr2_256mb_CSN0 = ddr2_256mb_csn_0, UCF_NET_STRING=("LOC=AK14", "IOSTANDARD = SSTL18_I")
#       PORT ddr2_256mb_RASN = ddr2_256mb_rasn, UCF_NET_STRING=("LOC=AJ11", "IOSTANDARD = SSTL18_I")
#       PORT ddr2_256mb_WEN = ddr2_256mb_wen, UCF_NET_STRING=("LOC=AR13", "IOSTANDARD = SSTL18_I")
#       PORT ddr2_256mb_DM0 = ddr2_256mb_dm_0, UCF_NET_STRING=("LOC=AU36", "IOSTANDARD = SSTL18_I")
#       PORT ddr2_256mb_DM1 = ddr2_256mb_dm_1, UCF_NET_STRING=("LOC=AR34", "IOSTANDARD = SSTL18_I")
#       PORT ddr2_256mb_DM2 = ddr2_256mb_dm_2, UCF_NET_STRING=("LOC=AK31", "IOSTANDARD = SSTL18_I")
#       PORT ddr2_256mb_DM3 = ddr2_256mb_dm_3, UCF_NET_STRING=("LOC=AN28", "IOSTANDARD = SSTL18_I")
#       PORT ddr2_256mb_DM4 = ddr2_256mb_dm_4, UCF_NET_STRING=("LOC=AU16", "IOSTANDARD = SSTL18_I")
#       PORT ddr2_256mb_DM5 = ddr2_256mb_dm_5, UCF_NET_STRING=("LOC=AP12", "IOSTANDARD = SSTL18_I")
#       PORT ddr2_256mb_DM6 = ddr2_256mb_dm_6, UCF_NET_STRING=("LOC=AP15", "IOSTANDARD = SSTL18_I")
#       PORT ddr2_256mb_DM7 = ddr2_256mb_dm_7, UCF_NET_STRING=("LOC=AJ12", "IOSTANDARD = SSTL18_I")
#       PORT ddr2_256mb_DQS0 = ddr2_256mb_dqs_0, UCF_NET_STRING=("LOC=AU26", "IOSTANDARD = DIFF_SSTL18_II")
#       PORT ddr2_256mb_DQS1 = ddr2_256mb_dqs_1, UCF_NET_STRING=("LOC=AT35", "IOSTANDARD = DIFF_SSTL18_II")
#       PORT ddr2_256mb_DQS2 = ddr2_256mb_dqs_2, UCF_NET_STRING=("LOC=AM28", "IOSTANDARD = DIFF_SSTL18_II")
#       PORT ddr2_256mb_DQS3 = ddr2_256mb_dqs_3, UCF_NET_STRING=("LOC=AT31", "IOSTANDARD = DIFF_SSTL18_II")
#       PORT ddr2_256mb_DQS4 = ddr2_256mb_dqs_4, UCF_NET_STRING=("LOC=AN8", "IOSTANDARD = DIFF_SSTL18_II")
#       PORT ddr2_256mb_DQS5 = ddr2_256mb_dqs_5, UCF_NET_STRING=("LOC=AT15", "IOSTANDARD = DIFF_SSTL18_II")
#       PORT ddr2_256mb_DQS6 = ddr2_256mb_dqs_6, UCF_NET_STRING=("LOC=AT11", "IOSTANDARD = DIFF_SSTL18_II")
#       PORT ddr2_256mb_DQS7 = ddr2_256mb_dqs_7, UCF_NET_STRING=("LOC=AL13", "IOSTANDARD = DIFF_SSTL18_II")
#       PORT ddr2_256mb_DQSn0 = ddr2_256mb_dqsn_0, UCF_NET_STRING=("LOC=AT26", "IOSTANDARD = DIFF_SSTL18_II")
#       PORT ddr2_256mb_DQSn1 = ddr2_256mb_dqsn_1, UCF_NET_STRING=("LOC=AU35", "IOSTANDARD = DIFF_SSTL18_II")
#       PORT ddr2_256mb_DQSn2 = ddr2_256mb_dqsn_2, UCF_NET_STRING=("LOC=AL28", "IOSTANDARD = DIFF_SSTL18_II")
#       PORT ddr2_256mb_DQSn3 = ddr2_256mb_dqsn_3, UCF_NET_STRING=("LOC=AU31", "IOSTANDARD = DIFF_SSTL18_II")
#       PORT ddr2_256mb_DQSn4 = ddr2_256mb_dqsn_4, UCF_NET_STRING=("LOC=AN7", "IOSTANDARD = DIFF_SSTL18_II")
#       PORT ddr2_256mb_DQSn5 = ddr2_256mb_dqsn_5, UCF_NET_STRING=("LOC=AU15", "IOSTANDARD = DIFF_SSTL18_II")
#       PORT ddr2_256mb_DQSn6 = ddr2_256mb_dqsn_6, UCF_NET_STRING=("LOC=AU11", "IOSTANDARD = DIFF_SSTL18_II")
#       PORT ddr2_256mb_DQSn7 = ddr2_256mb_dqsn_7, UCF_NET_STRING=("LOC=AM13", "IOSTANDARD = DIFF_SSTL18_II")
#       PORT ddr2_256mb_DQ0 = ddr2_256mb_dq_0, UCF_NET_STRING=("LOC=AR27", "IOSTANDARD = SSTL18_I")
#       PORT ddr2_256mb_DQ1 = ddr2_256mb_dq_1, UCF_NET_STRING=("LOC=AR26", "IOSTANDARD = SSTL18_I")
#       PORT ddr2_256mb_DQ2 = ddr2_256mb_dq_2, UCF_NET_STRING=("LOC=AM26", "IOSTANDARD = SSTL18_I")
#       PORT ddr2_256mb_DQ3 = ddr2_256mb_dq_3, UCF_NET_STRING=("LOC=AT24", "IOSTANDARD = SSTL18_I")
#       PORT ddr2_256mb_DQ4 = ddr2_256mb_dq_4, UCF_NET_STRING=("LOC=AP37", "IOSTANDARD = SSTL18_I")
#       PORT ddr2_256mb_DQ5 = ddr2_256mb_dq_5, UCF_NET_STRING=("LOC=AR37", "IOSTANDARD = SSTL18_I")
#       PORT ddr2_256mb_DQ6 = ddr2_256mb_dq_6, UCF_NET_STRING=("LOC=AP32", "IOSTANDARD = SSTL18_I")
#       PORT ddr2_256mb_DQ7 = ddr2_256mb_dq_7, UCF_NET_STRING=("LOC=AT36", "IOSTANDARD = SSTL18_I")
#       PORT ddr2_256mb_DQ8 = ddr2_256mb_dq_8, UCF_NET_STRING=("LOC=AR33", "IOSTANDARD = SSTL18_I")
#       PORT ddr2_256mb_DQ9 = ddr2_256mb_dq_9, UCF_NET_STRING=("LOC=AR24", "IOSTANDARD = SSTL18_I")
#       PORT ddr2_256mb_DQ10 = ddr2_256mb_dq_10, UCF_NET_STRING=("LOC=AM32", "IOSTANDARD = SSTL18_I")
#       PORT ddr2_256mb_DQ11 = ddr2_256mb_dq_11, UCF_NET_STRING=("LOC=AN32", "IOSTANDARD = SSTL18_I")
#       PORT ddr2_256mb_DQ12 = ddr2_256mb_dq_12, UCF_NET_STRING=("LOC=AR36", "IOSTANDARD = SSTL18_I")
#       PORT ddr2_256mb_DQ13 = ddr2_256mb_dq_13, UCF_NET_STRING=("LOC=AT34", "IOSTANDARD = SSTL18_I")
#       PORT ddr2_256mb_DQ14 = ddr2_256mb_dq_14, UCF_NET_STRING=("LOC=AP36", "IOSTANDARD = SSTL18_I")
#       PORT ddr2_256mb_DQ15 = ddr2_256mb_dq_15, UCF_NET_STRING=("LOC=AP26", "IOSTANDARD = SSTL18_I")
#       PORT ddr2_256mb_DQ16 = ddr2_256mb_dq_16, UCF_NET_STRING=("LOC=AM31", "IOSTANDARD = SSTL18_I")
#       PORT ddr2_256mb_DQ17 = ddr2_256mb_dq_17, UCF_NET_STRING=("LOC=AL31", "IOSTANDARD = SSTL18_I")
#       PORT ddr2_256mb_DQ18 = ddr2_256mb_dq_18, UCF_NET_STRING=("LOC=AU28", "IOSTANDARD = SSTL18_I")
#       PORT ddr2_256mb_DQ19 = ddr2_256mb_dq_19, UCF_NET_STRING=("LOC=AP24", "IOSTANDARD = SSTL18_I")
#       PORT ddr2_256mb_DQ20 = ddr2_256mb_dq_20, UCF_NET_STRING=("LOC=AR32", "IOSTANDARD = SSTL18_I")
#       PORT ddr2_256mb_DQ21 = ddr2_256mb_dq_21, UCF_NET_STRING=("LOC=AP31", "IOSTANDARD = SSTL18_I")
#       PORT ddr2_256mb_DQ22 = ddr2_256mb_dq_22, UCF_NET_STRING=("LOC=AU33", "IOSTANDARD = SSTL18_I")
#       PORT ddr2_256mb_DQ23 = ddr2_256mb_dq_23, UCF_NET_STRING=("LOC=AM27", "IOSTANDARD = SSTL18_I")
#       PORT ddr2_256mb_DQ24 = ddr2_256mb_dq_24, UCF_NET_STRING=("LOC=AT33", "IOSTANDARD = SSTL18_I")
#       PORT ddr2_256mb_DQ25 = ddr2_256mb_dq_25, UCF_NET_STRING=("LOC=AU27", "IOSTANDARD = SSTL18_I")
#       PORT ddr2_256mb_DQ26 = ddr2_256mb_dq_26, UCF_NET_STRING=("LOC=AN27", "IOSTANDARD = SSTL18_I")
#       PORT ddr2_256mb_DQ27 = ddr2_256mb_dq_27, UCF_NET_STRING=("LOC=AR31", "IOSTANDARD = SSTL18_I")
#       PORT ddr2_256mb_DQ28 = ddr2_256mb_dq_28, UCF_NET_STRING=("LOC=AU32", "IOSTANDARD = SSTL18_I")
#       PORT ddr2_256mb_DQ29 = ddr2_256mb_dq_29, UCF_NET_STRING=("LOC=AU30", "IOSTANDARD = SSTL18_I")
#       PORT ddr2_256mb_DQ30 = ddr2_256mb_dq_30, UCF_NET_STRING=("LOC=AT30", "IOSTANDARD = SSTL18_I")
#       PORT ddr2_256mb_DQ31 = ddr2_256mb_dq_31, UCF_NET_STRING=("LOC=AT28", "IOSTANDARD = SSTL18_I")
#       PORT ddr2_256mb_DQ32 = ddr2_256mb_dq_32, UCF_NET_STRING=("LOC=AR11", "IOSTANDARD = SSTL18_I")
#       PORT ddr2_256mb_DQ33 = ddr2_256mb_dq_33, UCF_NET_STRING=("LOC=AL10", "IOSTANDARD = SSTL18_I")
#       PORT ddr2_256mb_DQ34 = ddr2_256mb_dq_34, UCF_NET_STRING=("LOC=AP10", "IOSTANDARD = SSTL18_I")
#       PORT ddr2_256mb_DQ35 = ddr2_256mb_dq_35, UCF_NET_STRING=("LOC=AR8", "IOSTANDARD = SSTL18_I")
#       PORT ddr2_256mb_DQ36 = ddr2_256mb_dq_36, UCF_NET_STRING=("LOC=AT18", "IOSTANDARD = SSTL18_I")
#       PORT ddr2_256mb_DQ37 = ddr2_256mb_dq_37, UCF_NET_STRING=("LOC=AU17", "IOSTANDARD = SSTL18_I")
#       PORT ddr2_256mb_DQ38 = ddr2_256mb_dq_38, UCF_NET_STRING=("LOC=AH12", "IOSTANDARD = SSTL18_I")
#       PORT ddr2_256mb_DQ39 = ddr2_256mb_dq_39, UCF_NET_STRING=("LOC=AR14", "IOSTANDARD = SSTL18_I")
#       PORT ddr2_256mb_DQ40 = ddr2_256mb_dq_40, UCF_NET_STRING=("LOC=AR12", "IOSTANDARD = SSTL18_I")
#       PORT ddr2_256mb_DQ41 = ddr2_256mb_dq_41, UCF_NET_STRING=("LOC=AP7", "IOSTANDARD = SSTL18_I")
#       PORT ddr2_256mb_DQ42 = ddr2_256mb_dq_42, UCF_NET_STRING=("LOC=AR9", "IOSTANDARD = SSTL18_I")
#       PORT ddr2_256mb_DQ43 = ddr2_256mb_dq_43, UCF_NET_STRING=("LOC=AT9", "IOSTANDARD = SSTL18_I")
#       PORT ddr2_256mb_DQ44 = ddr2_256mb_dq_44, UCF_NET_STRING=("LOC=AL14", "IOSTANDARD = SSTL18_I")
#       PORT ddr2_256mb_DQ45 = ddr2_256mb_dq_45, UCF_NET_STRING=("LOC=AL11", "IOSTANDARD = SSTL18_I")
#       PORT ddr2_256mb_DQ46 = ddr2_256mb_dq_46, UCF_NET_STRING=("LOC=AJ14", "IOSTANDARD = SSTL18_I")
#       PORT ddr2_256mb_DQ47 = ddr2_256mb_dq_47, UCF_NET_STRING=("LOC=AM15", "IOSTANDARD = SSTL18_I")
#       PORT ddr2_256mb_DQ48 = ddr2_256mb_dq_48, UCF_NET_STRING=("LOC=AM10", "IOSTANDARD = SSTL18_I")
#       PORT ddr2_256mb_DQ49 = ddr2_256mb_dq_49, UCF_NET_STRING=("LOC=AP9", "IOSTANDARD = SSTL18_I")
#       PORT ddr2_256mb_DQ50 = ddr2_256mb_dq_50, UCF_NET_STRING=("LOC=AT8", "IOSTANDARD = SSTL18_I")
#       PORT ddr2_256mb_DQ51 = ddr2_256mb_dq_51, UCF_NET_STRING=("LOC=AL9", "IOSTANDARD = SSTL18_I")
#       PORT ddr2_256mb_DQ52 = ddr2_256mb_dq_52, UCF_NET_STRING=("LOC=AN15", "IOSTANDARD = SSTL18_I")
#       PORT ddr2_256mb_DQ53 = ddr2_256mb_dq_53, UCF_NET_STRING=("LOC=AN12", "IOSTANDARD = SSTL18_I")
#       PORT ddr2_256mb_DQ54 = ddr2_256mb_dq_54, UCF_NET_STRING=("LOC=AN14", "IOSTANDARD = SSTL18_I")
#       PORT ddr2_256mb_DQ55 = ddr2_256mb_dq_55, UCF_NET_STRING=("LOC=AK13", "IOSTANDARD = SSTL18_I")
#       PORT ddr2_256mb_DQ56 = ddr2_256mb_dq_56, UCF_NET_STRING=("LOC=AK9", "IOSTANDARD = SSTL18_I")
#       PORT ddr2_256mb_DQ57 = ddr2_256mb_dq_57, UCF_NET_STRING=("LOC=AU8", "IOSTANDARD = SSTL18_I")
#       PORT ddr2_256mb_DQ58 = ddr2_256mb_dq_58, UCF_NET_STRING=("LOC=AR7", "IOSTANDARD = SSTL18_I")
#       PORT ddr2_256mb_DQ59 = ddr2_256mb_dq_59, UCF_NET_STRING=("LOC=AJ10", "IOSTANDARD = SSTL18_I")
#       PORT ddr2_256mb_DQ60 = ddr2_256mb_dq_60, UCF_NET_STRING=("LOC=AK12", "IOSTANDARD = SSTL18_I")
#       PORT ddr2_256mb_DQ61 = ddr2_256mb_dq_61, UCF_NET_STRING=("LOC=AN10", "IOSTANDARD = SSTL18_I")
#       PORT ddr2_256mb_DQ62 = ddr2_256mb_dq_62, UCF_NET_STRING=("LOC=AT10", "IOSTANDARD = SSTL18_I")
#       PORT ddr2_256mb_DQ63 = ddr2_256mb_dq_63, UCF_NET_STRING=("LOC=AU10", "IOSTANDARD = SSTL18_I")
#       PORT ddr2_256mb_CLK0 = ddr2_256mb_clk_0, UCF_NET_STRING=("LOC=AP35", "IOSTANDARD = DIFF_SSTL18_II")
#       PORT ddr2_256mb_CLK1 = ddr2_256mb_clk_1, UCF_NET_STRING=("LOC=AK27", "IOSTANDARD = DIFF_SSTL18_II")
#       PORT ddr2_256mb_CLKN0 = ddr2_256mb_clkn_0, UCF_NET_STRING=("LOC=AP34", "IOSTANDARD = DIFF_SSTL18_II")
#       PORT ddr2_256mb_CLKN1 = ddr2_256mb_clkn_1, UCF_NET_STRING=("LOC=AL26", "IOSTANDARD = DIFF_SSTL18_II")

### DDR2 2GB ###
    PORT ddr2_2gb_ODT_0 = ddr2_2gb_odt_0, UCF_NET_STRING=("LOC=AT16", "IOSTANDARD = SSTL18_I")
    PORT ddr2_2gb_ODT_1 = ddr2_2gb_odt_1, UCF_NET_STRING=("LOC=AP11", "IOSTANDARD = SSTL18_I")
    PORT ddr2_2gb_ADDR0 = ddr2_2gb_addr_0, UCF_NET_STRING=("LOC=AH13", "IOSTANDARD = SSTL18_I")
    PORT ddr2_2gb_ADDR1 = ddr2_2gb_addr_1, UCF_NET_STRING=("LOC=AR16", "IOSTANDARD = SSTL18_I")
    PORT ddr2_2gb_ADDR2 = ddr2_2gb_addr_2, UCF_NET_STRING=("LOC=AH14", "IOSTANDARD = SSTL18_I")
    PORT ddr2_2gb_ADDR3 = ddr2_2gb_addr_3, UCF_NET_STRING=("LOC=AU13", "IOSTANDARD = SSTL18_I")
    PORT ddr2_2gb_ADDR4 = ddr2_2gb_addr_4, UCF_NET_STRING=("LOC=AP25", "IOSTANDARD = SSTL18_I")
    PORT ddr2_2gb_ADDR5 = ddr2_2gb_addr_5, UCF_NET_STRING=("LOC=AN30", "IOSTANDARD = SSTL18_I")
    PORT ddr2_2gb_ADDR6 = ddr2_2gb_addr_6, UCF_NET_STRING=("LOC=AR29", "IOSTANDARD = SSTL18_I")
    PORT ddr2_2gb_ADDR7 = ddr2_2gb_addr_7, UCF_NET_STRING=("LOC=AT29", "IOSTANDARD = SSTL18_I")
    PORT ddr2_2gb_ADDR8 = ddr2_2gb_addr_8, UCF_NET_STRING=("LOC=AL30", "IOSTANDARD = SSTL18_I")
    PORT ddr2_2gb_ADDR9 = ddr2_2gb_addr_9, UCF_NET_STRING=("LOC=AP30", "IOSTANDARD = SSTL18_I")
    PORT ddr2_2gb_ADDR10 = ddr2_2gb_addr_10, UCF_NET_STRING=("LOC=AM30", "IOSTANDARD = SSTL18_I")
    PORT ddr2_2gb_ADDR11 = ddr2_2gb_addr_11, UCF_NET_STRING=("LOC=AL29", "IOSTANDARD = SSTL18_I")
    PORT ddr2_2gb_ADDR12 = ddr2_2gb_addr_12, UCF_NET_STRING=("LOC=AN29", "IOSTANDARD = SSTL18_I")
    PORT ddr2_2gb_ADDR13 = ddr2_2gb_addr_13, UCF_NET_STRING=("LOC=AK29", "IOSTANDARD = SSTL18_I")
    PORT ddr2_2gb_BANKADDR0 = ddr2_2gb_bankaddr_0, UCF_NET_STRING=("LOC=AP14", "IOSTANDARD = SSTL18_I")
    PORT ddr2_2gb_BANKADDR1 = ddr2_2gb_bankaddr_1, UCF_NET_STRING=("LOC=AN13", "IOSTANDARD = SSTL18_I")
    PORT ddr2_2gb_BANKADDR2 = ddr2_2gb_bankaddr_2, UCF_NET_STRING=("LOC=AT14", "IOSTANDARD = SSTL18_I")
    PORT ddr2_2gb_CASN = ddr2_2gb_casn, UCF_NET_STRING=("LOC=AU12", "IOSTANDARD = SSTL18_I")
    PORT ddr2_2gb_CKE1 = ddr2_2gb_cke_1, UCF_NET_STRING=("LOC=AK11", "IOSTANDARD = SSTL18_I")
    PORT ddr2_2gb_CKE0 = ddr2_2gb_cke_0, UCF_NET_STRING=("LOC=AP16", "IOSTANDARD = SSTL18_I")
    PORT ddr2_2gb_CSN1 = ddr2_2gb_csn_1, UCF_NET_STRING=("LOC=AT13", "IOSTANDARD = SSTL18_I")
    PORT ddr2_2gb_CSN0 = ddr2_2gb_csn_0, UCF_NET_STRING=("LOC=AK14", "IOSTANDARD = SSTL18_I")
    PORT ddr2_2gb_RASN = ddr2_2gb_rasn, UCF_NET_STRING=("LOC=AJ11", "IOSTANDARD = SSTL18_I")
    PORT ddr2_2gb_WEN = ddr2_2gb_wen, UCF_NET_STRING=("LOC=AR13", "IOSTANDARD = SSTL18_I")
    PORT ddr2_2gb_DM0 = ddr2_2gb_dm_0, UCF_NET_STRING=("LOC=AU36", "IOSTANDARD = SSTL18_I")
    PORT ddr2_2gb_DM1 = ddr2_2gb_dm_1, UCF_NET_STRING=("LOC=AR34", "IOSTANDARD = SSTL18_I")
    PORT ddr2_2gb_DM2 = ddr2_2gb_dm_2, UCF_NET_STRING=("LOC=AK31", "IOSTANDARD = SSTL18_I")
    PORT ddr2_2gb_DM3 = ddr2_2gb_dm_3, UCF_NET_STRING=("LOC=AN28", "IOSTANDARD = SSTL18_I")
    PORT ddr2_2gb_DM4 = ddr2_2gb_dm_4, UCF_NET_STRING=("LOC=AU16", "IOSTANDARD = SSTL18_I")
    PORT ddr2_2gb_DM5 = ddr2_2gb_dm_5, UCF_NET_STRING=("LOC=AP12", "IOSTANDARD = SSTL18_I")
    PORT ddr2_2gb_DM6 = ddr2_2gb_dm_6, UCF_NET_STRING=("LOC=AP15", "IOSTANDARD = SSTL18_I")
    PORT ddr2_2gb_DM7 = ddr2_2gb_dm_7, UCF_NET_STRING=("LOC=AJ12", "IOSTANDARD = SSTL18_I")
    PORT ddr2_2gb_DQS0 = ddr2_2gb_dqs_0, UCF_NET_STRING=("LOC=AU26", "IOSTANDARD = DIFF_SSTL18_II")
    PORT ddr2_2gb_DQS1 = ddr2_2gb_dqs_1, UCF_NET_STRING=("LOC=AT35", "IOSTANDARD = DIFF_SSTL18_II")
    PORT ddr2_2gb_DQS2 = ddr2_2gb_dqs_2, UCF_NET_STRING=("LOC=AM28", "IOSTANDARD = DIFF_SSTL18_II")
    PORT ddr2_2gb_DQS3 = ddr2_2gb_dqs_3, UCF_NET_STRING=("LOC=AT31", "IOSTANDARD = DIFF_SSTL18_II")
    PORT ddr2_2gb_DQS4 = ddr2_2gb_dqs_4, UCF_NET_STRING=("LOC=AN8", "IOSTANDARD = DIFF_SSTL18_II")
    PORT ddr2_2gb_DQS5 = ddr2_2gb_dqs_5, UCF_NET_STRING=("LOC=AT15", "IOSTANDARD = DIFF_SSTL18_II")
    PORT ddr2_2gb_DQS6 = ddr2_2gb_dqs_6, UCF_NET_STRING=("LOC=AT11", "IOSTANDARD = DIFF_SSTL18_II")
    PORT ddr2_2gb_DQS7 = ddr2_2gb_dqs_7, UCF_NET_STRING=("LOC=AL13", "IOSTANDARD = DIFF_SSTL18_II")
    PORT ddr2_2gb_DQSn0 = ddr2_2gb_dqsn_0, UCF_NET_STRING=("LOC=AT26", "IOSTANDARD = DIFF_SSTL18_II")
    PORT ddr2_2gb_DQSn1 = ddr2_2gb_dqsn_1, UCF_NET_STRING=("LOC=AU35", "IOSTANDARD = DIFF_SSTL18_II")
    PORT ddr2_2gb_DQSn2 = ddr2_2gb_dqsn_2, UCF_NET_STRING=("LOC=AL28", "IOSTANDARD = DIFF_SSTL18_II")
    PORT ddr2_2gb_DQSn3 = ddr2_2gb_dqsn_3, UCF_NET_STRING=("LOC=AU31", "IOSTANDARD = DIFF_SSTL18_II")
    PORT ddr2_2gb_DQSn4 = ddr2_2gb_dqsn_4, UCF_NET_STRING=("LOC=AN7", "IOSTANDARD = DIFF_SSTL18_II")
    PORT ddr2_2gb_DQSn5 = ddr2_2gb_dqsn_5, UCF_NET_STRING=("LOC=AU15", "IOSTANDARD = DIFF_SSTL18_II")
    PORT ddr2_2gb_DQSn6 = ddr2_2gb_dqsn_6, UCF_NET_STRING=("LOC=AU11", "IOSTANDARD = DIFF_SSTL18_II")
    PORT ddr2_2gb_DQSn7 = ddr2_2gb_dqsn_7, UCF_NET_STRING=("LOC=AM13", "IOSTANDARD = DIFF_SSTL18_II")
    PORT ddr2_2gb_DQ0 = ddr2_2gb_dq_0, UCF_NET_STRING=("LOC=AR27", "IOSTANDARD = SSTL18_I")
    PORT ddr2_2gb_DQ1 = ddr2_2gb_dq_1, UCF_NET_STRING=("LOC=AR26", "IOSTANDARD = SSTL18_I")
    PORT ddr2_2gb_DQ2 = ddr2_2gb_dq_2, UCF_NET_STRING=("LOC=AM26", "IOSTANDARD = SSTL18_I")
    PORT ddr2_2gb_DQ3 = ddr2_2gb_dq_3, UCF_NET_STRING=("LOC=AT24", "IOSTANDARD = SSTL18_I")
    PORT ddr2_2gb_DQ4 = ddr2_2gb_dq_4, UCF_NET_STRING=("LOC=AP37", "IOSTANDARD = SSTL18_I")
    PORT ddr2_2gb_DQ5 = ddr2_2gb_dq_5, UCF_NET_STRING=("LOC=AR37", "IOSTANDARD = SSTL18_I")
    PORT ddr2_2gb_DQ6 = ddr2_2gb_dq_6, UCF_NET_STRING=("LOC=AP32", "IOSTANDARD = SSTL18_I")
    PORT ddr2_2gb_DQ7 = ddr2_2gb_dq_7, UCF_NET_STRING=("LOC=AT36", "IOSTANDARD = SSTL18_I")
    PORT ddr2_2gb_DQ8 = ddr2_2gb_dq_8, UCF_NET_STRING=("LOC=AR33", "IOSTANDARD = SSTL18_I")
    PORT ddr2_2gb_DQ9 = ddr2_2gb_dq_9, UCF_NET_STRING=("LOC=AR24", "IOSTANDARD = SSTL18_I")
    PORT ddr2_2gb_DQ10 = ddr2_2gb_dq_10, UCF_NET_STRING=("LOC=AM32", "IOSTANDARD = SSTL18_I")
    PORT ddr2_2gb_DQ11 = ddr2_2gb_dq_11, UCF_NET_STRING=("LOC=AN32", "IOSTANDARD = SSTL18_I")
    PORT ddr2_2gb_DQ12 = ddr2_2gb_dq_12, UCF_NET_STRING=("LOC=AR36", "IOSTANDARD = SSTL18_I")
    PORT ddr2_2gb_DQ13 = ddr2_2gb_dq_13, UCF_NET_STRING=("LOC=AT34", "IOSTANDARD = SSTL18_I")
    PORT ddr2_2gb_DQ14 = ddr2_2gb_dq_14, UCF_NET_STRING=("LOC=AP36", "IOSTANDARD = SSTL18_I")
    PORT ddr2_2gb_DQ15 = ddr2_2gb_dq_15, UCF_NET_STRING=("LOC=AP26", "IOSTANDARD = SSTL18_I")
    PORT ddr2_2gb_DQ16 = ddr2_2gb_dq_16, UCF_NET_STRING=("LOC=AM31", "IOSTANDARD = SSTL18_I")
    PORT ddr2_2gb_DQ17 = ddr2_2gb_dq_17, UCF_NET_STRING=("LOC=AL31", "IOSTANDARD = SSTL18_I")
    PORT ddr2_2gb_DQ18 = ddr2_2gb_dq_18, UCF_NET_STRING=("LOC=AU28", "IOSTANDARD = SSTL18_I")
    PORT ddr2_2gb_DQ19 = ddr2_2gb_dq_19, UCF_NET_STRING=("LOC=AP24", "IOSTANDARD = SSTL18_I")
    PORT ddr2_2gb_DQ20 = ddr2_2gb_dq_20, UCF_NET_STRING=("LOC=AR32", "IOSTANDARD = SSTL18_I")
    PORT ddr2_2gb_DQ21 = ddr2_2gb_dq_21, UCF_NET_STRING=("LOC=AP31", "IOSTANDARD = SSTL18_I")
    PORT ddr2_2gb_DQ22 = ddr2_2gb_dq_22, UCF_NET_STRING=("LOC=AU33", "IOSTANDARD = SSTL18_I")
    PORT ddr2_2gb_DQ23 = ddr2_2gb_dq_23, UCF_NET_STRING=("LOC=AM27", "IOSTANDARD = SSTL18_I")
    PORT ddr2_2gb_DQ24 = ddr2_2gb_dq_24, UCF_NET_STRING=("LOC=AT33", "IOSTANDARD = SSTL18_I")
    PORT ddr2_2gb_DQ25 = ddr2_2gb_dq_25, UCF_NET_STRING=("LOC=AU27", "IOSTANDARD = SSTL18_I")
    PORT ddr2_2gb_DQ26 = ddr2_2gb_dq_26, UCF_NET_STRING=("LOC=AN27", "IOSTANDARD = SSTL18_I")
    PORT ddr2_2gb_DQ27 = ddr2_2gb_dq_27, UCF_NET_STRING=("LOC=AR31", "IOSTANDARD = SSTL18_I")
    PORT ddr2_2gb_DQ28 = ddr2_2gb_dq_28, UCF_NET_STRING=("LOC=AU32", "IOSTANDARD = SSTL18_I")
    PORT ddr2_2gb_DQ29 = ddr2_2gb_dq_29, UCF_NET_STRING=("LOC=AU30", "IOSTANDARD = SSTL18_I")
    PORT ddr2_2gb_DQ30 = ddr2_2gb_dq_30, UCF_NET_STRING=("LOC=AT30", "IOSTANDARD = SSTL18_I")
    PORT ddr2_2gb_DQ31 = ddr2_2gb_dq_31, UCF_NET_STRING=("LOC=AT28", "IOSTANDARD = SSTL18_I")
    PORT ddr2_2gb_DQ32 = ddr2_2gb_dq_32, UCF_NET_STRING=("LOC=AR11", "IOSTANDARD = SSTL18_I")
    PORT ddr2_2gb_DQ33 = ddr2_2gb_dq_33, UCF_NET_STRING=("LOC=AL10", "IOSTANDARD = SSTL18_I")
    PORT ddr2_2gb_DQ34 = ddr2_2gb_dq_34, UCF_NET_STRING=("LOC=AP10", "IOSTANDARD = SSTL18_I")
    PORT ddr2_2gb_DQ35 = ddr2_2gb_dq_35, UCF_NET_STRING=("LOC=AR8", "IOSTANDARD = SSTL18_I")
    PORT ddr2_2gb_DQ36 = ddr2_2gb_dq_36, UCF_NET_STRING=("LOC=AT18", "IOSTANDARD = SSTL18_I")
    PORT ddr2_2gb_DQ37 = ddr2_2gb_dq_37, UCF_NET_STRING=("LOC=AU17", "IOSTANDARD = SSTL18_I")
    PORT ddr2_2gb_DQ38 = ddr2_2gb_dq_38, UCF_NET_STRING=("LOC=AH12", "IOSTANDARD = SSTL18_I")
    PORT ddr2_2gb_DQ39 = ddr2_2gb_dq_39, UCF_NET_STRING=("LOC=AR14", "IOSTANDARD = SSTL18_I")
    PORT ddr2_2gb_DQ40 = ddr2_2gb_dq_40, UCF_NET_STRING=("LOC=AR12", "IOSTANDARD = SSTL18_I")
    PORT ddr2_2gb_DQ41 = ddr2_2gb_dq_41, UCF_NET_STRING=("LOC=AP7", "IOSTANDARD = SSTL18_I")
    PORT ddr2_2gb_DQ42 = ddr2_2gb_dq_42, UCF_NET_STRING=("LOC=AR9", "IOSTANDARD = SSTL18_I")
    PORT ddr2_2gb_DQ43 = ddr2_2gb_dq_43, UCF_NET_STRING=("LOC=AT9", "IOSTANDARD = SSTL18_I")
    PORT ddr2_2gb_DQ44 = ddr2_2gb_dq_44, UCF_NET_STRING=("LOC=AL14", "IOSTANDARD = SSTL18_I")
    PORT ddr2_2gb_DQ45 = ddr2_2gb_dq_45, UCF_NET_STRING=("LOC=AL11", "IOSTANDARD = SSTL18_I")
    PORT ddr2_2gb_DQ46 = ddr2_2gb_dq_46, UCF_NET_STRING=("LOC=AJ14", "IOSTANDARD = SSTL18_I")
    PORT ddr2_2gb_DQ47 = ddr2_2gb_dq_47, UCF_NET_STRING=("LOC=AM15", "IOSTANDARD = SSTL18_I")
    PORT ddr2_2gb_DQ48 = ddr2_2gb_dq_48, UCF_NET_STRING=("LOC=AM10", "IOSTANDARD = SSTL18_I")
    PORT ddr2_2gb_DQ49 = ddr2_2gb_dq_49, UCF_NET_STRING=("LOC=AP9", "IOSTANDARD = SSTL18_I")
    PORT ddr2_2gb_DQ50 = ddr2_2gb_dq_50, UCF_NET_STRING=("LOC=AT8", "IOSTANDARD = SSTL18_I")
    PORT ddr2_2gb_DQ51 = ddr2_2gb_dq_51, UCF_NET_STRING=("LOC=AL9", "IOSTANDARD = SSTL18_I")
    PORT ddr2_2gb_DQ52 = ddr2_2gb_dq_52, UCF_NET_STRING=("LOC=AN15", "IOSTANDARD = SSTL18_I")
    PORT ddr2_2gb_DQ53 = ddr2_2gb_dq_53, UCF_NET_STRING=("LOC=AN12", "IOSTANDARD = SSTL18_I")
    PORT ddr2_2gb_DQ54 = ddr2_2gb_dq_54, UCF_NET_STRING=("LOC=AN14", "IOSTANDARD = SSTL18_I")
    PORT ddr2_2gb_DQ55 = ddr2_2gb_dq_55, UCF_NET_STRING=("LOC=AK13", "IOSTANDARD = SSTL18_I")
    PORT ddr2_2gb_DQ56 = ddr2_2gb_dq_56, UCF_NET_STRING=("LOC=AK9", "IOSTANDARD = SSTL18_I")
    PORT ddr2_2gb_DQ57 = ddr2_2gb_dq_57, UCF_NET_STRING=("LOC=AU8", "IOSTANDARD = SSTL18_I")
    PORT ddr2_2gb_DQ58 = ddr2_2gb_dq_58, UCF_NET_STRING=("LOC=AR7", "IOSTANDARD = SSTL18_I")
    PORT ddr2_2gb_DQ59 = ddr2_2gb_dq_59, UCF_NET_STRING=("LOC=AJ10", "IOSTANDARD = SSTL18_I")
    PORT ddr2_2gb_DQ60 = ddr2_2gb_dq_60, UCF_NET_STRING=("LOC=AK12", "IOSTANDARD = SSTL18_I")
    PORT ddr2_2gb_DQ61 = ddr2_2gb_dq_61, UCF_NET_STRING=("LOC=AN10", "IOSTANDARD = SSTL18_I")
    PORT ddr2_2gb_DQ62 = ddr2_2gb_dq_62, UCF_NET_STRING=("LOC=AT10", "IOSTANDARD = SSTL18_I")
    PORT ddr2_2gb_DQ63 = ddr2_2gb_dq_63, UCF_NET_STRING=("LOC=AU10", "IOSTANDARD = SSTL18_I")
    PORT ddr2_2gb_CLK0 = ddr2_2gb_clk_0, UCF_NET_STRING=("LOC=AP35", "IOSTANDARD = DIFF_SSTL18_II")
    PORT ddr2_2gb_CLK1 = ddr2_2gb_clk_1, UCF_NET_STRING=("LOC=AK27", "IOSTANDARD = DIFF_SSTL18_II")
    PORT ddr2_2gb_CLKN0 = ddr2_2gb_clkn_0, UCF_NET_STRING=("LOC=AP34", "IOSTANDARD = DIFF_SSTL18_II")
    PORT ddr2_2gb_CLKN1 = ddr2_2gb_clkn_1, UCF_NET_STRING=("LOC=AL26", "IOSTANDARD = DIFF_SSTL18_II")


##Radio Bridge for Slot #1
#   PORT radio1_conv_clk_p = radio1_conv_clk_p, UCF_NET_STRING=("LOC=E11", "IOSTANDARD=LVDCI_33")
    PORT radio1_conv_clk_p = radio1_conv_clk_p, UCF_NET_STRING=("LOC=F10", "IOSTANDARD=LVTTL")
    PORT radio1_EEPROM_IO = radio1_EEPROM_IO, UCF_NET_STRING=("LOC=G12", "IOSTANDARD=LVTTL", "SLEW = SLOW", "DRIVE = 8")
    PORT dac1_spi_clk_pin = dac1_spi_clk, UCF_NET_STRING=("LOC=K7", "IOSTANDARD=LVTTL")
    PORT dac1_spi_cs_pin = dac1_spi_cs, UCF_NET_STRING=("LOC=J6", "IOSTANDARD=LVTTL")
    PORT dac1_spi_data_pin = dac1_spi_data, UCF_NET_STRING=("LOC=N5", "IOSTANDARD=LVTTL")
    PORT radio1_24PA_pin = radio1_24PA, UCF_NET_STRING=("LOC=G3", "IOSTANDARD=LVTTL")
    PORT radio1_5PA_pin = radio1_5PA, UCF_NET_STRING=("LOC=F3", "IOSTANDARD=LVTTL")
    PORT radio1_ANTSW0_pin = radio1_ANTSW0, UCF_NET_STRING=("LOC=H3", "IOSTANDARD=LVTTL")
    PORT radio1_ANTSW1_pin = radio1_ANTSW1, UCF_NET_STRING=("LOC=C5", "IOSTANDARD=LVTTL")
    PORT radio1_dac1_PLL_LOCK_pin = radio1_dac1_PLL_LOCK, UCF_NET_STRING=("LOC=K8", "IOSTANDARD=LVTTL")
    PORT radio1_dac1_RESET_pin = radio1_dac1_RESET, UCF_NET_STRING=("LOC=P7", "IOSTANDARD=LVTTL")
    PORT radio1_DIPSW0_pin = radio1_DIPSW0, UCF_NET_STRING=("LOC=J5", "IOSTANDARD=LVTTL")
    PORT radio1_DIPSW1_pin = radio1_DIPSW1, UCF_NET_STRING=("LOC=K3", "IOSTANDARD=LVTTL")
    PORT radio1_DIPSW2_pin = radio1_DIPSW2, UCF_NET_STRING=("LOC=P6", "IOSTANDARD=LVTTL")
    PORT radio1_DIPSW3_pin = radio1_DIPSW3, UCF_NET_STRING=("LOC=J4", "IOSTANDARD=LVTTL")
    PORT radio1_LD_pin = radio1_LD, UCF_NET_STRING=("LOC=L3", "IOSTANDARD=LVTTL")
    PORT radio1_LED0_pin = radio1_LED0, UCF_NET_STRING=("LOC=H4", "IOSTANDARD=LVTTL")
    PORT radio1_LED1_pin = radio1_LED1, UCF_NET_STRING=("LOC=C4", "IOSTANDARD=LVTTL")
    PORT radio1_LED2_pin = radio1_LED2, UCF_NET_STRING=("LOC=C8", "IOSTANDARD=LVTTL")
    PORT radio1_rssi_ADC_clk_pin = radio1_rssi_ADC_clk, UCF_NET_STRING=("LOC=H9", "IOSTANDARD=LVTTL")
    PORT radio1_RSSI_ADC_CLAMP_pin = radio1_RSSI_ADC_CLAMP, UCF_NET_STRING=("LOC=U12", "IOSTANDARD=LVTTL")
    PORT radio1_RSSI_ADC_D0_pin = radio1_RSSI_ADC_D0, UCF_NET_STRING=("LOC=T9", "IOSTANDARD=LVTTL", "PULLDOWN")
    PORT radio1_RSSI_ADC_D1_pin = radio1_RSSI_ADC_D1, UCF_NET_STRING=("LOC=L10", "IOSTANDARD=LVTTL", "PULLDOWN")
    PORT radio1_RSSI_ADC_D2_pin = radio1_RSSI_ADC_D2, UCF_NET_STRING=("LOC=U8", "IOSTANDARD=LVTTL", "PULLDOWN")
    PORT radio1_RSSI_ADC_D3_pin = radio1_RSSI_ADC_D3, UCF_NET_STRING=("LOC=T4", "IOSTANDARD=LVTTL", "PULLDOWN")
    PORT radio1_RSSI_ADC_D4_pin = radio1_RSSI_ADC_D4, UCF_NET_STRING=("LOC=K11", "IOSTANDARD=LVTTL", "PULLDOWN")
    PORT radio1_RSSI_ADC_D5_pin = radio1_RSSI_ADC_D5, UCF_NET_STRING=("LOC=T13", "IOSTANDARD=LVTTL", "PULLDOWN")
    PORT radio1_RSSI_ADC_D6_pin = radio1_RSSI_ADC_D6, UCF_NET_STRING=("LOC=N8", "IOSTANDARD=LVTTL", "PULLDOWN")
    PORT radio1_RSSI_ADC_D7_pin = radio1_RSSI_ADC_D7, UCF_NET_STRING=("LOC=R11", "IOSTANDARD=LVTTL", "PULLDOWN")
    PORT radio1_RSSI_ADC_D8_pin = radio1_RSSI_ADC_D8, UCF_NET_STRING=("LOC=U10", "IOSTANDARD=LVTTL", "PULLDOWN")
    PORT radio1_RSSI_ADC_D9_pin = radio1_RSSI_ADC_D9, UCF_NET_STRING=("LOC=J14", "IOSTANDARD=LVTTL", "PULLDOWN")
    PORT radio1_RSSI_ADC_HIZ_pin = radio1_RSSI_ADC_HIZ, UCF_NET_STRING=("LOC=U11", "IOSTANDARD=LVTTL")
    PORT radio1_RSSI_ADC_OTR_pin = radio1_RSSI_ADC_OTR, UCF_NET_STRING=("LOC=V9", "IOSTANDARD=LVTTL")
    PORT radio1_RSSI_ADC_SLEEP_pin = radio1_RSSI_ADC_SLEEP, UCF_NET_STRING=("LOC=T5", "IOSTANDARD=LVTTL")
    PORT radio1_RX_ADC_DCS_pin = radio1_RX_ADC_DCS, UCF_NET_STRING=("LOC=D14", "IOSTANDARD=LVTTL")
    PORT radio1_RX_ADC_DFS_pin = radio1_RX_ADC_DFS, UCF_NET_STRING=("LOC=G11", "IOSTANDARD=LVTTL")
    PORT radio1_RX_ADC_OTRA_pin = radio1_RX_ADC_OTRA, UCF_NET_STRING=("LOC=C7", "IOSTANDARD=LVTTL")
    PORT radio1_RX_ADC_OTRB_pin = radio1_RX_ADC_OTRB, UCF_NET_STRING=("LOC=C9", "IOSTANDARD=LVTTL")
    PORT radio1_RX_ADC_PWDNA_pin = radio1_RX_ADC_PWDNA, UCF_NET_STRING=("LOC=G5", "IOSTANDARD=LVTTL")
    PORT radio1_RX_ADC_PWDNB_pin = radio1_RX_ADC_PWDNB, UCF_NET_STRING=("LOC=G10", "IOSTANDARD=LVTTL")
    PORT radio1_RxEn_pin = radio1_RxEn, UCF_NET_STRING=("LOC=G13", "IOSTANDARD=LVTTL")
    PORT radio1_RxHP_pin = radio1_RxHP, UCF_NET_STRING=("LOC=F6", "IOSTANDARD=LVTTL")
    PORT radio1_SHDN_pin = radio1_SHDN, UCF_NET_STRING=("LOC=F11", "IOSTANDARD=LVTTL")
    PORT radio1_spi_clk_pin = radio1_spi_clk, UCF_NET_STRING=("LOC=P9", "IOSTANDARD=LVTTL")
    PORT radio1_spi_cs_pin = radio1_spi_cs, UCF_NET_STRING=("LOC=N3", "IOSTANDARD=LVTTL")
    PORT radio1_spi_data_pin = radio1_spi_data, UCF_NET_STRING=("LOC=K4", "IOSTANDARD=LVTTL")
    PORT radio1_TxEn_pin = radio1_TxEn, UCF_NET_STRING=("LOC=R6", "IOSTANDARD=LVTTL")

    PORT radio1_b0_pin = radio1_b0, UCF_NET_STRING=("LOC=F16", "IOSTANDARD = LVTTL") #Radio_B1
    PORT radio1_b1_pin = radio1_b1, UCF_NET_STRING=("LOC=H13", "IOSTANDARD = LVTTL") #Radio_B2
    PORT radio1_b2_pin = radio1_b2, UCF_NET_STRING=("LOC=E16", "IOSTANDARD = LVTTL") #Radio_B3
    PORT radio1_b3_pin = radio1_b3, UCF_NET_STRING=("LOC=D15", "IOSTANDARD = LVTTL") #Radio_B4
    PORT radio1_b4_pin = radio1_b4, UCF_NET_STRING=("LOC=H10", "IOSTANDARD = LVTTL") #Radio_B5
    PORT radio1_b5_pin = radio1_b5, UCF_NET_STRING=("LOC=D16", "IOSTANDARD = LVTTL") #Radio_B6
    PORT radio1_b6_pin = radio1_b6, UCF_NET_STRING=("LOC=H8", "IOSTANDARD = LVTTL") #Radio_B7

    PORT radio1_DAC_I0_pin = radio1_DAC_I0, UCF_NET_STRING=("LOC=N10", "IOSTANDARD = LVTTL")
    PORT radio1_DAC_I1_pin = radio1_DAC_I1, UCF_NET_STRING=("LOC=R4", "IOSTANDARD = LVTTL")
    PORT radio1_DAC_I2_pin = radio1_DAC_I2, UCF_NET_STRING=("LOC=R3", "IOSTANDARD = LVTTL")
    PORT radio1_DAC_I3_pin = radio1_DAC_I3, UCF_NET_STRING=("LOC=N9", "IOSTANDARD = LVTTL")
    PORT radio1_DAC_I4_pin = radio1_DAC_I4, UCF_NET_STRING=("LOC=R8", "IOSTANDARD = LVTTL")
    PORT radio1_DAC_I5_pin = radio1_DAC_I5, UCF_NET_STRING=("LOC=T3", "IOSTANDARD = LVTTL")
    PORT radio1_DAC_I6_pin = radio1_DAC_I6, UCF_NET_STRING=("LOC=T11", "IOSTANDARD = LVTTL")
    PORT radio1_DAC_I7_pin = radio1_DAC_I7, UCF_NET_STRING=("LOC=P5", "IOSTANDARD = LVTTL")
    PORT radio1_DAC_I8_pin = radio1_DAC_I8, UCF_NET_STRING=("LOC=R12", "IOSTANDARD = LVTTL")
    PORT radio1_DAC_I9_pin = radio1_DAC_I9, UCF_NET_STRING=("LOC=P12", "IOSTANDARD = LVTTL")
    PORT radio1_DAC_I10_pin = radio1_DAC_I10, UCF_NET_STRING=("LOC=T10", "IOSTANDARD = LVTTL")
    PORT radio1_DAC_I11_pin = radio1_DAC_I11, UCF_NET_STRING=("LOC=T8", "IOSTANDARD = LVTTL")
    PORT radio1_DAC_I12_pin = radio1_DAC_I12, UCF_NET_STRING=("LOC=P10", "IOSTANDARD = LVTTL")
    PORT radio1_DAC_I13_pin = radio1_DAC_I13, UCF_NET_STRING=("LOC=P11", "IOSTANDARD = LVTTL")
    PORT radio1_DAC_I14_pin = radio1_DAC_I14, UCF_NET_STRING=("LOC=N12", "IOSTANDARD = LVTTL")
    PORT radio1_DAC_I15_pin = radio1_DAC_I15, UCF_NET_STRING=("LOC=T6", "IOSTANDARD = LVTTL")

    PORT radio1_DAC_Q0_pin = radio1_DAC_Q0, UCF_NET_STRING=("LOC=N7", "IOSTANDARD = LVTTL")
    PORT radio1_DAC_Q1_pin = radio1_DAC_Q1, UCF_NET_STRING=("LOC=M11", "IOSTANDARD = LVTTL")
    PORT radio1_DAC_Q2_pin = radio1_DAC_Q2, UCF_NET_STRING=("LOC=L4", "IOSTANDARD = LVTTL")
    PORT radio1_DAC_Q3_pin = radio1_DAC_Q3, UCF_NET_STRING=("LOC=M5", "IOSTANDARD = LVTTL")
    PORT radio1_DAC_Q4_pin = radio1_DAC_Q4, UCF_NET_STRING=("LOC=L5", "IOSTANDARD = LVTTL")
    PORT radio1_DAC_Q5_pin = radio1_DAC_Q5, UCF_NET_STRING=("LOC=J10", "IOSTANDARD = LVTTL")
    PORT radio1_DAC_Q6_pin = radio1_DAC_Q6, UCF_NET_STRING=("LOC=J11", "IOSTANDARD = LVTTL")
    PORT radio1_DAC_Q7_pin = radio1_DAC_Q7, UCF_NET_STRING=("LOC=J9", "IOSTANDARD = LVTTL")
    PORT radio1_DAC_Q8_pin = radio1_DAC_Q8, UCF_NET_STRING=("LOC=M7", "IOSTANDARD = LVTTL")
    PORT radio1_DAC_Q9_pin = radio1_DAC_Q9, UCF_NET_STRING=("LOC=M6", "IOSTANDARD = LVTTL")
    PORT radio1_DAC_Q10_pin = radio1_DAC_Q10, UCF_NET_STRING=("LOC=M3", "IOSTANDARD = LVTTL")
    PORT radio1_DAC_Q11_pin = radio1_DAC_Q11, UCF_NET_STRING=("LOC=M10", "IOSTANDARD = LVTTL")
    PORT radio1_DAC_Q12_pin = radio1_DAC_Q12, UCF_NET_STRING=("LOC=K9", "IOSTANDARD = LVTTL")
    PORT radio1_DAC_Q13_pin = radio1_DAC_Q13, UCF_NET_STRING=("LOC=J12", "IOSTANDARD = LVTTL")
    PORT radio1_DAC_Q14_pin = radio1_DAC_Q14, UCF_NET_STRING=("LOC=L6", "IOSTANDARD = LVTTL")
    PORT radio1_DAC_Q15_pin = radio1_DAC_Q15, UCF_NET_STRING=("LOC=L8", "IOSTANDARD = LVTTL")
    PORT radio1_ADC_I0_pin = radio1_ADC_I0, UCF_NET_STRING=("LOC=E7", "IOSTANDARD = LVTTL")
    PORT radio1_ADC_I1_pin = radio1_ADC_I1, UCF_NET_STRING=("LOC=E8", "IOSTANDARD = LVTTL")
    PORT radio1_ADC_I2_pin = radio1_ADC_I2, UCF_NET_STRING=("LOC=D10", "IOSTANDARD = LVTTL")
    PORT radio1_ADC_I3_pin = radio1_ADC_I3, UCF_NET_STRING=("LOC=AG20", "IOSTANDARD = LVTTL")
    PORT radio1_ADC_I4_pin = radio1_ADC_I4, UCF_NET_STRING=("LOC=D11", "IOSTANDARD = LVTTL")
    PORT radio1_ADC_I5_pin = radio1_ADC_I5, UCF_NET_STRING=("LOC=C15", "IOSTANDARD = LVTTL")
    PORT radio1_ADC_I6_pin = radio1_ADC_I6, UCF_NET_STRING=("LOC=E6", "IOSTANDARD = LVTTL")
    PORT radio1_ADC_I7_pin = radio1_ADC_I7, UCF_NET_STRING=("LOC=E4", "IOSTANDARD = LVTTL")
    PORT radio1_ADC_I8_pin = radio1_ADC_I8, UCF_NET_STRING=("LOC=D4", "IOSTANDARD = LVTTL")
    PORT radio1_ADC_I9_pin = radio1_ADC_I9, UCF_NET_STRING=("LOC=C10", "IOSTANDARD = LVTTL")
    PORT radio1_ADC_I10_pin = radio1_ADC_I10, UCF_NET_STRING=("LOC=G6", "IOSTANDARD = LVTTL")
    PORT radio1_ADC_I11_pin = radio1_ADC_I11, UCF_NET_STRING=("LOC=D7", "IOSTANDARD = LVTTL")
    PORT radio1_ADC_I12_pin = radio1_ADC_I12, UCF_NET_STRING=("LOC=F4", "IOSTANDARD = LVTTL")
    PORT radio1_ADC_I13_pin = radio1_ADC_I13, UCF_NET_STRING=("LOC=E3", "IOSTANDARD = LVTTL")
    PORT radio1_ADC_Q0_pin = radio1_ADC_Q0, UCF_NET_STRING=("LOC=G7", "IOSTANDARD = LVTTL")
    PORT radio1_ADC_Q1_pin = radio1_ADC_Q1, UCF_NET_STRING=("LOC=E12", "IOSTANDARD = LVTTL")
    PORT radio1_ADC_Q2_pin = radio1_ADC_Q2, UCF_NET_STRING=("LOC=E13", "IOSTANDARD = LVTTL")
    PORT radio1_ADC_Q3_pin = radio1_ADC_Q3, UCF_NET_STRING=("LOC=D12", "IOSTANDARD = LVTTL")
    PORT radio1_ADC_Q4_pin = radio1_ADC_Q4, UCF_NET_STRING=("LOC=F9", "IOSTANDARD = LVTTL")
    PORT radio1_ADC_Q5_pin = radio1_ADC_Q5, UCF_NET_STRING=("LOC=H7", "IOSTANDARD = LVTTL")
    PORT radio1_ADC_Q6_pin = radio1_ADC_Q6, UCF_NET_STRING=("LOC=G8", "IOSTANDARD = LVTTL")
    PORT radio1_ADC_Q7_pin = radio1_ADC_Q7, UCF_NET_STRING=("LOC=E9", "IOSTANDARD = LVTTL")
    PORT radio1_ADC_Q8_pin = radio1_ADC_Q8, UCF_NET_STRING=("LOC=C12", "IOSTANDARD = LVTTL")
    PORT radio1_ADC_Q9_pin = radio1_ADC_Q9, UCF_NET_STRING=("LOC=F5", "IOSTANDARD = LVTTL")
    PORT radio1_ADC_Q10_pin = radio1_ADC_Q10, UCF_NET_STRING=("LOC=F8", "IOSTANDARD = LVTTL")
    PORT radio1_ADC_Q11_pin = radio1_ADC_Q11, UCF_NET_STRING=("LOC=D6", "IOSTANDARD = LVTTL")
    PORT radio1_ADC_Q12_pin = radio1_ADC_Q12, UCF_NET_STRING=("LOC=C13", "IOSTANDARD = LVTTL")
    PORT radio1_ADC_Q13_pin = radio1_ADC_Q13, UCF_NET_STRING=("LOC=D9", "IOSTANDARD = LVTTL")

#Radio Bridge for Slot #2
#   PORT radio2_conv_clk_p = radio2_conv_clk_p, UCF_NET_STRING=("LOC=Y14", "IOSTANDARD=LVDCI_33")
    PORT radio2_conv_clk_p = radio2_conv_clk_p, UCF_NET_STRING=("LOC=AD5", "IOSTANDARD=LVTTL")
    PORT radio2_EEPROM_IO = radio2_EEPROM_IO, UCF_NET_STRING=("LOC=AE6", "IOSTANDARD=LVTTL", "SLEW = SLOW", "DRIVE = 8")
    PORT dac2_spi_clk_pin = dac2_spi_clk, UCF_NET_STRING=("LOC=AK7", "IOSTANDARD=LVTTL")
    PORT dac2_spi_cs_pin = dac2_spi_cs, UCF_NET_STRING=("LOC=AK8", "IOSTANDARD=LVTTL")
    PORT dac2_spi_data_pin = dac2_spi_data, UCF_NET_STRING=("LOC=AC9", "IOSTANDARD=LVTTL")
    PORT radio2_24PA_pin = radio2_24PA, UCF_NET_STRING=("LOC=W7", "IOSTANDARD=LVTTL")
    PORT radio2_5PA_pin = radio2_5PA, UCF_NET_STRING=("LOC=AC8", "IOSTANDARD=LVTTL")
    PORT radio2_ANTSW0_pin = radio2_ANTSW0, UCF_NET_STRING=("LOC=U3", "IOSTANDARD=LVTTL")
    PORT radio2_ANTSW1_pin = radio2_ANTSW1, UCF_NET_STRING=("LOC=Y7", "IOSTANDARD=LVTTL")
    PORT radio2_dac2_PLL_LOCK_pin = radio2_dac2_PLL_LOCK, UCF_NET_STRING=("LOC=AL3", "IOSTANDARD=LVTTL")
    PORT radio2_dac2_RESET_pin = radio2_dac2_RESET, UCF_NET_STRING=("LOC=AC10", "IOSTANDARD=LVTTL")
    PORT radio2_DIPSW0_pin = radio2_DIPSW0, UCF_NET_STRING=("LOC=Y13", "IOSTANDARD=LVTTL")
    PORT radio2_DIPSW1_pin = radio2_DIPSW1, UCF_NET_STRING=("LOC=AH3", "IOSTANDARD=LVTTL")
    PORT radio2_DIPSW2_pin = radio2_DIPSW2, UCF_NET_STRING=("LOC=W15", "IOSTANDARD=LVTTL")
    PORT radio2_DIPSW3_pin = radio2_DIPSW3, UCF_NET_STRING=("LOC=AA13", "IOSTANDARD=LVTTL")
    PORT radio2_LD_pin = radio2_LD, UCF_NET_STRING=("LOC=AD9", "IOSTANDARD=LVTTL")
    PORT radio2_LED0_pin = radio2_LED0, UCF_NET_STRING=("LOC=AA8", "IOSTANDARD=LVTTL")
    PORT radio2_LED1_pin = radio2_LED1, UCF_NET_STRING=("LOC=W10", "IOSTANDARD=LVTTL")
    PORT radio2_LED2_pin = radio2_LED2, UCF_NET_STRING=("LOC=V4", "IOSTANDARD=LVTTL")
    PORT radio2_rssi_ADC_clk_pin = radio2_rssi_ADC_clk, UCF_NET_STRING=("LOC=AF5", "IOSTANDARD=LVTTL")
    PORT radio2_RSSI_ADC_CLAMP_pin = radio2_RSSI_ADC_CLAMP, UCF_NET_STRING=("LOC=AB13", "IOSTANDARD=LVTTL")
    PORT radio2_RSSI_ADC_D0_pin = radio2_RSSI_ADC_D0, UCF_NET_STRING=("LOC=AD10", "IOSTANDARD=LVTTL", "PULLDOWN")
    PORT radio2_RSSI_ADC_D1_pin = radio2_RSSI_ADC_D1, UCF_NET_STRING=("LOC=AD11", "IOSTANDARD=LVTTL", "PULLDOWN")
    PORT radio2_RSSI_ADC_D2_pin = radio2_RSSI_ADC_D2, UCF_NET_STRING=("LOC=AE3", "IOSTANDARD=LVTTL", "PULLDOWN")
    PORT radio2_RSSI_ADC_D3_pin = radio2_RSSI_ADC_D3, UCF_NET_STRING=("LOC=AC13", "IOSTANDARD=LVTTL", "PULLDOWN")
    PORT radio2_RSSI_ADC_D4_pin = radio2_RSSI_ADC_D4, UCF_NET_STRING=("LOC=AF3", "IOSTANDARD=LVTTL", "PULLDOWN")
    PORT radio2_RSSI_ADC_D5_pin = radio2_RSSI_ADC_D5, UCF_NET_STRING=("LOC=AM3", "IOSTANDARD=LVTTL", "PULLDOWN")
    PORT radio2_RSSI_ADC_D6_pin = radio2_RSSI_ADC_D6, UCF_NET_STRING=("LOC=AG10", "IOSTANDARD=LVTTL", "PULLDOWN")
    PORT radio2_RSSI_ADC_D7_pin = radio2_RSSI_ADC_D7, UCF_NET_STRING=("LOC=AF10", "IOSTANDARD=LVTTL", "PULLDOWN")
    PORT radio2_RSSI_ADC_D8_pin = radio2_RSSI_ADC_D8, UCF_NET_STRING=("LOC=AL5", "IOSTANDARD=LVTTL", "PULLDOWN")
    PORT radio2_RSSI_ADC_D9_pin = radio2_RSSI_ADC_D9, UCF_NET_STRING=("LOC=AM8", "IOSTANDARD=LVTTL", "PULLDOWN")
    PORT radio2_RSSI_ADC_HIZ_pin = radio2_RSSI_ADC_HIZ, UCF_NET_STRING=("LOC=AK3", "IOSTANDARD=LVTTL")
    PORT radio2_RSSI_ADC_OTR_pin = radio2_RSSI_ADC_OTR, UCF_NET_STRING=("LOC=AC12", "IOSTANDARD=LVTTL")
    PORT radio2_RSSI_ADC_SLEEP_pin = radio2_RSSI_ADC_SLEEP, UCF_NET_STRING=("LOC=AH9", "IOSTANDARD=LVTTL")
    PORT radio2_RX_ADC_DCS_pin = radio2_RX_ADC_DCS, UCF_NET_STRING=("LOC=AA5", "IOSTANDARD=LVTTL")
    PORT radio2_RX_ADC_DFS_pin = radio2_RX_ADC_DFS, UCF_NET_STRING=("LOC=AF4", "IOSTANDARD=LVTTL")
    PORT radio2_RX_ADC_OTRA_pin = radio2_RX_ADC_OTRA, UCF_NET_STRING=("LOC=V13", "IOSTANDARD=LVTTL")
    PORT radio2_RX_ADC_OTRB_pin = radio2_RX_ADC_OTRB, UCF_NET_STRING=("LOC=Y9", "IOSTANDARD=LVTTL")
    PORT radio2_RX_ADC_PWDNA_pin = radio2_RX_ADC_PWDNA, UCF_NET_STRING=("LOC=Y8", "IOSTANDARD=LVTTL")
    PORT radio2_RX_ADC_PWDNB_pin = radio2_RX_ADC_PWDNB, UCF_NET_STRING=("LOC=AA14", "IOSTANDARD=LVTTL")
    PORT radio2_RxEn_pin = radio2_RxEn, UCF_NET_STRING=("LOC=AB10", "IOSTANDARD=LVTTL")
    PORT radio2_RxHP_pin = radio2_RxHP, UCF_NET_STRING=("LOC=AC4", "IOSTANDARD=LVTTL")
    PORT radio2_SHDN_pin = radio2_SHDN, UCF_NET_STRING=("LOC=AB3", "IOSTANDARD=LVTTL")
    PORT radio2_spi_clk_pin = radio2_spi_clk, UCF_NET_STRING=("LOC=AB12", "IOSTANDARD=LVTTL")
    PORT radio2_spi_cs_pin = radio2_spi_cs, UCF_NET_STRING=("LOC=AE8", "IOSTANDARD=LVTTL")
    PORT radio2_spi_data_pin = radio2_spi_data, UCF_NET_STRING=("LOC=AG3", "IOSTANDARD=LVTTL")
    PORT radio2_TxEn_pin = radio2_TxEn, UCF_NET_STRING=("LOC=W16", "IOSTANDARD=LVTTL")

    PORT radio2_b0_pin = radio2_b0, UCF_NET_STRING=("LOC=AA4", "IOSTANDARD = LVTTL") #Radio_B1
    PORT radio2_b1_pin = radio2_b1, UCF_NET_STRING=("LOC=AH5", "IOSTANDARD = LVTTL") #Radio_B2
    PORT radio2_b2_pin = radio2_b2, UCF_NET_STRING=("LOC=Y4", "IOSTANDARD = LVTTL") #Radio_B3
    PORT radio2_b3_pin = radio2_b3, UCF_NET_STRING=("LOC=V17", "IOSTANDARD = LVTTL") #Radio_B4
    PORT radio2_b4_pin = radio2_b4, UCF_NET_STRING=("LOC=AC3", "IOSTANDARD = LVTTL") #Radio_B5
    PORT radio2_b5_pin = radio2_b5, UCF_NET_STRING=("LOC=Y6", "IOSTANDARD = LVTTL") #Radio_B6
    PORT radio2_b6_pin = radio2_b6, UCF_NET_STRING=("LOC=AH4", "IOSTANDARD = LVTTL") #Radio_B7

    PORT radio2_DAC_I0_pin = radio2_DAC_I0, UCF_NET_STRING=("LOC=AP4", "IOSTANDARD = LVTTL")
    PORT radio2_DAC_I1_pin = radio2_DAC_I1, UCF_NET_STRING=("LOC=AR3", "IOSTANDARD = LVTTL")
    PORT radio2_DAC_I2_pin = radio2_DAC_I2, UCF_NET_STRING=("LOC=AT4", "IOSTANDARD = LVTTL")
    PORT radio2_DAC_I3_pin = radio2_DAC_I3, UCF_NET_STRING=("LOC=AR4", "IOSTANDARD = LVTTL")
    PORT radio2_DAC_I4_pin = radio2_DAC_I4, UCF_NET_STRING=("LOC=AT5", "IOSTANDARD = LVTTL")
    PORT radio2_DAC_I5_pin = radio2_DAC_I5, UCF_NET_STRING=("LOC=AN3", "IOSTANDARD = LVTTL")
    PORT radio2_DAC_I6_pin = radio2_DAC_I6, UCF_NET_STRING=("LOC=AT3", "IOSTANDARD = LVTTL")
    PORT radio2_DAC_I7_pin = radio2_DAC_I7, UCF_NET_STRING=("LOC=AU5", "IOSTANDARD = LVTTL")
    PORT radio2_DAC_I8_pin = radio2_DAC_I8, UCF_NET_STRING=("LOC=AM7", "IOSTANDARD = LVTTL")
    PORT radio2_DAC_I9_pin = radio2_DAC_I9, UCF_NET_STRING=("LOC=AU6", "IOSTANDARD = LVTTL")
    PORT radio2_DAC_I10_pin = radio2_DAC_I10, UCF_NET_STRING=("LOC=AP5", "IOSTANDARD = LVTTL")
    PORT radio2_DAC_I11_pin = radio2_DAC_I11, UCF_NET_STRING=("LOC=AN5", "IOSTANDARD = LVTTL")
    PORT radio2_DAC_I12_pin = radio2_DAC_I12, UCF_NET_STRING=("LOC=AT6", "IOSTANDARD = LVTTL")
    PORT radio2_DAC_I13_pin = radio2_DAC_I13, UCF_NET_STRING=("LOC=AM6", "IOSTANDARD = LVTTL")
    PORT radio2_DAC_I14_pin = radio2_DAC_I14, UCF_NET_STRING=("LOC=AL6", "IOSTANDARD = LVTTL")
    PORT radio2_DAC_I15_pin = radio2_DAC_I15, UCF_NET_STRING=("LOC=AL8", "IOSTANDARD = LVTTL")

    PORT radio2_DAC_Q0_pin = radio2_DAC_Q0, UCF_NET_STRING=("LOC=AF8", "IOSTANDARD = LVTTL")
    PORT radio2_DAC_Q1_pin = radio2_DAC_Q1, UCF_NET_STRING=("LOC=AF9", "IOSTANDARD = LVTTL")
    PORT radio2_DAC_Q2_pin = radio2_DAC_Q2, UCF_NET_STRING=("LOC=AH8", "IOSTANDARD = LVTTL")
    PORT radio2_DAC_Q3_pin = radio2_DAC_Q3, UCF_NET_STRING=("LOC=AG7", "IOSTANDARD = LVTTL")
    PORT radio2_DAC_Q4_pin = radio2_DAC_Q4, UCF_NET_STRING=("LOC=AJ6", "IOSTANDARD = LVTTL")
    PORT radio2_DAC_Q5_pin = radio2_DAC_Q5, UCF_NET_STRING=("LOC=AN4", "IOSTANDARD = LVTTL")
    PORT radio2_DAC_Q6_pin = radio2_DAC_Q6, UCF_NET_STRING=("LOC=AG8", "IOSTANDARD = LVTTL")
    PORT radio2_DAC_Q7_pin = radio2_DAC_Q7, UCF_NET_STRING=("LOC=AM5", "IOSTANDARD = LVTTL")
    PORT radio2_DAC_Q8_pin = radio2_DAC_Q8, UCF_NET_STRING=("LOC=AJ5", "IOSTANDARD = LVTTL")
    PORT radio2_DAC_Q9_pin = radio2_DAC_Q9, UCF_NET_STRING=("LOC=AK6", "IOSTANDARD = LVTTL")
    PORT radio2_DAC_Q10_pin = radio2_DAC_Q10, UCF_NET_STRING=("LOC=AH7", "IOSTANDARD = LVTTL")
    PORT radio2_DAC_Q11_pin = radio2_DAC_Q11, UCF_NET_STRING=("LOC=AJ4", "IOSTANDARD = LVTTL")
    PORT radio2_DAC_Q12_pin = radio2_DAC_Q12, UCF_NET_STRING=("LOC=AL4", "IOSTANDARD = LVTTL")
    PORT radio2_DAC_Q13_pin = radio2_DAC_Q13, UCF_NET_STRING=("LOC=AB15", "IOSTANDARD = LVTTL")
    PORT radio2_DAC_Q14_pin = radio2_DAC_Q14, UCF_NET_STRING=("LOC=AC14", "IOSTANDARD = LVTTL")
    PORT radio2_DAC_Q15_pin = radio2_DAC_Q15, UCF_NET_STRING=("LOC=AK4", "IOSTANDARD = LVTTL")

    PORT radio2_ADC_I0_pin = radio2_ADC_I0, UCF_NET_STRING=("LOC=V14", "IOSTANDARD = LVTTL")
    PORT radio2_ADC_I1_pin = radio2_ADC_I1, UCF_NET_STRING=("LOC=U15", "IOSTANDARD = LVTTL")
    PORT radio2_ADC_I2_pin = radio2_ADC_I2, UCF_NET_STRING=("LOC=W6", "IOSTANDARD = LVTTL")
    PORT radio2_ADC_I3_pin = radio2_ADC_I3, UCF_NET_STRING=("LOC=AG18", "IOSTANDARD = LVTTL")
    PORT radio2_ADC_I4_pin = radio2_ADC_I4, UCF_NET_STRING=("LOC=V15", "IOSTANDARD = LVTTL")
    PORT radio2_ADC_I5_pin = radio2_ADC_I5, UCF_NET_STRING=("LOC=V5", "IOSTANDARD = LVTTL")
    PORT radio2_ADC_I6_pin = radio2_ADC_I6, UCF_NET_STRING=("LOC=AA10", "IOSTANDARD = LVTTL")
    PORT radio2_ADC_I7_pin = radio2_ADC_I7, UCF_NET_STRING=("LOC=Y11", "IOSTANDARD = LVTTL")
    PORT radio2_ADC_I8_pin = radio2_ADC_I8, UCF_NET_STRING=("LOC=AA9", "IOSTANDARD = LVTTL")
    PORT radio2_ADC_I9_pin = radio2_ADC_I9, UCF_NET_STRING=("LOC=V7", "IOSTANDARD = LVTTL")
    PORT radio2_ADC_I10_pin = radio2_ADC_I10, UCF_NET_STRING=("LOC=U6", "IOSTANDARD = LVTTL")
    PORT radio2_ADC_I11_pin = radio2_ADC_I11, UCF_NET_STRING=("LOC=AB11", "IOSTANDARD = LVTTL")
    PORT radio2_ADC_I12_pin = radio2_ADC_I12, UCF_NET_STRING=("LOC=W4", "IOSTANDARD = LVTTL")
    PORT radio2_ADC_I13_pin = radio2_ADC_I13, UCF_NET_STRING=("LOC=V12", "IOSTANDARD = LVTTL")

    PORT radio2_ADC_Q0_pin = radio2_ADC_Q0, UCF_NET_STRING=("LOC=AB7", "IOSTANDARD = LVTTL")
    PORT radio2_ADC_Q1_pin = radio2_ADC_Q1, UCF_NET_STRING=("LOC=AE7", "IOSTANDARD = LVTTL")
    PORT radio2_ADC_Q2_pin = radio2_ADC_Q2, UCF_NET_STRING=("LOC=AC7", "IOSTANDARD = LVTTL")
    PORT radio2_ADC_Q3_pin = radio2_ADC_Q3, UCF_NET_STRING=("LOC=AC5", "IOSTANDARD = LVTTL")
    PORT radio2_ADC_Q4_pin = radio2_ADC_Q4, UCF_NET_STRING=("LOC=AE4", "IOSTANDARD = LVTTL")
    PORT radio2_ADC_Q5_pin = radio2_ADC_Q5, UCF_NET_STRING=("LOC=AD4", "IOSTANDARD = LVTTL")
    PORT radio2_ADC_Q6_pin = radio2_ADC_Q6, UCF_NET_STRING=("LOC=AD7", "IOSTANDARD = LVTTL")
    PORT radio2_ADC_Q7_pin = radio2_ADC_Q7, UCF_NET_STRING=("LOC=AD6", "IOSTANDARD = LVTTL")
    PORT radio2_ADC_Q8_pin = radio2_ADC_Q8, UCF_NET_STRING=("LOC=W14", "IOSTANDARD = LVTTL")
    PORT radio2_ADC_Q9_pin = radio2_ADC_Q9, UCF_NET_STRING=("LOC=U5", "IOSTANDARD = LVTTL")
    PORT radio2_ADC_Q10_pin = radio2_ADC_Q10, UCF_NET_STRING=("LOC=W5", "IOSTANDARD = LVTTL")
    PORT radio2_ADC_Q11_pin = radio2_ADC_Q11, UCF_NET_STRING=("LOC=AA11", "IOSTANDARD = LVTTL")
    PORT radio2_ADC_Q12_pin = radio2_ADC_Q12, UCF_NET_STRING=("LOC=W9", "IOSTANDARD = LVTTL")
    PORT radio2_ADC_Q13_pin = radio2_ADC_Q13, UCF_NET_STRING=("LOC=Y12", "IOSTANDARD = LVTTL")

##Radio Bridge for Slot #3
#   PORT radio3_conv_clk_p = radio3_conv_clk_p, UCF_NET_STRING=("LOC=AD30", "IOSTANDARD=LVDCI_33")
    PORT radio3_conv_clk_p = radio3_conv_clk_p, UCF_NET_STRING=("LOC=AC29", "IOSTANDARD=LVTTL")
    PORT radio3_EEPROM_IO = radio3_EEPROM_IO, UCF_NET_STRING=("LOC=AE32", "IOSTANDARD=LVTTL", "SLEW = SLOW", "DRIVE = 8")
    PORT dac3_spi_clk_pin = dac3_spi_clk, UCF_NET_STRING=("LOC=AA36", "IOSTANDARD=LVTTL")
    PORT dac3_spi_cs_pin = dac3_spi_cs, UCF_NET_STRING=("LOC=W35", "IOSTANDARD=LVTTL")
    PORT dac3_spi_data_pin = dac3_spi_data, UCF_NET_STRING=("LOC=T36", "IOSTANDARD=LVTTL")
    PORT radio3_24PA_pin = radio3_24PA, UCF_NET_STRING=("LOC=AM36", "IOSTANDARD=LVTTL")
    PORT radio3_5PA_pin = radio3_5PA, UCF_NET_STRING=("LOC=AN35", "IOSTANDARD=LVTTL")
    PORT radio3_ANTSW0_pin = radio3_ANTSW0, UCF_NET_STRING=("LOC=AN37", "IOSTANDARD=LVTTL")
    PORT radio3_ANTSW1_pin = radio3_ANTSW1, UCF_NET_STRING=("LOC=AJ37", "IOSTANDARD=LVTTL")
    PORT radio3_dac3_PLL_LOCK_pin = radio3_dac3_PLL_LOCK, UCF_NET_STRING=("LOC=AG35", "IOSTANDARD=LVTTL")
    PORT radio3_dac3_RESET_pin = radio3_dac3_RESET, UCF_NET_STRING=("LOC=AE36", "IOSTANDARD=LVTTL")
    PORT radio3_DIPSW0_pin = radio3_DIPSW0, UCF_NET_STRING=("LOC=AG36", "IOSTANDARD=LVTTL")
    PORT radio3_DIPSW1_pin = radio3_DIPSW1, UCF_NET_STRING=("LOC=AG37", "IOSTANDARD=LVTTL")
    PORT radio3_DIPSW2_pin = radio3_DIPSW2, UCF_NET_STRING=("LOC=T34", "IOSTANDARD=LVTTL")
    PORT radio3_DIPSW3_pin = radio3_DIPSW3, UCF_NET_STRING=("LOC=AH37", "IOSTANDARD=LVTTL")
    PORT radio3_LD_pin = radio3_LD, UCF_NET_STRING=("LOC=AB37", "IOSTANDARD=LVTTL")
    PORT radio3_LED0_pin = radio3_LED0, UCF_NET_STRING=("LOC=AL35", "IOSTANDARD=LVTTL")
    PORT radio3_LED1_pin = radio3_LED1, UCF_NET_STRING=("LOC=AE33", "IOSTANDARD=LVTTL")
    PORT radio3_LED2_pin = radio3_LED2, UCF_NET_STRING=("LOC=AM35", "IOSTANDARD=LVTTL")
    PORT radio3_rssi_ADC_clk_pin = radio3_rssi_ADC_clk, UCF_NET_STRING=("LOC=AD32", "IOSTANDARD=LVTTL")
    PORT radio3_RSSI_ADC_CLAMP_pin = radio3_RSSI_ADC_CLAMP, UCF_NET_STRING=("LOC=K36", "IOSTANDARD=LVTTL")
    PORT radio3_RSSI_ADC_D0_pin = radio3_RSSI_ADC_D0, UCF_NET_STRING=("LOC=P35", "IOSTANDARD=LVTTL", "PULLDOWN")
    PORT radio3_RSSI_ADC_D1_pin = radio3_RSSI_ADC_D1, UCF_NET_STRING=("LOC=AB28", "IOSTANDARD=LVTTL", "PULLDOWN")
    PORT radio3_RSSI_ADC_D2_pin = radio3_RSSI_ADC_D2, UCF_NET_STRING=("LOC=M36", "IOSTANDARD=LVTTL", "PULLDOWN")
    PORT radio3_RSSI_ADC_D3_pin = radio3_RSSI_ADC_D3, UCF_NET_STRING=("LOC=AF35", "IOSTANDARD=LVTTL", "PULLDOWN")
    PORT radio3_RSSI_ADC_D4_pin = radio3_RSSI_ADC_D4, UCF_NET_STRING=("LOC=L36", "IOSTANDARD=LVTTL", "PULLDOWN")
    PORT radio3_RSSI_ADC_D5_pin = radio3_RSSI_ADC_D5, UCF_NET_STRING=("LOC=M37", "IOSTANDARD=LVTTL", "PULLDOWN")
    PORT radio3_RSSI_ADC_D6_pin = radio3_RSSI_ADC_D6, UCF_NET_STRING=("LOC=R37", "IOSTANDARD=LVTTL", "PULLDOWN")
    PORT radio3_RSSI_ADC_D7_pin = radio3_RSSI_ADC_D7, UCF_NET_STRING=("LOC=P36", "IOSTANDARD=LVTTL", "PULLDOWN")
    PORT radio3_RSSI_ADC_D8_pin = radio3_RSSI_ADC_D8, UCF_NET_STRING=("LOC=AE34", "IOSTANDARD=LVTTL", "PULLDOWN")
    PORT radio3_RSSI_ADC_D9_pin = radio3_RSSI_ADC_D9, UCF_NET_STRING=("LOC=Y31", "IOSTANDARD=LVTTL", "PULLDOWN")
    PORT radio3_RSSI_ADC_HIZ_pin = radio3_RSSI_ADC_HIZ, UCF_NET_STRING=("LOC=W29", "IOSTANDARD=LVTTL")
    PORT radio3_RSSI_ADC_OTR_pin = radio3_RSSI_ADC_OTR, UCF_NET_STRING=("LOC=U36", "IOSTANDARD=LVTTL")
    PORT radio3_RSSI_ADC_SLEEP_pin = radio3_RSSI_ADC_SLEEP, UCF_NET_STRING=("LOC=K37", "IOSTANDARD=LVTTL")
    PORT radio3_RX_ADC_DCS_pin = radio3_RX_ADC_DCS, UCF_NET_STRING=("LOC=AF28", "IOSTANDARD=LVTTL")
    PORT radio3_RX_ADC_DFS_pin = radio3_RX_ADC_DFS, UCF_NET_STRING=("LOC=AD34", "IOSTANDARD=LVTTL")
    PORT radio3_RX_ADC_OTRA_pin = radio3_RX_ADC_OTRA, UCF_NET_STRING=("LOC=AM37", "IOSTANDARD=LVTTL")
    PORT radio3_RX_ADC_OTRB_pin = radio3_RX_ADC_OTRB, UCF_NET_STRING=("LOC=AL36", "IOSTANDARD=LVTTL")
    PORT radio3_RX_ADC_PWDNA_pin = radio3_RX_ADC_PWDNA, UCF_NET_STRING=("LOC=AK36", "IOSTANDARD=LVTTL")
    PORT radio3_RX_ADC_PWDNB_pin = radio3_RX_ADC_PWDNB, UCF_NET_STRING=("LOC=AE28", "IOSTANDARD=LVTTL")
    PORT radio3_RxEn_pin = radio3_RxEn, UCF_NET_STRING=("LOC=Y26", "IOSTANDARD=LVTTL")
    PORT radio3_RxHP_pin = radio3_RxHP, UCF_NET_STRING=("LOC=AC25", "IOSTANDARD=LVTTL")
    PORT radio3_SHDN_pin = radio3_SHDN, UCF_NET_STRING=("LOC=AD27", "IOSTANDARD=LVTTL")
    PORT radio3_spi_clk_pin = radio3_spi_clk, UCF_NET_STRING=("LOC=AC37", "IOSTANDARD=LVTTL")
    PORT radio3_spi_cs_pin = radio3_spi_cs, UCF_NET_STRING=("LOC=AF36", "IOSTANDARD=LVTTL")
    PORT radio3_spi_data_pin = radio3_spi_data, UCF_NET_STRING=("LOC=AD37", "IOSTANDARD=LVTTL")
    PORT radio3_TxEn_pin = radio3_TxEn, UCF_NET_STRING=("LOC=AE37", "IOSTANDARD=LVTTL")

    PORT radio3_b0_pin = radio3_b0, UCF_NET_STRING=("LOC=AG28", "IOSTANDARD = LVTTL") #Radio_B1
    PORT radio3_b1_pin = radio3_b1, UCF_NET_STRING=("LOC=AC24", "IOSTANDARD = LVTTL") #Radio_B2
    PORT radio3_b2_pin = radio3_b2, UCF_NET_STRING=("LOC=AD31", "IOSTANDARD = LVTTL") #Radio_B3
    PORT radio3_b3_pin = radio3_b3, UCF_NET_STRING=("LOC=AA24", "IOSTANDARD = LVTTL") #Radio_B4
    PORT radio3_b4_pin = radio3_b4, UCF_NET_STRING=("LOC=AG30", "IOSTANDARD = LVTTL") #Radio_B5
    PORT radio3_b5_pin = radio3_b5, UCF_NET_STRING=("LOC=AB23", "IOSTANDARD = LVTTL") #Radio_B6
    PORT radio3_b6_pin = radio3_b6, UCF_NET_STRING=("LOC=AH29", "IOSTANDARD = LVTTL") #Radio_B7

    PORT radio3_DAC_I0_pin = radio3_DAC_I0, UCF_NET_STRING=("LOC=AB35", "IOSTANDARD = LVTTL")
    PORT radio3_DAC_I1_pin = radio3_DAC_I1, UCF_NET_STRING=("LOC=AC34", "IOSTANDARD = LVTTL")
    PORT radio3_DAC_I2_pin = radio3_DAC_I2, UCF_NET_STRING=("LOC=AA30", "IOSTANDARD = LVTTL")
    PORT radio3_DAC_I3_pin = radio3_DAC_I3, UCF_NET_STRING=("LOC=Y27", "IOSTANDARD = LVTTL")
    PORT radio3_DAC_I4_pin = radio3_DAC_I4, UCF_NET_STRING=("LOC=AB31", "IOSTANDARD = LVTTL")
    PORT radio3_DAC_I5_pin = radio3_DAC_I5, UCF_NET_STRING=("LOC=N37", "IOSTANDARD = LVTTL")
    PORT radio3_DAC_I6_pin = radio3_DAC_I6, UCF_NET_STRING=("LOC=AA31", "IOSTANDARD = LVTTL")
    PORT radio3_DAC_I7_pin = radio3_DAC_I7, UCF_NET_STRING=("LOC=R34", "IOSTANDARD = LVTTL")
    PORT radio3_DAC_I8_pin = radio3_DAC_I8, UCF_NET_STRING=("LOC=AC32", "IOSTANDARD = LVTTL")
    PORT radio3_DAC_I9_pin = radio3_DAC_I9, UCF_NET_STRING=("LOC=Y32", "IOSTANDARD = LVTTL")
    PORT radio3_DAC_I10_pin = radio3_DAC_I10, UCF_NET_STRING=("LOC=AD35", "IOSTANDARD = LVTTL")
    PORT radio3_DAC_I11_pin = radio3_DAC_I11, UCF_NET_STRING=("LOC=Y34", "IOSTANDARD = LVTTL")
    PORT radio3_DAC_I12_pin = radio3_DAC_I12, UCF_NET_STRING=("LOC=P37", "IOSTANDARD = LVTTL")
    PORT radio3_DAC_I13_pin = radio3_DAC_I13, UCF_NET_STRING=("LOC=R36", "IOSTANDARD = LVTTL")
    PORT radio3_DAC_I14_pin = radio3_DAC_I14, UCF_NET_STRING=("LOC=T35", "IOSTANDARD = LVTTL")
    PORT radio3_DAC_I15_pin = radio3_DAC_I15, UCF_NET_STRING=("LOC=Y33", "IOSTANDARD = LVTTL")

    PORT radio3_DAC_Q0_pin = radio3_DAC_Q0, UCF_NET_STRING=("LOC=V34", "IOSTANDARD = LVTTL")
    PORT radio3_DAC_Q1_pin = radio3_DAC_Q1, UCF_NET_STRING=("LOC=AC35", "IOSTANDARD = LVTTL")
    PORT radio3_DAC_Q2_pin = radio3_DAC_Q2, UCF_NET_STRING=("LOC=V33", "IOSTANDARD = LVTTL")
    PORT radio3_DAC_Q3_pin = radio3_DAC_Q3, UCF_NET_STRING=("LOC=Y36", "IOSTANDARD = LVTTL")
    PORT radio3_DAC_Q4_pin = radio3_DAC_Q4, UCF_NET_STRING=("LOC=U37", "IOSTANDARD = LVTTL")
    PORT radio3_DAC_Q5_pin = radio3_DAC_Q5, UCF_NET_STRING=("LOC=AB36", "IOSTANDARD = LVTTL")
    PORT radio3_DAC_Q6_pin = radio3_DAC_Q6, UCF_NET_STRING=("LOC=U35", "IOSTANDARD = LVTTL")
    PORT radio3_DAC_Q7_pin = radio3_DAC_Q7, UCF_NET_STRING=("LOC=Y37", "IOSTANDARD = LVTTL")
    PORT radio3_DAC_Q8_pin = radio3_DAC_Q8, UCF_NET_STRING=("LOC=W37", "IOSTANDARD = LVTTL")
    PORT radio3_DAC_Q9_pin = radio3_DAC_Q9, UCF_NET_STRING=("LOC=AA34", "IOSTANDARD = LVTTL")
    PORT radio3_DAC_Q10_pin = radio3_DAC_Q10, UCF_NET_STRING=("LOC=W36", "IOSTANDARD = LVTTL")
    PORT radio3_DAC_Q11_pin = radio3_DAC_Q11, UCF_NET_STRING=("LOC=AA35", "IOSTANDARD = LVTTL")
    PORT radio3_DAC_Q12_pin = radio3_DAC_Q12, UCF_NET_STRING=("LOC=W30", "IOSTANDARD = LVTTL")
    PORT radio3_DAC_Q13_pin = radio3_DAC_Q13, UCF_NET_STRING=("LOC=W32", "IOSTANDARD = LVTTL")
    PORT radio3_DAC_Q14_pin = radio3_DAC_Q14, UCF_NET_STRING=("LOC=V35", "IOSTANDARD = LVTTL")
    PORT radio3_DAC_Q15_pin = radio3_DAC_Q15, UCF_NET_STRING=("LOC=W34", "IOSTANDARD = LVTTL")
    PORT radio3_ADC_I0_pin = radio3_ADC_I0, UCF_NET_STRING=("LOC=AM33", "IOSTANDARD = LVTTL")
    PORT radio3_ADC_I1_pin = radio3_ADC_I1, UCF_NET_STRING=("LOC=AF33", "IOSTANDARD = LVTTL")
    PORT radio3_ADC_I2_pin = radio3_ADC_I2, UCF_NET_STRING=("LOC=AG31", "IOSTANDARD = LVTTL")
    PORT radio3_ADC_I3_pin = radio3_ADC_I3, UCF_NET_STRING=("LOC=AM22", "IOSTANDARD = LVTTL")
    PORT radio3_ADC_I4_pin = radio3_ADC_I4, UCF_NET_STRING=("LOC=AH30", "IOSTANDARD = LVTTL")
    PORT radio3_ADC_I5_pin = radio3_ADC_I5, UCF_NET_STRING=("LOC=AG32", "IOSTANDARD = LVTTL")
    PORT radio3_ADC_I6_pin = radio3_ADC_I6, UCF_NET_STRING=("LOC=AF31", "IOSTANDARD = LVTTL")
    PORT radio3_ADC_I7_pin = radio3_ADC_I7, UCF_NET_STRING=("LOC=AH34", "IOSTANDARD = LVTTL")
    PORT radio3_ADC_I8_pin = radio3_ADC_I8, UCF_NET_STRING=("LOC=AK32", "IOSTANDARD = LVTTL")
    PORT radio3_ADC_I9_pin = radio3_ADC_I9, UCF_NET_STRING=("LOC=AF34", "IOSTANDARD = LVTTL")
    PORT radio3_ADC_I10_pin = radio3_ADC_I10, UCF_NET_STRING=("LOC=AN34", "IOSTANDARD = LVTTL")
    PORT radio3_ADC_I11_pin = radio3_ADC_I11, UCF_NET_STRING=("LOC=AJ36", "IOSTANDARD = LVTTL")
    PORT radio3_ADC_I12_pin = radio3_ADC_I12, UCF_NET_STRING=("LOC=AN33", "IOSTANDARD = LVTTL")
    PORT radio3_ADC_I13_pin = radio3_ADC_I13, UCF_NET_STRING=("LOC=AH35", "IOSTANDARD = LVTTL")
    PORT radio3_ADC_Q0_pin = radio3_ADC_Q0, UCF_NET_STRING=("LOC=AA26", "IOSTANDARD = LVTTL")
    PORT radio3_ADC_Q1_pin = radio3_ADC_Q1, UCF_NET_STRING=("LOC=AE29", "IOSTANDARD = LVTTL")
    PORT radio3_ADC_Q2_pin = radio3_ADC_Q2, UCF_NET_STRING=("LOC=AA29", "IOSTANDARD = LVTTL")
    PORT radio3_ADC_Q3_pin = radio3_ADC_Q3, UCF_NET_STRING=("LOC=AD29", "IOSTANDARD = LVTTL")
    PORT radio3_ADC_Q4_pin = radio3_ADC_Q4, UCF_NET_STRING=("LOC=AB26", "IOSTANDARD = LVTTL")
    PORT radio3_ADC_Q5_pin = radio3_ADC_Q5, UCF_NET_STRING=("LOC=AB27", "IOSTANDARD = LVTTL")
    PORT radio3_ADC_Q6_pin = radio3_ADC_Q6, UCF_NET_STRING=("LOC=AA28", "IOSTANDARD = LVTTL")
    PORT radio3_ADC_Q7_pin = radio3_ADC_Q7, UCF_NET_STRING=("LOC=AC28", "IOSTANDARD = LVTTL")
    PORT radio3_ADC_Q8_pin = radio3_ADC_Q8, UCF_NET_STRING=("LOC=AL34", "IOSTANDARD = LVTTL")
    PORT radio3_ADC_Q9_pin = radio3_ADC_Q9, UCF_NET_STRING=("LOC=AJ34", "IOSTANDARD = LVTTL")
    PORT radio3_ADC_Q10_pin = radio3_ADC_Q10, UCF_NET_STRING=("LOC=AK33", "IOSTANDARD = LVTTL")
    PORT radio3_ADC_Q11_pin = radio3_ADC_Q11, UCF_NET_STRING=("LOC=AK34", "IOSTANDARD = LVTTL")
    PORT radio3_ADC_Q12_pin = radio3_ADC_Q12, UCF_NET_STRING=("LOC=AJ35", "IOSTANDARD = LVTTL")
    PORT radio3_ADC_Q13_pin = radio3_ADC_Q13, UCF_NET_STRING=("LOC=AG33", "IOSTANDARD = LVTTL")

##Radio Bridge for Slot #4
#   PORT radio4_conv_clk_p = radio4_conv_clk_p, UCF_NET_STRING=("LOC=N30", "IOSTANDARD=LVDCI_33")
    PORT radio4_conv_clk_p = radio4_conv_clk_p, UCF_NET_STRING=("LOC=H33", "IOSTANDARD=LVTTL")
    PORT radio4_EEPROM_IO = radio4_EEPROM_IO, UCF_NET_STRING=("LOC=L31", "IOSTANDARD=LVTTL", "SLEW = SLOW", "DRIVE = 8")
    PORT dac4_spi_clk_pin = dac4_spi_clk, UCF_NET_STRING=("LOC=G28", "IOSTANDARD=LVTTL")
    PORT dac4_spi_cs_pin = dac4_spi_cs, UCF_NET_STRING=("LOC=D25", "IOSTANDARD=LVTTL")
    PORT dac4_spi_data_pin = dac4_spi_data, UCF_NET_STRING=("LOC=C28", "IOSTANDARD=LVTTL")
    PORT radio4_24PA_pin = radio4_24PA, UCF_NET_STRING=("LOC=H27", "IOSTANDARD=LVTTL")
    PORT radio4_5PA_pin = radio4_5PA, UCF_NET_STRING=("LOC=L26", "IOSTANDARD=LVTTL")
    PORT radio4_ANTSW0_pin = radio4_ANTSW0, UCF_NET_STRING=("LOC=U31", "IOSTANDARD=LVTTL")
    PORT radio4_ANTSW1_pin = radio4_ANTSW1, UCF_NET_STRING=("LOC=V29", "IOSTANDARD=LVTTL")
    PORT radio4_dac4_PLL_LOCK_pin = radio4_dac4_PLL_LOCK, UCF_NET_STRING=("LOC=F30", "IOSTANDARD=LVTTL")
    PORT radio4_dac4_RESET_pin = radio4_dac4_RESET, UCF_NET_STRING=("LOC=G26", "IOSTANDARD=LVTTL")
    PORT radio4_DIPSW0_pin = radio4_DIPSW0, UCF_NET_STRING=("LOC=C30", "IOSTANDARD=LVTTL")
    PORT radio4_DIPSW1_pin = radio4_DIPSW1, UCF_NET_STRING=("LOC=H25", "IOSTANDARD=LVTTL")
    PORT radio4_DIPSW2_pin = radio4_DIPSW2, UCF_NET_STRING=("LOC=C24", "IOSTANDARD=LVTTL")
    PORT radio4_DIPSW3_pin = radio4_DIPSW3, UCF_NET_STRING=("LOC=J27", "IOSTANDARD=LVTTL")
    PORT radio4_LD_pin = radio4_LD, UCF_NET_STRING=("LOC=E24", "IOSTANDARD=LVTTL")
    PORT radio4_LED0_pin = radio4_LED0, UCF_NET_STRING=("LOC=U26", "IOSTANDARD=LVTTL")
    PORT radio4_LED1_pin = radio4_LED1, UCF_NET_STRING=("LOC=N35", "IOSTANDARD=LVTTL")
    PORT radio4_LED2_pin = radio4_LED2, UCF_NET_STRING=("LOC=N34", "IOSTANDARD=LVTTL")
    PORT radio4_rssi_ADC_clk_pin = radio4_rssi_ADC_clk, UCF_NET_STRING=("LOC=L33", "IOSTANDARD=LVTTL")
    PORT radio4_RSSI_ADC_CLAMP_pin = radio4_RSSI_ADC_CLAMP, UCF_NET_STRING=("LOC=J37", "IOSTANDARD=LVTTL")
    PORT radio4_RSSI_ADC_D0_pin = radio4_RSSI_ADC_D0, UCF_NET_STRING=("LOC=J36", "IOSTANDARD=LVTTL", "PULLDOWN")
    PORT radio4_RSSI_ADC_D1_pin = radio4_RSSI_ADC_D1, UCF_NET_STRING=("LOC=C33", "IOSTANDARD=LVTTL", "PULLDOWN")
    PORT radio4_RSSI_ADC_D2_pin = radio4_RSSI_ADC_D2, UCF_NET_STRING=("LOC=G37", "IOSTANDARD=LVTTL", "PULLDOWN")
    PORT radio4_RSSI_ADC_D3_pin = radio4_RSSI_ADC_D3, UCF_NET_STRING=("LOC=C32", "IOSTANDARD=LVTTL", "PULLDOWN")
    PORT radio4_RSSI_ADC_D4_pin = radio4_RSSI_ADC_D4, UCF_NET_STRING=("LOC=G36", "IOSTANDARD=LVTTL", "PULLDOWN")
    PORT radio4_RSSI_ADC_D5_pin = radio4_RSSI_ADC_D5, UCF_NET_STRING=("LOC=D36", "IOSTANDARD=LVTTL", "PULLDOWN")
    PORT radio4_RSSI_ADC_D6_pin = radio4_RSSI_ADC_D6, UCF_NET_STRING=("LOC=D34", "IOSTANDARD=LVTTL", "PULLDOWN")
    PORT radio4_RSSI_ADC_D7_pin = radio4_RSSI_ADC_D7, UCF_NET_STRING=("LOC=E36", "IOSTANDARD=LVTTL", "PULLDOWN")
    PORT radio4_RSSI_ADC_D8_pin = radio4_RSSI_ADC_D8, UCF_NET_STRING=("LOC=E34", "IOSTANDARD=LVTTL", "PULLDOWN")
    PORT radio4_RSSI_ADC_D9_pin = radio4_RSSI_ADC_D9, UCF_NET_STRING=("LOC=H35", "IOSTANDARD=LVTTL", "PULLDOWN")
    PORT radio4_RSSI_ADC_HIZ_pin = radio4_RSSI_ADC_HIZ, UCF_NET_STRING=("LOC=H37", "IOSTANDARD=LVTTL")
    PORT radio4_RSSI_ADC_OTR_pin = radio4_RSSI_ADC_OTR, UCF_NET_STRING=("LOC=D35", "IOSTANDARD=LVTTL")
    PORT radio4_RSSI_ADC_SLEEP_pin = radio4_RSSI_ADC_SLEEP, UCF_NET_STRING=("LOC=C35", "IOSTANDARD=LVTTL")
    PORT radio4_RX_ADC_DCS_pin = radio4_RX_ADC_DCS, UCF_NET_STRING=("LOC=K32", "IOSTANDARD=LVTTL")
    PORT radio4_RX_ADC_DFS_pin = radio4_RX_ADC_DFS, UCF_NET_STRING=("LOC=G31", "IOSTANDARD=LVTTL")
    PORT radio4_RX_ADC_OTRA_pin = radio4_RX_ADC_OTRA, UCF_NET_STRING=("LOC=N32", "IOSTANDARD=LVTTL")
    PORT radio4_RX_ADC_OTRB_pin = radio4_RX_ADC_OTRB, UCF_NET_STRING=("LOC=V27", "IOSTANDARD=LVTTL")
    PORT radio4_RX_ADC_PWDNA_pin = radio4_RX_ADC_PWDNA, UCF_NET_STRING=("LOC=U30", "IOSTANDARD=LVTTL")
    PORT radio4_RX_ADC_PWDNB_pin = radio4_RX_ADC_PWDNB, UCF_NET_STRING=("LOC=M32", "IOSTANDARD=LVTTL")
    PORT radio4_RxEn_pin = radio4_RxEn, UCF_NET_STRING=("LOC=L34", "IOSTANDARD=LVTTL")
    PORT radio4_RxHP_pin = radio4_RxHP, UCF_NET_STRING=("LOC=J26", "IOSTANDARD=LVTTL")
    PORT radio4_SHDN_pin = radio4_SHDN, UCF_NET_STRING=("LOC=K34", "IOSTANDARD=LVTTL")
    PORT radio4_spi_clk_pin = radio4_spi_clk, UCF_NET_STRING=("LOC=J29", "IOSTANDARD=LVTTL")
    PORT radio4_spi_cs_pin = radio4_spi_cs, UCF_NET_STRING=("LOC=H28", "IOSTANDARD=LVTTL")
    PORT radio4_spi_data_pin = radio4_spi_data, UCF_NET_STRING=("LOC=D24", "IOSTANDARD=LVTTL")
    PORT radio4_TxEn_pin = radio4_TxEn, UCF_NET_STRING=("LOC=H30", "IOSTANDARD=LVTTL")

    PORT radio4_b0_pin = radio4_b0, UCF_NET_STRING=("LOC=G30", "IOSTANDARD = LVTTL") #Radio_B1
    PORT radio4_b1_pin = radio4_b1, UCF_NET_STRING=("LOC=U33", "IOSTANDARD = LVTTL") #Radio_B2
    PORT radio4_b2_pin = radio4_b2, UCF_NET_STRING=("LOC=G32", "IOSTANDARD = LVTTL") #Radio_B3
    PORT radio4_b3_pin = radio4_b3, UCF_NET_STRING=("LOC=J34", "IOSTANDARD = LVTTL") #Radio_B4
    PORT radio4_b4_pin = radio4_b4, UCF_NET_STRING=("LOC=K29", "IOSTANDARD = LVTTL") #Radio_B5
    PORT radio4_b5_pin = radio4_b5, UCF_NET_STRING=("LOC=J35", "IOSTANDARD = LVTTL") #Radio_B6
    PORT radio4_b6_pin = radio4_b6, UCF_NET_STRING=("LOC=U32", "IOSTANDARD = LVTTL") #Radio_B7

    PORT radio4_DAC_I0_pin = radio4_DAC_I0, UCF_NET_STRING=("LOC=E32", "IOSTANDARD = LVTTL")
    PORT radio4_DAC_I1_pin = radio4_DAC_I1, UCF_NET_STRING=("LOC=D27", "IOSTANDARD = LVTTL")
    PORT radio4_DAC_I2_pin = radio4_DAC_I2, UCF_NET_STRING=("LOC=E33", "IOSTANDARD = LVTTL")
    PORT radio4_DAC_I3_pin = radio4_DAC_I3, UCF_NET_STRING=("LOC=F34", "IOSTANDARD = LVTTL")
    PORT radio4_DAC_I4_pin = radio4_DAC_I4, UCF_NET_STRING=("LOC=F35", "IOSTANDARD = LVTTL")
    PORT radio4_DAC_I5_pin = radio4_DAC_I5, UCF_NET_STRING=("LOC=F33", "IOSTANDARD = LVTTL")
    PORT radio4_DAC_I6_pin = radio4_DAC_I6, UCF_NET_STRING=("LOC=D31", "IOSTANDARD = LVTTL")
    PORT radio4_DAC_I7_pin = radio4_DAC_I7, UCF_NET_STRING=("LOC=D30", "IOSTANDARD = LVTTL")
    PORT radio4_DAC_I8_pin = radio4_DAC_I8, UCF_NET_STRING=("LOC=E28", "IOSTANDARD = LVTTL")
    PORT radio4_DAC_I9_pin = radio4_DAC_I9, UCF_NET_STRING=("LOC=F36", "IOSTANDARD = LVTTL")
    PORT radio4_DAC_I10_pin = radio4_DAC_I10, UCF_NET_STRING=("LOC=G33", "IOSTANDARD = LVTTL")
    PORT radio4_DAC_I11_pin = radio4_DAC_I11, UCF_NET_STRING=("LOC=G35", "IOSTANDARD = LVTTL")
    PORT radio4_DAC_I12_pin = radio4_DAC_I12, UCF_NET_STRING=("LOC=D29", "IOSTANDARD = LVTTL")
    PORT radio4_DAC_I13_pin = radio4_DAC_I13, UCF_NET_STRING=("LOC=C29", "IOSTANDARD = LVTTL")
    PORT radio4_DAC_I14_pin = radio4_DAC_I14, UCF_NET_STRING=("LOC=D37", "IOSTANDARD = LVTTL")
    PORT radio4_DAC_I15_pin = radio4_DAC_I15, UCF_NET_STRING=("LOC=E37", "IOSTANDARD = LVTTL")

    PORT radio4_DAC_Q0_pin = radio4_DAC_Q0, UCF_NET_STRING=("LOC=D26", "IOSTANDARD = LVTTL")
    PORT radio4_DAC_Q1_pin = radio4_DAC_Q1, UCF_NET_STRING=("LOC=C27", "IOSTANDARD = LVTTL")
    PORT radio4_DAC_Q2_pin = radio4_DAC_Q2, UCF_NET_STRING=("LOC=G25", "IOSTANDARD = LVTTL")
    PORT radio4_DAC_Q3_pin = radio4_DAC_Q3, UCF_NET_STRING=("LOC=C25", "IOSTANDARD = LVTTL")
    PORT radio4_DAC_Q4_pin = radio4_DAC_Q4, UCF_NET_STRING=("LOC=F29", "IOSTANDARD = LVTTL")
    PORT radio4_DAC_Q5_pin = radio4_DAC_Q5, UCF_NET_STRING=("LOC=F24", "IOSTANDARD = LVTTL")
    PORT radio4_DAC_Q6_pin = radio4_DAC_Q6, UCF_NET_STRING=("LOC=E26", "IOSTANDARD = LVTTL")
    PORT radio4_DAC_Q7_pin = radio4_DAC_Q7, UCF_NET_STRING=("LOC=D32", "IOSTANDARD = LVTTL")
    PORT radio4_DAC_Q8_pin = radio4_DAC_Q8, UCF_NET_STRING=("LOC=F28", "IOSTANDARD = LVTTL")
    PORT radio4_DAC_Q9_pin = radio4_DAC_Q9, UCF_NET_STRING=("LOC=F31", "IOSTANDARD = LVTTL")
    PORT radio4_DAC_Q10_pin = radio4_DAC_Q10, UCF_NET_STRING=("LOC=E27", "IOSTANDARD = LVTTL")
    PORT radio4_DAC_Q11_pin = radio4_DAC_Q11, UCF_NET_STRING=("LOC=F26", "IOSTANDARD = LVTTL")
    PORT radio4_DAC_Q12_pin = radio4_DAC_Q12, UCF_NET_STRING=("LOC=H34", "IOSTANDARD = LVTTL")
    PORT radio4_DAC_Q13_pin = radio4_DAC_Q13, UCF_NET_STRING=("LOC=E31", "IOSTANDARD = LVTTL")
    PORT radio4_DAC_Q14_pin = radio4_DAC_Q14, UCF_NET_STRING=("LOC=F25", "IOSTANDARD = LVTTL")
    PORT radio4_DAC_Q15_pin = radio4_DAC_Q15, UCF_NET_STRING=("LOC=E29", "IOSTANDARD = LVTTL")
    PORT radio4_ADC_I0_pin = radio4_ADC_I0, UCF_NET_STRING=("LOC=K26", "IOSTANDARD = LVTTL")
    PORT radio4_ADC_I1_pin = radio4_ADC_I1, UCF_NET_STRING=("LOC=P30", "IOSTANDARD = LVTTL")
    PORT radio4_ADC_I2_pin = radio4_ADC_I2, UCF_NET_STRING=("LOC=M27", "IOSTANDARD = LVTTL")
    PORT radio4_ADC_I3_pin = radio4_ADC_I3, UCF_NET_STRING=("LOC=AF23", "IOSTANDARD = LVTTL")
    PORT radio4_ADC_I4_pin = radio4_ADC_I4, UCF_NET_STRING=("LOC=T29", "IOSTANDARD = LVTTL")
    PORT radio4_ADC_I5_pin = radio4_ADC_I5, UCF_NET_STRING=("LOC=R31", "IOSTANDARD = LVTTL")
    PORT radio4_ADC_I6_pin = radio4_ADC_I6, UCF_NET_STRING=("LOC=V30", "IOSTANDARD = LVTTL")
    PORT radio4_ADC_I7_pin = radio4_ADC_I7, UCF_NET_STRING=("LOC=M31", "IOSTANDARD = LVTTL")
    PORT radio4_ADC_I8_pin = radio4_ADC_I8, UCF_NET_STRING=("LOC=W26", "IOSTANDARD = LVTTL")
    PORT radio4_ADC_I9_pin = radio4_ADC_I9, UCF_NET_STRING=("LOC=K27", "IOSTANDARD = LVTTL")
    PORT radio4_ADC_I10_pin = radio4_ADC_I10, UCF_NET_STRING=("LOC=M26", "IOSTANDARD = LVTTL")
    PORT radio4_ADC_I11_pin = radio4_ADC_I11, UCF_NET_STRING=("LOC=L29", "IOSTANDARD = LVTTL")
    PORT radio4_ADC_I12_pin = radio4_ADC_I12, UCF_NET_STRING=("LOC=V25", "IOSTANDARD = LVTTL")
    PORT radio4_ADC_I13_pin = radio4_ADC_I13, UCF_NET_STRING=("LOC=W27", "IOSTANDARD = LVTTL")
    PORT radio4_ADC_Q0_pin = radio4_ADC_Q0, UCF_NET_STRING=("LOC=K28", "IOSTANDARD = LVTTL")
    PORT radio4_ADC_Q1_pin = radio4_ADC_Q1, UCF_NET_STRING=("LOC=J32", "IOSTANDARD = LVTTL")
    PORT radio4_ADC_Q2_pin = radio4_ADC_Q2, UCF_NET_STRING=("LOC=K33", "IOSTANDARD = LVTTL")
    PORT radio4_ADC_Q3_pin = radio4_ADC_Q3, UCF_NET_STRING=("LOC=H32", "IOSTANDARD = LVTTL")
    PORT radio4_ADC_Q4_pin = radio4_ADC_Q4, UCF_NET_STRING=("LOC=L30", "IOSTANDARD = LVTTL")
    PORT radio4_ADC_Q5_pin = radio4_ADC_Q5, UCF_NET_STRING=("LOC=M33", "IOSTANDARD = LVTTL")
    PORT radio4_ADC_Q6_pin = radio4_ADC_Q6, UCF_NET_STRING=("LOC=M35", "IOSTANDARD = LVTTL")
    PORT radio4_ADC_Q7_pin = radio4_ADC_Q7, UCF_NET_STRING=("LOC=P32", "IOSTANDARD = LVTTL")
    PORT radio4_ADC_Q8_pin = radio4_ADC_Q8, UCF_NET_STRING=("LOC=U28", "IOSTANDARD = LVTTL")
    PORT radio4_ADC_Q9_pin = radio4_ADC_Q9, UCF_NET_STRING=("LOC=N33", "IOSTANDARD = LVTTL")
    PORT radio4_ADC_Q10_pin = radio4_ADC_Q10, UCF_NET_STRING=("LOC=U27", "IOSTANDARD = LVTTL")
    PORT radio4_ADC_Q11_pin = radio4_ADC_Q11, UCF_NET_STRING=("LOC=L28", "IOSTANDARD = LVTTL")
    PORT radio4_ADC_Q12_pin = radio4_ADC_Q12, UCF_NET_STRING=("LOC=V28", "IOSTANDARD = LVTTL")
    PORT radio4_ADC_Q13_pin = radio4_ADC_Q13, UCF_NET_STRING=("LOC=M28", "IOSTANDARD = LVTTL")

### Analog Bridge slot4 ###
    PORT analog4_clock_out_pin = analog4_clock_out, UCF_NET_STRING=("LOC=E29", "IOSTANDARD = LVTTL")

    PORT analog4_DAC1_A0_pin = analog4_DAC1_A0, UCF_NET_STRING=("LOC=U31", "IOSTANDARD = LVTTL")
    PORT analog4_DAC1_A1_pin = analog4_DAC1_A1, UCF_NET_STRING=("LOC=V29", "IOSTANDARD = LVTTL")
    PORT analog4_DAC1_A2_pin = analog4_DAC1_A2, UCF_NET_STRING=("LOC=H27", "IOSTANDARD = LVTTL")
    PORT analog4_DAC1_A3_pin = analog4_DAC1_A3, UCF_NET_STRING=("LOC=L26", "IOSTANDARD = LVTTL")
    PORT analog4_DAC1_A4_pin = analog4_DAC1_A4, UCF_NET_STRING=("LOC=T30", "IOSTANDARD = LVTTL")
    PORT analog4_DAC1_A5_pin = analog4_DAC1_A5, UCF_NET_STRING=("LOC=U26", "IOSTANDARD = LVTTL")
    PORT analog4_DAC1_A6_pin = analog4_DAC1_A6, UCF_NET_STRING=("LOC=N35", "IOSTANDARD = LVTTL")
    PORT analog4_DAC1_A7_pin = analog4_DAC1_A7, UCF_NET_STRING=("LOC=N34", "IOSTANDARD = LVTTL")
    PORT analog4_DAC1_A8_pin = analog4_DAC1_A8, UCF_NET_STRING=("LOC=U30", "IOSTANDARD = LVTTL")
    PORT analog4_DAC1_A9_pin = analog4_DAC1_A9, UCF_NET_STRING=("LOC=N32", "IOSTANDARD = LVTTL")
    PORT analog4_DAC1_A10_pin = analog4_DAC1_A10, UCF_NET_STRING=("LOC=W27", "IOSTANDARD = LVTTL")
    PORT analog4_DAC1_A11_pin = analog4_DAC1_A11, UCF_NET_STRING=("LOC=V25", "IOSTANDARD = LVTTL")
    PORT analog4_DAC1_A12_pin = analog4_DAC1_A12, UCF_NET_STRING=("LOC=M26", "IOSTANDARD = LVTTL")
    PORT analog4_DAC1_A13_pin = analog4_DAC1_A13, UCF_NET_STRING=("LOC=K27", "IOSTANDARD = LVTTL")

    PORT analog4_DAC1_B0_pin = analog4_DAC1_B0, UCF_NET_STRING=("LOC=T31", "IOSTANDARD = LVTTL")
    PORT analog4_DAC1_B1_pin = analog4_DAC1_B1, UCF_NET_STRING=("LOC=L35", "IOSTANDARD = LVTTL")
    PORT analog4_DAC1_B2_pin = analog4_DAC1_B2, UCF_NET_STRING=("LOC=P31", "IOSTANDARD = LVTTL")
    PORT analog4_DAC1_B3_pin = analog4_DAC1_B3, UCF_NET_STRING=("LOC=L33", "IOSTANDARD = LVTTL")
    PORT analog4_DAC1_B4_pin = analog4_DAC1_B4, UCF_NET_STRING=("LOC=H29", "IOSTANDARD = LVTTL")
    PORT analog4_DAC1_B5_pin = analog4_DAC1_B5, UCF_NET_STRING=("LOC=R32", "IOSTANDARD = LVTTL")
    PORT analog4_DAC1_B6_pin = analog4_DAC1_B6, UCF_NET_STRING=("LOC=J30", "IOSTANDARD = LVTTL")
    PORT analog4_DAC1_B7_pin = analog4_DAC1_B7, UCF_NET_STRING=("LOC=G30", "IOSTANDARD = LVTTL")
    PORT analog4_DAC1_B8_pin = analog4_DAC1_B8, UCF_NET_STRING=("LOC=U33", "IOSTANDARD = LVTTL")
    PORT analog4_DAC1_B9_pin = analog4_DAC1_B9, UCF_NET_STRING=("LOC=G32", "IOSTANDARD = LVTTL")
    PORT analog4_DAC1_B10_pin = analog4_DAC1_B10, UCF_NET_STRING=("LOC=J34", "IOSTANDARD = LVTTL")
    PORT analog4_DAC1_B11_pin = analog4_DAC1_B11, UCF_NET_STRING=("LOC=K29", "IOSTANDARD = LVTTL")
    PORT analog4_DAC1_B12_pin = analog4_DAC1_B12, UCF_NET_STRING=("LOC=J35", "IOSTANDARD = LVTTL")
    PORT analog4_DAC1_B13_pin = analog4_DAC1_B13, UCF_NET_STRING=("LOC=U32", "IOSTANDARD = LVTTL")

    PORT analog4_DAC2_A0_pin = analog4_DAC2_A0, UCF_NET_STRING=("LOC=J26", "IOSTANDARD = LVTTL")
    PORT analog4_DAC2_A1_pin = analog4_DAC2_A1, UCF_NET_STRING=("LOC=L34", "IOSTANDARD = LVTTL")
    PORT analog4_DAC2_A2_pin = analog4_DAC2_A2, UCF_NET_STRING=("LOC=K34", "IOSTANDARD = LVTTL")
    PORT analog4_DAC2_A3_pin = analog4_DAC2_A3, UCF_NET_STRING=("LOC=K32", "IOSTANDARD = LVTTL")
    PORT analog4_DAC2_A4_pin = analog4_DAC2_A4, UCF_NET_STRING=("LOC=G31", "IOSTANDARD = LVTTL")
    PORT analog4_DAC2_A5_pin = analog4_DAC2_A5, UCF_NET_STRING=("LOC=M32", "IOSTANDARD = LVTTL")
    PORT analog4_DAC2_A6_pin = analog4_DAC2_A6, UCF_NET_STRING=("LOC=K28", "IOSTANDARD = LVTTL")
    PORT analog4_DAC2_A7_pin = analog4_DAC2_A7, UCF_NET_STRING=("LOC=J32", "IOSTANDARD = LVTTL")
    PORT analog4_DAC2_A8_pin = analog4_DAC2_A8, UCF_NET_STRING=("LOC=K33", "IOSTANDARD = LVTTL")
    PORT analog4_DAC2_A9_pin = analog4_DAC2_A9, UCF_NET_STRING=("LOC=H32", "IOSTANDARD = LVTTL")
    PORT analog4_DAC2_A10_pin = analog4_DAC2_A10, UCF_NET_STRING=("LOC=L30", "IOSTANDARD = LVTTL")
    PORT analog4_DAC2_A11_pin = analog4_DAC2_A11, UCF_NET_STRING=("LOC=M33", "IOSTANDARD = LVTTL")
    PORT analog4_DAC2_A12_pin = analog4_DAC2_A12, UCF_NET_STRING=("LOC=M35", "IOSTANDARD = LVTTL")
    PORT analog4_DAC2_A13_pin = analog4_DAC2_A13, UCF_NET_STRING=("LOC=P32", "IOSTANDARD = LVTTL")

    PORT analog4_DAC2_B0_pin = analog4_DAC2_B0, UCF_NET_STRING=("LOC=F24", "IOSTANDARD = LVTTL")
    PORT analog4_DAC2_B1_pin = analog4_DAC2_B1, UCF_NET_STRING=("LOC=F29", "IOSTANDARD = LVTTL")
    PORT analog4_DAC2_B2_pin = analog4_DAC2_B2, UCF_NET_STRING=("LOC=C25", "IOSTANDARD = LVTTL")
    PORT analog4_DAC2_B3_pin = analog4_DAC2_B3, UCF_NET_STRING=("LOC=G25", "IOSTANDARD = LVTTL")
    PORT analog4_DAC2_B4_pin = analog4_DAC2_B4, UCF_NET_STRING=("LOC=C27", "IOSTANDARD = LVTTL")
    PORT analog4_DAC2_B5_pin = analog4_DAC2_B5, UCF_NET_STRING=("LOC=D26", "IOSTANDARD = LVTTL")
    PORT analog4_DAC2_B6_pin = analog4_DAC2_B6, UCF_NET_STRING=("LOC=G27", "IOSTANDARD = LVTTL")
    PORT analog4_DAC2_B7_pin = analog4_DAC2_B7, UCF_NET_STRING=("LOC=C28", "IOSTANDARD = LVTTL")
    PORT analog4_DAC2_B8_pin = analog4_DAC2_B8, UCF_NET_STRING=("LOC=G28", "IOSTANDARD = LVTTL")
    PORT analog4_DAC2_B9_pin = analog4_DAC2_B9, UCF_NET_STRING=("LOC=D25", "IOSTANDARD = LVTTL")
    PORT analog4_DAC2_B10_pin = analog4_DAC2_B10, UCF_NET_STRING=("LOC=G26", "IOSTANDARD = LVTTL")
    PORT analog4_DAC2_B11_pin = analog4_DAC2_B11, UCF_NET_STRING=("LOC=E24", "IOSTANDARD = LVTTL")
    PORT analog4_DAC2_B12_pin = analog4_DAC2_B12, UCF_NET_STRING=("LOC=H28", "IOSTANDARD = LVTTL")
    PORT analog4_DAC2_B13_pin = analog4_DAC2_B13, UCF_NET_STRING=("LOC=J29", "IOSTANDARD = LVTTL")

    PORT analog4_DAC1_sleep_pin = analog4_DAC1_sleep, UCF_NET_STRING=("LOC=L29", "IOSTANDARD = LVTTL")
    PORT analog4_DAC2_sleep_pin = analog4_DAC2_sleep, UCF_NET_STRING=("LOC=M31", "IOSTANDARD = LVTTL")

    PORT analog4_ADC_A0_pin = analog4_ADC_A0, UCF_NET_STRING=("LOC=E34", "IOSTANDARD = LVTTL", "PULLDOWN")
    PORT analog4_ADC_A1_pin = analog4_ADC_A1, UCF_NET_STRING=("LOC=E37", "IOSTANDARD = LVTTL", "PULLDOWN")
    PORT analog4_ADC_A2_pin = analog4_ADC_A2, UCF_NET_STRING=("LOC=D37", "IOSTANDARD = LVTTL", "PULLDOWN")
    PORT analog4_ADC_A3_pin = analog4_ADC_A3, UCF_NET_STRING=("LOC=C29", "IOSTANDARD = LVTTL", "PULLDOWN")
    PORT analog4_ADC_A4_pin = analog4_ADC_A4, UCF_NET_STRING=("LOC=D29", "IOSTANDARD = LVTTL", "PULLDOWN")
    PORT analog4_ADC_A5_pin = analog4_ADC_A5, UCF_NET_STRING=("LOC=G35", "IOSTANDARD = LVTTL", "PULLDOWN")
    PORT analog4_ADC_A6_pin = analog4_ADC_A6, UCF_NET_STRING=("LOC=G33", "IOSTANDARD = LVTTL", "PULLDOWN")
    PORT analog4_ADC_A7_pin = analog4_ADC_A7, UCF_NET_STRING=("LOC=F36", "IOSTANDARD = LVTTL", "PULLDOWN")
    PORT analog4_ADC_A8_pin = analog4_ADC_A8, UCF_NET_STRING=("LOC=E28", "IOSTANDARD = LVTTL", "PULLDOWN")
    PORT analog4_ADC_A9_pin = analog4_ADC_A9, UCF_NET_STRING=("LOC=D30", "IOSTANDARD = LVTTL", "PULLDOWN")
    PORT analog4_ADC_A10_pin = analog4_ADC_A10, UCF_NET_STRING=("LOC=C30", "IOSTANDARD = LVTTL", "PULLDOWN")
    PORT analog4_ADC_A11_pin = analog4_ADC_A11, UCF_NET_STRING=("LOC=H25", "IOSTANDARD = LVTTL", "PULLDOWN")
    PORT analog4_ADC_A12_pin = analog4_ADC_A12, UCF_NET_STRING=("LOC=J27", "IOSTANDARD = LVTTL", "PULLDOWN")
    PORT analog4_ADC_A13_pin = analog4_ADC_A13, UCF_NET_STRING=("LOC=F34", "IOSTANDARD = LVTTL", "PULLDOWN")

    PORT analog4_ADC_B0_pin = analog4_ADC_B0, UCF_NET_STRING=("LOC=J37", "IOSTANDARD = LVTTL", "PULLDOWN")
    PORT analog4_ADC_B1_pin = analog4_ADC_B1, UCF_NET_STRING=("LOC=C34", "IOSTANDARD = LVTTL", "PULLDOWN")
    PORT analog4_ADC_B2_pin = analog4_ADC_B2, UCF_NET_STRING=("LOC=C35", "IOSTANDARD = LVTTL", "PULLDOWN")
    PORT analog4_ADC_B3_pin = analog4_ADC_B3, UCF_NET_STRING=("LOC=H37", "IOSTANDARD = LVTTL", "PULLDOWN")
    PORT analog4_ADC_B4_pin = analog4_ADC_B4, UCF_NET_STRING=("LOC=D36", "IOSTANDARD = LVTTL", "PULLDOWN")
    PORT analog4_ADC_B5_pin = analog4_ADC_B5, UCF_NET_STRING=("LOC=G36", "IOSTANDARD = LVTTL", "PULLDOWN")
    PORT analog4_ADC_B6_pin = analog4_ADC_B6, UCF_NET_STRING=("LOC=C32", "IOSTANDARD = LVTTL", "PULLDOWN")
    PORT analog4_ADC_B7_pin = analog4_ADC_B7, UCF_NET_STRING=("LOC=G37", "IOSTANDARD = LVTTL", "PULLDOWN")
    PORT analog4_ADC_B8_pin = analog4_ADC_B8, UCF_NET_STRING=("LOC=C33", "IOSTANDARD = LVTTL", "PULLDOWN")
    PORT analog4_ADC_B9_pin = analog4_ADC_B9, UCF_NET_STRING=("LOC=J36", "IOSTANDARD = LVTTL", "PULLDOWN")
    PORT analog4_ADC_B10_pin = analog4_ADC_B10, UCF_NET_STRING=("LOC=D34", "IOSTANDARD = LVTTL", "PULLDOWN")
    PORT analog4_ADC_B11_pin = analog4_ADC_B11, UCF_NET_STRING=("LOC=E36", "IOSTANDARD = LVTTL", "PULLDOWN")
    PORT analog4_ADC_B12_pin = analog4_ADC_B12, UCF_NET_STRING=("LOC=D35", "IOSTANDARD = LVTTL", "PULLDOWN")
    PORT analog4_ADC_B13_pin = analog4_ADC_B13, UCF_NET_STRING=("LOC=H35", "IOSTANDARD = LVTTL", "PULLDOWN")

    PORT analog4_ADC_DFS_pin = analog4_ADC_DFS, UCF_NET_STRING=("LOC=F33", "IOSTANDARD = LVTTL")
    PORT analog4_ADC_DCS_pin = analog4_ADC_DCS, UCF_NET_STRING=("LOC=F35", "IOSTANDARD = LVTTL")
    PORT analog4_ADC_pdwnA_pin = analog4_ADC_pdwnA, UCF_NET_STRING=("LOC=H30", "IOSTANDARD = LVTTL")
    PORT analog4_ADC_pdwnB_pin = analog4_ADC_pdwnB, UCF_NET_STRING=("LOC=D31", "IOSTANDARD = LVTTL")
    PORT analog4_ADC_otrA_pin = analog4_ADC_otrA, UCF_NET_STRING=("LOC=D24", "IOSTANDARD = LVTTL")
    PORT analog4_ADC_otrB_pin = analog4_ADC_otrB, UCF_NET_STRING=("LOC=C24", "IOSTANDARD = LVTTL")
    
    PORT analog4_LED0_pin = analog4_LED0, UCF_NET_STRING=("LOC=T29", "IOSTANDARD = LVTTL")
    PORT analog4_LED1_pin = analog4_LED1, UCF_NET_STRING=("LOC=M27", "IOSTANDARD = LVTTL")
    PORT analog4_LED2_pin = analog4_LED2, UCF_NET_STRING=("LOC=AF23", "IOSTANDARD = LVTTL")

### USER I/O Board in Slot 1
    #LCD SPI interface
    PORT user_ioboard_slot1_sdi = user_ioboard_slot1_sdi, UCF_NET_STRING=("LOC=L8", "SLEW=SLOW", "IOSTANDARD=LVTTL")
    PORT userio_board_slot1_scl = userio_board_slot1_scl, UCF_NET_STRING=("LOC=L6", "SLEW=SLOW", "IOSTANDARD=LVTTL")
    PORT userio_board_slot1_resetlcd = userio_board_slot1_resetlcd, UCF_NET_STRING=("LOC=K8", "SLEW=SLOW", "IOSTANDARD=LVTTL")
    PORT userio_board_slot1_cs = userio_board_slot1_cs, UCF_NET_STRING=("LOC=J12", "SLEW=SLOW", "IOSTANDARD=LVTTL")

    #Buzzer output
    PORT userio_board_slot1_buzzer = userio_board_slot1_buzzer, UCF_NET_STRING=("LOC=K3", "SLEW=SLOW", "IOSTANDARD=LVTTL")

    #Trackball I/O
    PORT userio_board_slot1_trackball_yscn = userio_board_slot1_trackball_yscn, UCF_NET_STRING=("LOC=J10", "SLEW=SLOW", "IOSTANDARD=LVTTL")
    PORT userio_board_slot1_trackball_sel1 = userio_board_slot1_trackball_sel1, UCF_NET_STRING=("LOC=J9", "SLEW=SLOW", "IOSTANDARD=LVTTL")
    PORT userio_board_slot1_trackball_xscn = userio_board_slot1_trackball_xscn, UCF_NET_STRING=("LOC=K9", "SLEW=SLOW", "IOSTANDARD=LVTTL")
    PORT userio_board_slot1_trackball_sel2 = userio_board_slot1_trackball_sel2, UCF_NET_STRING=("LOC=M6", "SLEW=SLOW", "IOSTANDARD=LVTTL")
    PORT userio_board_slot1_trackball_oyn = userio_board_slot1_trackball_oyn, UCF_NET_STRING=("LOC=M7", "SLEW=SLOW", "IOSTANDARD=LVTTL")
    PORT userio_board_slot1_trackball_oy = userio_board_slot1_trackball_oy, UCF_NET_STRING=("LOC=J11", "SLEW=SLOW", "IOSTANDARD=LVTTL")
    PORT userio_board_slot1_trackball_oxn = userio_board_slot1_trackball_oxn, UCF_NET_STRING=("LOC=M3", "SLEW=SLOW", "IOSTANDARD=LVTTL")
    PORT userio_board_slot1_trackball_ox = userio_board_slot1_trackball_ox, UCF_NET_STRING=("LOC=M10", "SLEW=SLOW", "IOSTANDARD=LVTTL")

    #Eight LEDs
    PORT userio_board_slot1_leds_0 = userio_board_slot1_leds_0, UCF_NET_STRING=("LOC=E16", "SLEW=SLOW", "IOSTANDARD=LVTTL")
    PORT userio_board_slot1_leds_1 = userio_board_slot1_leds_1, UCF_NET_STRING=("LOC=H13", "SLEW=SLOW", "IOSTANDARD=LVTTL")
    PORT userio_board_slot1_leds_2 = userio_board_slot1_leds_2, UCF_NET_STRING=("LOC=F16", "SLEW=SLOW", "IOSTANDARD=LVTTL")
    PORT userio_board_slot1_leds_3 = userio_board_slot1_leds_3, UCF_NET_STRING=("LOC=C14", "SLEW=SLOW", "IOSTANDARD=LVTTL")
    PORT userio_board_slot1_leds_4 = userio_board_slot1_leds_4, UCF_NET_STRING=("LOC=H5", "SLEW=SLOW", "IOSTANDARD=LVTTL")
    PORT userio_board_slot1_leds_5 = userio_board_slot1_leds_5, UCF_NET_STRING=("LOC=H14", "SLEW=SLOW", "IOSTANDARD=LVTTL")
    PORT userio_board_slot1_leds_6 = userio_board_slot1_leds_6, UCF_NET_STRING=("LOC=F15", "SLEW=SLOW", "IOSTANDARD=LVTTL")
    PORT userio_board_slot1_leds_7 = userio_board_slot1_leds_7, UCF_NET_STRING=("LOC=H12", "SLEW=SLOW", "IOSTANDARD=LVTTL")

    #DIP switch
    PORT userio_board_slot1_dip_switch_0 = userio_board_slot1_dip_switch_0, UCF_NET_STRING=("LOC=H8", "SLEW=SLOW", "IOSTANDARD=LVTTL")
    PORT userio_board_slot1_dip_switch_1 = userio_board_slot1_dip_switch_1, UCF_NET_STRING=("LOC=D16", "SLEW=SLOW", "IOSTANDARD=LVTTL")
    PORT userio_board_slot1_dip_switch_2 = userio_board_slot1_dip_switch_2, UCF_NET_STRING=("LOC=H10", "SLEW=SLOW", "IOSTANDARD=LVTTL")
    PORT userio_board_slot1_dip_switch_3 = userio_board_slot1_dip_switch_3, UCF_NET_STRING=("LOC=D15", "SLEW=SLOW", "IOSTANDARD=LVTTL")

    #Six small push buttons
    PORT userio_board_slot1_buttons_small_0 = userio_board_slot1_buttons_small_0, UCF_NET_STRING=("LOC=G7", "SLEW=SLOW", "IOSTANDARD=LVTTL")
    PORT userio_board_slot1_buttons_small_1 = userio_board_slot1_buttons_small_1, UCF_NET_STRING=("LOC=G10", "SLEW=SLOW", "IOSTANDARD=LVTTL")
    PORT userio_board_slot1_buttons_small_2 = userio_board_slot1_buttons_small_2, UCF_NET_STRING=("LOC=G11", "SLEW=SLOW", "IOSTANDARD=LVTTL")
    PORT userio_board_slot1_buttons_small_3 = userio_board_slot1_buttons_small_3, UCF_NET_STRING=("LOC=D14", "SLEW=SLOW", "IOSTANDARD=LVTTL")
    PORT userio_board_slot1_buttons_small_4 = userio_board_slot1_buttons_small_4, UCF_NET_STRING=("LOC=F11", "SLEW=SLOW", "IOSTANDARD=LVTTL")
    PORT userio_board_slot1_buttons_small_5 = userio_board_slot1_buttons_small_5, UCF_NET_STRING=("LOC=G13", "SLEW=SLOW", "IOSTANDARD=LVTTL")

    #Two big push buttons
    PORT userio_board_slot1_buttons_big_0 = userio_board_slot1_buttons_big_0, UCF_NET_STRING=("LOC=P6", "SLEW=SLOW", "IOSTANDARD=LVTTL")
    PORT userio_board_slot1_buttons_big_1 = userio_board_slot1_buttons_big_1, UCF_NET_STRING=("LOC=J4", "SLEW=SLOW", "IOSTANDARD=LVTTL")

### FPGA BOARD EEPROM Serial Number and Memory interface
    PORT DQ0 = EEPROM_0_DQ0, UCF_NET_STRING=("LOC=AH22", "IOSTANDARD = LVTTL", "SLEW = SLOW", "DRIVE = 8") 

END