source: PlatformSupport/XBD/boards/Rice_University_WARP_FPGA_V4FX100_v22_ClkBoard/data/TriMode_MAC_GMII_xps_ll_temac.ucf

Last change on this file was 1346, checked in by sgupta, 14 years ago

xbd for v2.2

File size: 2.6 KB
Line 
1#### Additional TriMode_MAC_GMII constraints
2
3NET "*tx_gmii_mii_clk_in_0*"    TNM_NET = "clk_phy_tx_clk0";
4NET "*tx_gmii_mii_clk_out_0*"   TNM_NET = "clk_phy_tx_clk0";
5TIMESPEC "TS_phy_tx_clk0"     = PERIOD "clk_phy_tx_clk0" 7700 ps HIGH 50 %;
6
7NET "*gmii_rx_clk_0*"         TNM_NET = "clk_phy_rx_clk0";
8NET "*gmii_rx_clk_delay_0*"   TNM_NET = "clk_phy_rx_clk0";
9NET "*gmii_rx_clk_ibufg_0*"   TNM_NET = "clk_phy_rx_clk0";
10TIMESPEC "TS_phy_rx_clk0"     = PERIOD "clk_phy_rx_clk0" 7700 ps HIGH 50 %;
11
12NET "*tx_client_clk_in_0*"      TNM_NET = "clk_client_tx_clk0";
13NET "*tx_client_clk_out_0*"     TNM_NET = "clk_client_tx_clk0";
14TIMESPEC "TS_client_tx_clk0"            = PERIOD "clk_client_tx_clk0" 7700 ps HIGH 50 %;
15
16NET "*rx_client_clk_in_0*"      TNM_NET = "clk_client_rx_clk0";
17NET "*rx_client_clk_out_0*"     TNM_NET = "clk_client_rx_clk0";
18TIMESPEC "TS_client_rx_clk0"            = PERIOD "clk_client_rx_clk0" 7700 ps HIGH 50 %;
19
20NET "*mii_tx_clk_0*"            TNM_NET = "clk_mii_tx_clk0";
21TIMESPEC "TS_mii_tx_clk0"               = PERIOD "clk_mii_tx_clk0" 25000 ps HIGH 50 %;
22
23
24#################### EMAC 0 GMII Constraints ########################
25INST "*mii0?RXD_TO_MAC*"    IOB = true;
26INST "*mii0?RX_DV_TO_MAC"   IOB = true;
27INST "*mii0?RX_ER_TO_MAC"   IOB = true;
28
29INST "*gmii0/*gmii_rxd?_delay"    IOBDELAY_TYPE = FIXED;
30INST "*gmii0/*gmii_rx_dv_delay"   IOBDELAY_TYPE = FIXED;
31INST "*gmii0/*gmii_rx_er_delay"   IOBDELAY_TYPE = FIXED;
32INST "*gmii0/*gmii_rxd?_delay"    IOBDELAY_VALUE = 0;
33INST "*gmii0/*gmii_rx_dv_delay"   IOBDELAY_VALUE = 0;
34INST "*gmii0/*gmii_rx_er_delay"   IOBDELAY_VALUE = 0;
35INST "*gmii_rx_clk_0_delay"       IOBDELAY_TYPE = FIXED;
36INST "*gmii_rx_clk_0_delay"       IOBDELAY_VALUE = 30;
37
38INST "fpga_0_TriMode_MAC_GMII_GMII_TXD_0_pin<?>"     TNM = "sig_mii_tx_0";
39INST "fpga_0_TriMode_MAC_GMII_GMII_TX_EN_0_pin"      TNM = "sig_mii_tx_0";
40INST "fpga_0_TriMode_MAC_GMII_GMII_TX_ER_0_pin"      TNM = "sig_mii_tx_0";
41
42INST "fpga_0_TriMode_MAC_GMII_GMII_RXD_0_pin<?>"     TNM = "sig_mii_rx_0";
43INST "fpga_0_TriMode_MAC_GMII_GMII_RX_DV_0_pin"      TNM = "sig_mii_rx_0";
44INST "fpga_0_TriMode_MAC_GMII_GMII_RX_ER_0_pin"      TNM = "sig_mii_rx_0";
45
46# Need to TIG between the LocalLink clock and the rx_client and tx_client clocks
47NET "*/LlinkTemac0_CLK*" TNM_NET = "LLCLK";
48TIMESPEC "TS_LL_CLK_2_RX_CLIENT_CLK"  = FROM LLCLK TO clk_client_rx_clk0 8000 ps DATAPATHONLY;
49TIMESPEC "TS_LL_CLK_2_TX_CLIENT_CLK"  = FROM LLCLK TO clk_client_tx_clk0 8000 ps DATAPATHONLY;
50TIMESPEC "TS_RX_CLIENT_CLK_2_LL_CLK"  = FROM clk_client_rx_clk0 TO LLCLK 10000 ps DATAPATHONLY;
51TIMESPEC "TS_TX_CLIENT_CLK_2_LL_CLK"  = FROM clk_client_tx_clk0 TO LLCLK 10000 ps DATAPATHONLY;
52
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