source: ReferenceDesigns/w3_802.11/sysgen/wlan_agc/wlan_agc_init.m

Last change on this file was 6176, checked in by murphpo, 6 years ago

Fixed a 1-cycle latency difference between IQ and IQ_Valid through the DCO IIR filters. In rare cases this latency difference manifested as an extra sample being inserted into the output IQ stream when the DCO filter was enabled at the end of the AGC process.

File size: 2.6 KB
Line 
1%xlLoadChipScopeData('../wlan_phy_rx_pmd/rx_sigs/adi_tx_noPktDet_v0.prn'); cs_interp = 1; cs_start = 2500; cs_end = 4500;
2%payload_vec = [zeros(25,1); complex(ADC_I(cs_start:cs_interp:end), ADC_Q(cs_start:cs_interp:end));];
3
4load('../wlan_phy_rx_pmd/rx_sigs/wlan_tx_NONHT_MCS0_52B.mat');
5payload_vec = [zeros(25,1); wlan_tx_out(:)];
6%payload_vec = [zeros(25,1); sim_sig];%wlan_tx_out(:)];
7
8%payload_vec = 0;
9raw_rx_I.time = [];
10raw_rx_Q.time = [];
11
12DCO_I = 0;
13DCO_Q = 0;
14G_I = 1;
15G_Q = 1;
16
17raw_rx_I.signals.values = DCO_I + G_I*real(payload_vec);
18raw_rx_Q.signals.values = DCO_Q + G_Q*imag(payload_vec);
19
20
21PHY_CONFIG_PKT_DET_CORR_THRESH = 90;
22PHY_CONFIG_PKT_DET_ENERGY_THRESH = 1;
23PHY_CONFIG_PKT_DET_MIN_DURR = 4;
24
25%% Register Init
26
27%Timing registers
28AGC_TIMING_CAPT_RSSI_1 = 8;
29AGC_TIMING_CAPT_RSSI_2 = 24;
30AGC_TIMING_CAPT_V_DB = 48;
31AGC_TIMING_START_DCO = 60;
32
33AGC_TIMING_EN_IIR_FILT = 93;
34AGC_TIMING_DONE = 95;
35
36AGC_TIMING_RESET_RXHP = 0;
37AGC_TIMING_RESET_G_RF = 30;
38AGC_TIMING_RESET_G_BB = 25;
39
40
41%Config register
42AGC_G_RF_THRESH_32 = 256-52; %Reinterpret Fix8_0 to UFix8_0
43AGC_G_RF_THRESH_21 = 256-40; %Reinterpret Fix8_0 to UFix8_0
44AGC_RSSI_AVG_LEN_SEL = 0;
45AGC_V_DB_ADJ = 64-13; %Reinterpret Fix6_0 to UFix6_0
46AGC_INIT_G_BB = 24;
47
48%Target register
49AGC_TARGET_PWR = 64-15; %Reinterpret Fix6_0 to UFix6_0
50
51%IIR filt coefficients
52DCO_IIR_Coef_A1 = -0.98751192990731429;
53DCO_IIR_Coef_B0 =  0.99375596495365714;
54
55%Rx Power - RSSI calib register (-power values in dBm)
56RSSI_MIN_PWR_G_RF_3 = 100;
57RSSI_MIN_PWR_G_RF_2 = 85;
58RSSI_MIN_PWR_G_RF_1 = 70;
59
60
61REG_AGC_Timing_AGC = ...
62    2^0 * AGC_TIMING_CAPT_RSSI_1 + ... %UFix8_0
63    2^8 * AGC_TIMING_CAPT_RSSI_2 + ... %UFix8_0
64    2^16 * AGC_TIMING_CAPT_V_DB + ... %UFix8_0
65    2^24 * AGC_TIMING_DONE; %UFix8_0
66
67REG_AGC_Timing_DCO = ...
68    2^0 * AGC_TIMING_START_DCO + ... %UFix8_0
69    2^8 * AGC_TIMING_EN_IIR_FILT + ... %UFix8_0
70    0;
71
72REG_AGC_Timing_Reset = ...
73    2^0 * AGC_TIMING_RESET_RXHP + ... %UFix8_0
74    2^8 * AGC_TIMING_RESET_G_RF + ... %UFix8_0
75    2^16 * AGC_TIMING_RESET_G_BB + ... %UFix8_0
76    0;
77
78REG_AGC_Config = ...
79    2^0 * AGC_G_RF_THRESH_32 + ... %Fix8_0
80    2^8 * AGC_G_RF_THRESH_21 + ... %Fix8_0
81    2^16 * AGC_RSSI_AVG_LEN_SEL + ... %UFix2_0
82    2^18 * AGC_V_DB_ADJ + ... %Fix6_0
83    2^24 * AGC_INIT_G_BB + ... %UFix5_0
84    0;
85
86REG_AGC_Target = AGC_TARGET_PWR;
87
88REG_AGC_IIR_Coef_A1 = DCO_IIR_Coef_A1;
89REG_AGC_IIR_Coef_B0 = DCO_IIR_Coef_B0;
90
91REG_AGC_RSSI_RX_PWR_CALIB = ...
92    2^0 * RSSI_MIN_PWR_G_RF_3 + ... %UFix8_0
93    2^8 * RSSI_MIN_PWR_G_RF_2 + ... %UFix8_0
94    2^16 * RSSI_MIN_PWR_G_RF_1 + ... %UFix8_0
95    0;
96
97   
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