source: ReferenceDesigns/w3_802.11/sysgen/wlan_mac_hw/wlan_mac_hw_init.m

Last change on this file was 6263, checked in by murphpo, 4 years ago

Updated init script comments to match hardware, no design changes

File size: 4.7 KB
Line 
1addpath('./mcode_blocks');
2
3%Maximum interval values in usec
4% These determine bit widths of counters
5MAX_SLOT = 63;
6MAX_DIFS = 63;
7MAX_EIFS = 255;
8MAX_NAV = 4095;
9MAX_NUM_SLOTS = 2^16-1;
10
11%Calculate bit widths
12% All counters run at 160MHz (1/160 usec)
13NB_CNTR_SLOT = ceil(log2(MAX_SLOT * 160));
14NB_CNTR_DIFS = max(ceil(log2(MAX_DIFS * 160)), ceil(log2(MAX_EIFS * 160)));
15NB_CNTR_NAV = ceil(log2(MAX_NAV * 160));
16NB_CNTR_NUM_SLOTS = ceil(log2(MAX_NUM_SLOTS));
17NB_CNTR_POSTRX = 19; %big enough for SIFS and timeout
18
19%Max hardware latencies, used to calculate various MAC intervals
20PHY_RX_START_DLY = 25;
21
22%Actual hardware latencies, used to calibrate MAC intervals
23
24%D1: RxRfDelay + RxPLCPDelay
25% After pkt reception, D1 is delay from actual medium IDLE to PHY_RX_END
26hw_time_D1 = 1;
27
28%RxTx Turnaround
29% Time from PHY_TX_START.IND to PHY_TX_START.CONFIRM
30%  (delay from "transmit now" signal to first energy on medium)
31hw_time_rxtx_turnaround = 1;
32
33
34ticks_per_usec = 10;
35
36%%%%%%%%%%%%%%%%%%%%%%%%%
37% MAC timing parameters
38INTERVAL_SIFS = 10;
39INTERVAL_SLOT = 9;
40INTERVAL_DIFS = INTERVAL_SIFS + 2*INTERVAL_SLOT;
41INTERVAL_EIFS = INTERVAL_SIFS + INTERVAL_DIFS + 100; %guess TACK_slow for now
42INTERVAL_ACKTIMEOUT = INTERVAL_SIFS + INTERVAL_SLOT + PHY_RX_START_DLY;
43
44%%%%%%%%%%%%%%%%%%%%%%%%%
45% Calibrated MAC times
46
47%TxDIFS: instant to sample medium status after successful Rx
48calib_time_TxDIFS = INTERVAL_DIFS - hw_time_D1 - hw_time_rxtx_turnaround;
49
50%Adjustment for NAV times, to compensate dealy from actual idle to RX_END+FCS
51calib_time_NAV_adj = 0;
52
53REG_MAC_Intervals_1 = ...
54    2^0  * (10*INTERVAL_SLOT) + ... %b[9:0]
55    2^20 * (10*INTERVAL_DIFS) + ... %b[29:20]
56    0;
57   
58REG_MAC_Intervals_2 = ...
59    2^0  * (10*INTERVAL_EIFS) + ... %b[15:0]
60    2^16 * (10*INTERVAL_ACKTIMEOUT) + ... %b[31:16]
61    0;
62
63REG_MAC_Calib_Times = ...
64    2^0  * (10*calib_time_TxDIFS) + ... %b[9:0]
65    2^24 * (10*calib_time_NAV_adj) + ... %b[31:24]
66    0;
67
68REG_MAC_Tx_Ctrl_A_Params = 0;
69   
70REG_MAC_Tx_Ctrl_B_Params = 0;
71
72REG_MAC_Tx_Ctrl_C_Params = 0;
73
74REG_MAC_Tx_Ctrl_D_Params = 0;
75
76REG_MAC_PostRxTimers = ...
77    2^0  * (10*16) + ... %b[14:0] - timer 1 value
78    2^15 * (0)     + ... %b[15] - enable timer 1
79    2^16 * (10*16) + ... %b[30:16] - timer 2 value
80    2^31 * (0)     + ... %b[31] - enable timer 2
81    0;
82
83REG_MAC_PostTxTimers = ...
84    2^0  * (10*16) + ... %b[14:0] - timer 1 value
85    2^15 * (0)     + ... %b[15] - enable timer 1
86    2^16 * (10*16) + ... %b[30:16] - timer 2 value
87    2^31 * (0)     + ... %b[31] - enable timer 2
88    0;
89
90
91REG_MAC_Backoff_Control = ...
92    2^0  * (0) + ... %b[15:0] - num BO slots
93    2^31 * (0) + ... %b[31] - Start backoff period immediately
94    0;
95
96REG_MAC_Control = ...
97    2^0  * (0) + ... %b[0] Reset
98    2^1  * (0) + ... %b[1] Disable NAV
99    2^2  * (0) + ... %b[2] Reset NAV
100    2^3  * (1) + ... %b[3] Block Rx on Tx
101    2^4  * (0) + ... %b[4] Reset TU latch
102    2^5  * (0) + ... %b[5] Ignore Rx PHY for CCA
103    2^6  * (0) + ... %b[6] Ignore Tx PHY for CCA
104    2^7  * (0) + ... %b[7] Ignore NAV for CCA
105    2^8  * (0) + ... %b[8] Force CCA=BUSY
106    2^9  * (0) + ... %b[9] --
107    2^10 * (0) + ... %b[10] Reset RX_STARTED latch
108    2^11 * (0) + ... %b[11] Reset Tx controller A
109    2^12 * (0) + ... %b[12] Reset Tx controller B
110    2^13 * (0) + ... %b[13] Reset Tx controller C
111    2^14 * (0) + ... %b[14] Reset Tx controller D
112    2^15 * (0) + ... %b[15] Reset Tx controller A backoff
113    2^16 * (0) + ... %b[16] Reset Tx controller C backoff
114    2^17 * (0) + ... %b[17] Reset Tx controller D backoff
115    2^18 * (0) + ... %b[18] Pause Tx controller A
116    2^19 * (0) + ... %b[19] Pause Tx controller C
117    2^20 * (0) + ... %b[20] Pause Tx controller D
118    2^21 * (0) + ... %b[21] Enbale ext CCA.BUSY input
119    2^22 * (0) + ... %b[22] Enable ext PostRx Timer 1 start
120    2^23 * (0) + ... %b[23] Reset Rx PHY active latches
121    2^24 * (0) + ... %b[24] Reset Tx PHY active latch
122    0;
123
124%Match 40-d8-55-04-21-4a
125%REG_NAV_Match_Addr_1 = hex2dec('0455d840');
126%REG_NAV_Match_Addr_2 = hex2dec('00004a21');
127
128%Default to zeros - won't match anything until overwritten by software
129REG_NAV_Match_Addr_1 = 0;
130REG_NAV_Match_Addr_2 = 0;
131
132mac_sim_rx_data_b.time = [];
133mac_sim_rx_data_b.signals.values = sscanf('48 11 2c 00 40 d8 55 04 21 4a 40 d8 55 04 21 5a 40 d8 55 04 21 4a f0 92 f7 db e5 d9 ', '%02x');
134NUM_BYTES = length(mac_sim_rx_data_b.signals.values);
135
136mac_sim_rx_data_valid.time = [];
137mac_sim_rx_data_valid.signals.values = [zeros(1, NUM_BYTES) ones(1, NUM_BYTES) zeros(1, NUM_BYTES)].';
138
139mac_sim_rx_data_addr.time = [];
140mac_sim_rx_data_addr.signals.values = [zeros(1, NUM_BYTES) 0:NUM_BYTES-1 zeros(1, NUM_BYTES)].';
141
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143
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