[6151] | 1 | |
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| 2 | function bit_match_ram_config(this_block) |
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| 3 | |
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| 4 | this_block.setTopLevelLanguage('Verilog'); |
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| 5 | |
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| 6 | this_block.setEntityName('bit_match_ram'); |
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| 7 | |
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| 8 | % System Generator has to assume that your entity has a combinational feed through; |
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| 9 | % if it doesn't, then comment out the following line: |
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| 10 | this_block.tagAsCombinational; |
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| 11 | |
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| 12 | this_block.addSimulinkInport('bit_in'); |
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| 13 | this_block.addSimulinkInport('bit_in_wr_en'); |
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| 14 | this_block.addSimulinkInport('addr_a'); |
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| 15 | this_block.addSimulinkInport('addr_b'); |
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| 16 | |
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| 17 | this_block.addSimulinkOutport('dout_a'); |
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| 18 | this_block.addSimulinkOutport('dout_b'); |
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| 19 | |
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| 20 | dout_a_port = this_block.port('dout_a'); |
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| 21 | dout_a_port.setType('UFix_32_0'); |
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| 22 | dout_b_port = this_block.port('dout_b'); |
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| 23 | dout_b_port.setType('UFix_32_0'); |
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| 24 | |
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| 25 | % ----------------------------- |
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| 26 | if (this_block.inputTypesKnown) |
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| 27 | % do input type checking, dynamic output type and generic setup in this code block. |
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| 28 | |
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| 29 | if (this_block.port('bit_in').width ~= 1); |
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| 30 | this_block.setError('Input data type for port "bit_in" must have width=1.'); |
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| 31 | end |
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| 32 | |
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| 33 | if (this_block.port('bit_in_wr_en').width ~= 1); |
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| 34 | this_block.setError('Input data type for port "bit_in_wr_en" must have width=1.'); |
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| 35 | end |
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| 36 | |
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| 37 | if (this_block.port('addr_a').width ~= 15); |
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| 38 | this_block.setError('Input data type for port "addr_a" must have width=10.'); |
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| 39 | end |
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| 40 | |
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| 41 | if (this_block.port('addr_b').width ~= 15); |
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| 42 | this_block.setError('Input data type for port "addr_b" must have width=10.'); |
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| 43 | end |
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| 44 | |
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| 45 | end % if(inputTypesKnown) |
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| 46 | % ----------------------------- |
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| 47 | |
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| 48 | % ----------------------------- |
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| 49 | if (this_block.inputRatesKnown) |
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| 50 | setup_as_single_rate(this_block,'clk','ce') |
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| 51 | end % if(inputRatesKnown) |
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| 52 | % ----------------------------- |
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| 53 | |
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| 54 | % (!) Set the inout port rate to be the same as the first input |
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| 55 | % rate. Change the following code if this is untrue. |
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| 56 | uniqueInputRates = unique(this_block.getInputRates); |
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| 57 | |
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| 58 | |
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| 59 | % Add addtional source files as needed. |
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| 60 | % |------------- |
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| 61 | % | Add files in the order in which they should be compiled. |
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| 62 | % | If two files "a.vhd" and "b.vhd" contain the entities |
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| 63 | % | entity_a and entity_b, and entity_a contains a |
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| 64 | % | component of type entity_b, the correct sequence of |
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| 65 | % | addFile() calls would be: |
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| 66 | % | this_block.addFile('b.vhd'); |
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| 67 | % | this_block.addFile('a.vhd'); |
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| 68 | % |------------- |
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| 69 | |
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| 70 | % this_block.addFile(''); |
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| 71 | % this_block.addFile(''); |
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| 72 | this_block.addFile('blackboxes/bit_match_ram.v'); |
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| 73 | this_block.addFile('blackboxes/bit_match_ram_blkmemgen.ngc'); |
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| 74 | return; |
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| 75 | |
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| 76 | |
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| 77 | % ------------------------------------------------------------ |
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| 78 | |
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| 79 | function setup_as_single_rate(block,clkname,cename) |
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| 80 | inputRates = block.inputRates; |
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| 81 | uniqueInputRates = unique(inputRates); |
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| 82 | if (length(uniqueInputRates)==1 & uniqueInputRates(1)==Inf) |
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| 83 | block.addError('The inputs to this block cannot all be constant.'); |
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| 84 | return; |
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| 85 | end |
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| 86 | if (uniqueInputRates(end) == Inf) |
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| 87 | hasConstantInput = true; |
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| 88 | uniqueInputRates = uniqueInputRates(1:end-1); |
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| 89 | end |
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| 90 | if (length(uniqueInputRates) ~= 1) |
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| 91 | block.addError('The inputs to this block must run at a single rate.'); |
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| 92 | return; |
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| 93 | end |
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| 94 | theInputRate = uniqueInputRates(1); |
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| 95 | for i = 1:block.numSimulinkOutports |
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| 96 | block.outport(i).setRate(theInputRate); |
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| 97 | end |
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| 98 | block.addClkCEPair(clkname,cename,theInputRate); |
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| 99 | return; |
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| 100 | |
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| 101 | % ------------------------------------------------------------ |
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| 102 | |
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