source: ReferenceDesigns/w3_802.11/sysgen/wlan_phy_rx_pmd/blackboxes/bit_match_ram_config.m

function bit_match_ram_config(this_block)

  this_block.setTopLevelLanguage('Verilog');

  this_block.setEntityName('bit_match_ram');

  % System Generator has to assume that your entity  has a combinational feed through; 
  %   if it  doesn't, then comment out the following line:
  this_block.tagAsCombinational;

  this_block.addSimulinkInport('bit_in');
  this_block.addSimulinkInport('bit_in_wr_en');
  this_block.addSimulinkInport('addr_a');
  this_block.addSimulinkInport('addr_b');

  this_block.addSimulinkOutport('dout_a');
  this_block.addSimulinkOutport('dout_b');

  dout_a_port = this_block.port('dout_a');
  dout_a_port.setType('UFix_32_0');
  dout_b_port = this_block.port('dout_b');
  dout_b_port.setType('UFix_32_0');

  % -----------------------------
  if (this_block.inputTypesKnown)
    % do input type checking, dynamic output type and generic setup in this code block.

    if (this_block.port('bit_in').width ~= 1);
      this_block.setError('Input data type for port "bit_in" must have width=1.');
    end

    if (this_block.port('bit_in_wr_en').width ~= 1);
      this_block.setError('Input data type for port "bit_in_wr_en" must have width=1.');
    end

    if (this_block.port('addr_a').width ~= 15);
      this_block.setError('Input data type for port "addr_a" must have width=10.');
    end

    if (this_block.port('addr_b').width ~= 15);
      this_block.setError('Input data type for port "addr_b" must have width=10.');
    end

  end  % if(inputTypesKnown)
  % -----------------------------

  % -----------------------------
   if (this_block.inputRatesKnown)
     setup_as_single_rate(this_block,'clk','ce')
   end  % if(inputRatesKnown)
  % -----------------------------

    % (!) Set the inout port rate to be the same as the first input 
    %     rate. Change the following code if this is untrue.
    uniqueInputRates = unique(this_block.getInputRates);


  % Add addtional source files as needed.
  %  |-------------
  %  | Add files in the order in which they should be compiled.
  %  | If two files "a.vhd" and "b.vhd" contain the entities
  %  | entity_a and entity_b, and entity_a contains a
  %  | component of type entity_b, the correct sequence of
  %  | addFile() calls would be:
  %  |    this_block.addFile('b.vhd');
  %  |    this_block.addFile('a.vhd');
  %  |-------------

  %    this_block.addFile('');
  %    this_block.addFile('');
  this_block.addFile('blackboxes/bit_match_ram.v');
  this_block.addFile('blackboxes/bit_match_ram_blkmemgen.ngc');
return;


% ------------------------------------------------------------

function setup_as_single_rate(block,clkname,cename) 
  inputRates = block.inputRates; 
  uniqueInputRates = unique(inputRates); 
  if (length(uniqueInputRates)==1 & uniqueInputRates(1)==Inf) 
    block.addError('The inputs to this block cannot all be constant.'); 
    return; 
  end 
  if (uniqueInputRates(end) == Inf) 
     hasConstantInput = true; 
     uniqueInputRates = uniqueInputRates(1:end-1); 
  end 
  if (length(uniqueInputRates) ~= 1) 
    block.addError('The inputs to this block must run at a single rate.'); 
    return; 
  end 
  theInputRate = uniqueInputRates(1); 
  for i = 1:block.numSimulinkOutports 
     block.outport(i).setRate(theInputRate); 
  end 
  block.addClkCEPair(clkname,cename,theInputRate); 
  return; 

% ------------------------------------------------------------