1 | module deinterleaver_ram( |
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2 | clk, |
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3 | ce, |
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4 | wea, |
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5 | addra, |
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6 | dina, |
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7 | douta, |
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8 | web, |
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9 | addrb, |
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10 | dinb, |
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11 | doutb |
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12 | ); |
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13 | |
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14 | //Sysgen blackboxes must have clk and ce ports |
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15 | // VHDL wrapper uses std_logic for these signals |
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16 | input clk; |
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17 | input ce; |
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18 | |
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19 | // Sysgen instantiates this module in a VHDL wrapper. The wrapper uses std_logic_vector(0:0) signals |
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20 | // to connect to this module's ports. It's *very* important the scalar I/O below have dimensions [0:0]. |
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21 | // Without these XST bizarrely decides no connection is made and optimizes out the interleaver RAM. |
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22 | // Using Sysgen's "port.useHDLVector(false)" in the config.m would probably achieve the same thing. |
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23 | |
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24 | input [31:0] dina; |
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25 | input [0:0] wea; |
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26 | input [8:0] addra; |
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27 | output [3:0] douta; |
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28 | |
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29 | input [31:0] dinb; |
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30 | input [0:0] web; |
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31 | input [8:0] addrb; |
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32 | output [3:0] doutb; |
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33 | |
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34 | //Map sysgen clk to BRAM clks |
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35 | // This module does not use Sysgen's clock enbale (ce) signal |
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36 | // The Sysgen model must run this block at the system sample rate |
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37 | wire clka, clkb; |
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38 | assign clka = clk; |
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39 | assign clkb = clk; |
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40 | |
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41 | // dp_ram_wr_32b_rd_4b_2048b is packaged as an ngc netlist cretaed with Coregen's Block Memory Generator |
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42 | // The block memory is configured as: |
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43 | // True dual port memory mode (required for different read/write widths) |
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44 | // Common clock (clka=clkb) |
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45 | // Write width A/B = 32 bits |
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46 | // Write depth = 64 (2048 bits total) |
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47 | // Read width A/B = 4 bits |
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48 | // Read depth = 512 (2048 / 4) |
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49 | // Always enbaled (no ena/enb ports) |
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50 | |
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51 | (* box_type = "black_box" *) |
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52 | dp_ram_wr_32b_rd_4b_2048b ram_inst ( |
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53 | .clka(clka), |
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54 | .wea(wea), |
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55 | .addra(addra), |
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56 | .dina(dina), |
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57 | .douta(douta), |
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58 | .clkb(clkb), |
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59 | .web(web), |
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60 | .addrb(addrb), |
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61 | .dinb(dinb), |
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62 | .doutb(doutb) |
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63 | ); |
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64 | |
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65 | endmodule |
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66 | |
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67 | //Define module for RAM blackbox - ngdbuild will substitute dp_ram_wr_32b_rd_4b_2048b.ngc during implementation |
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68 | // Code inside translate_off/translate_on only used for simulation |
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69 | // Implementation will use NGC netlist for RAM block |
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70 | module dp_ram_wr_32b_rd_4b_2048b( |
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71 | clka, |
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72 | wea, |
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73 | addra, |
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74 | dina, |
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75 | douta, |
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76 | clkb, |
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77 | web, |
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78 | addrb, |
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79 | dinb, |
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80 | doutb |
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81 | ); |
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82 | |
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83 | input clka; |
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84 | input [0 : 0] wea; |
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85 | input [8 : 0] addra; |
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86 | input [31 : 0] dina; |
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87 | output [3 : 0] douta; |
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88 | input clkb; |
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89 | input [0 : 0] web; |
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90 | input [8 : 0] addrb; |
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91 | input [31 : 0] dinb; |
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92 | output [3 : 0] doutb; |
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93 | |
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94 | // synthesis translate_off |
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95 | |
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96 | BLK_MEM_GEN_V7_3 #( |
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97 | .C_ADDRA_WIDTH(9), |
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98 | .C_ADDRB_WIDTH(9), |
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99 | .C_ALGORITHM(1), |
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100 | .C_AXI_ID_WIDTH(4), |
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101 | .C_AXI_SLAVE_TYPE(0), |
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102 | .C_AXI_TYPE(1), |
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103 | .C_BYTE_SIZE(9), |
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104 | .C_COMMON_CLK(1), |
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105 | .C_DEFAULT_DATA("0"), |
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106 | .C_DISABLE_WARN_BHV_COLL(0), |
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107 | .C_DISABLE_WARN_BHV_RANGE(0), |
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108 | .C_ENABLE_32BIT_ADDRESS(0), |
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109 | .C_FAMILY("virtex6"), |
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110 | .C_HAS_AXI_ID(0), |
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111 | .C_HAS_ENA(0), |
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112 | .C_HAS_ENB(0), |
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113 | .C_HAS_INJECTERR(0), |
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114 | .C_HAS_MEM_OUTPUT_REGS_A(0), |
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115 | .C_HAS_MEM_OUTPUT_REGS_B(0), |
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116 | .C_HAS_MUX_OUTPUT_REGS_A(0), |
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117 | .C_HAS_MUX_OUTPUT_REGS_B(0), |
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118 | .C_HAS_REGCEA(0), |
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119 | .C_HAS_REGCEB(0), |
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120 | .C_HAS_RSTA(0), |
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121 | .C_HAS_RSTB(0), |
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122 | .C_HAS_SOFTECC_INPUT_REGS_A(0), |
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123 | .C_HAS_SOFTECC_OUTPUT_REGS_B(0), |
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124 | .C_INIT_FILE("BlankString"), |
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125 | .C_INIT_FILE_NAME("no_coe_file_loaded"), |
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126 | .C_INITA_VAL("0"), |
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127 | .C_INITB_VAL("0"), |
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128 | .C_INTERFACE_TYPE(0), |
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129 | .C_LOAD_INIT_FILE(0), |
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130 | .C_MEM_TYPE(2), |
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131 | .C_MUX_PIPELINE_STAGES(0), |
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132 | .C_PRIM_TYPE(1), |
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133 | .C_READ_DEPTH_A(512), |
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134 | .C_READ_DEPTH_B(512), |
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135 | .C_READ_WIDTH_A(4), |
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136 | .C_READ_WIDTH_B(4), |
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137 | .C_RST_PRIORITY_A("CE"), |
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138 | .C_RST_PRIORITY_B("CE"), |
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139 | .C_RST_TYPE("SYNC"), |
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140 | .C_RSTRAM_A(0), |
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141 | .C_RSTRAM_B(0), |
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142 | .C_SIM_COLLISION_CHECK("ALL"), |
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143 | .C_USE_BRAM_BLOCK(0), |
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144 | .C_USE_BYTE_WEA(0), |
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145 | .C_USE_BYTE_WEB(0), |
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146 | .C_USE_DEFAULT_DATA(0), |
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147 | .C_USE_ECC(0), |
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148 | .C_USE_SOFTECC(0), |
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149 | .C_WEA_WIDTH(1), |
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150 | .C_WEB_WIDTH(1), |
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151 | .C_WRITE_DEPTH_A(64), |
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152 | .C_WRITE_DEPTH_B(64), |
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153 | .C_WRITE_MODE_A("WRITE_FIRST"), |
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154 | .C_WRITE_MODE_B("WRITE_FIRST"), |
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155 | .C_WRITE_WIDTH_A(32), |
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156 | .C_WRITE_WIDTH_B(32), |
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157 | .C_XDEVICEFAMILY("virtex6") |
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158 | ) |
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159 | inst ( |
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160 | .CLKA(clka), |
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161 | .WEA(wea), |
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162 | .ADDRA(addra), |
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163 | .DINA(dina), |
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164 | .DOUTA(douta), |
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165 | .CLKB(clkb), |
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166 | .WEB(web), |
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167 | .ADDRB(addrb), |
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168 | .DINB(dinb), |
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169 | .DOUTB(doutb), |
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170 | .RSTA(), |
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171 | .ENA(), |
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172 | .REGCEA(), |
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173 | .RSTB(), |
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174 | .ENB(), |
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175 | .REGCEB(), |
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176 | .INJECTSBITERR(), |
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177 | .INJECTDBITERR(), |
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178 | .SBITERR(), |
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179 | .DBITERR(), |
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180 | .RDADDRECC(), |
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181 | .S_ACLK(), |
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182 | .S_ARESETN(), |
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183 | .S_AXI_AWID(), |
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184 | .S_AXI_AWADDR(), |
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185 | .S_AXI_AWLEN(), |
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186 | .S_AXI_AWSIZE(), |
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187 | .S_AXI_AWBURST(), |
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188 | .S_AXI_AWVALID(), |
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189 | .S_AXI_AWREADY(), |
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190 | .S_AXI_WDATA(), |
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191 | .S_AXI_WSTRB(), |
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192 | .S_AXI_WLAST(), |
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193 | .S_AXI_WVALID(), |
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194 | .S_AXI_WREADY(), |
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195 | .S_AXI_BID(), |
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196 | .S_AXI_BRESP(), |
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197 | .S_AXI_BVALID(), |
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198 | .S_AXI_BREADY(), |
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199 | .S_AXI_ARID(), |
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200 | .S_AXI_ARADDR(), |
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201 | .S_AXI_ARLEN(), |
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202 | .S_AXI_ARSIZE(), |
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203 | .S_AXI_ARBURST(), |
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204 | .S_AXI_ARVALID(), |
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205 | .S_AXI_ARREADY(), |
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206 | .S_AXI_RID(), |
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207 | .S_AXI_RDATA(), |
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208 | .S_AXI_RRESP(), |
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209 | .S_AXI_RLAST(), |
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210 | .S_AXI_RVALID(), |
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211 | .S_AXI_RREADY(), |
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212 | .S_AXI_INJECTSBITERR(), |
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213 | .S_AXI_INJECTDBITERR(), |
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214 | .S_AXI_SBITERR(), |
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215 | .S_AXI_DBITERR(), |
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216 | .S_AXI_RDADDRECC() |
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217 | ); |
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218 | |
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219 | // synthesis translate_on |
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220 | |
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221 | endmodule |
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