[2088] | 1 | |
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| 2 | function vb_decoder_top_config(this_block) |
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| 3 | |
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| 4 | % Revision History: |
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| 5 | % |
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| 6 | % 13-Jul-2013 (13:25 hours): |
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| 7 | % Original code was machine generated by Xilinx's System Generator after parsing |
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| 8 | % S:\work\wlan\sysgen\wlan_phy_rx\decoder_dev\blackboxes\vb_decoder_top.v |
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| 9 | % |
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| 10 | % |
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| 11 | |
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| 12 | this_block.setTopLevelLanguage('Verilog'); |
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| 13 | |
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| 14 | this_block.setEntityName('vb_decoder_top'); |
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| 15 | |
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| 16 | % System Generator has to assume that your entity has a combinational feed through; |
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| 17 | % if it doesn't, then comment out the following line: |
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| 18 | this_block.tagAsCombinational; |
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| 19 | |
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| 20 | this_block.addSimulinkInport('llr_b1'); |
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| 21 | this_block.addSimulinkInport('llr_b0'); |
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| 22 | this_block.addSimulinkInport('vin'); |
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[2184] | 23 | this_block.addSimulinkInport('nrst'); |
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[2088] | 24 | this_block.addSimulinkInport('packet_start'); |
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| 25 | this_block.addSimulinkInport('packet_end'); |
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[4394] | 26 | this_block.addSimulinkInport('early_trace1'); |
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| 27 | this_block.addSimulinkInport('early_trace2'); |
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[2088] | 28 | |
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| 29 | this_block.addSimulinkOutport('done'); |
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| 30 | this_block.addSimulinkOutport('vout'); |
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| 31 | this_block.addSimulinkOutport('dout_in_byte'); |
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| 32 | |
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| 33 | done_port = this_block.port('done'); |
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| 34 | done_port.setType('UFix_1_0'); |
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| 35 | done_port.useHDLVector(false); |
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| 36 | vout_port = this_block.port('vout'); |
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| 37 | vout_port.setType('UFix_1_0'); |
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| 38 | vout_port.useHDLVector(false); |
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| 39 | dout_in_byte_port = this_block.port('dout_in_byte'); |
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| 40 | dout_in_byte_port.setType('UFix_8_0'); |
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| 41 | |
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| 42 | % ----------------------------- |
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| 43 | if (this_block.inputTypesKnown) |
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| 44 | % do input type checking, dynamic output type and generic setup in this code block. |
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| 45 | |
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| 46 | if (this_block.port('nrst').width ~= 1); |
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| 47 | this_block.setError('Input data type for port "nrst" must have width=1.'); |
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| 48 | end |
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| 49 | |
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| 50 | this_block.port('nrst').useHDLVector(false); |
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| 51 | |
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| 52 | if (this_block.port('packet_start').width ~= 1); |
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| 53 | this_block.setError('Input data type for port "packet_start" must have width=1.'); |
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| 54 | end |
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| 55 | |
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| 56 | this_block.port('packet_start').useHDLVector(false); |
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| 57 | |
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| 58 | if (this_block.port('packet_end').width ~= 1); |
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| 59 | this_block.setError('Input data type for port "packet_end" must have width=1.'); |
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| 60 | end |
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| 61 | |
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| 62 | this_block.port('packet_end').useHDLVector(false); |
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| 63 | |
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| 64 | if (this_block.port('vin').width ~= 1); |
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| 65 | this_block.setError('Input data type for port "vin" must have width=1.'); |
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| 66 | end |
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| 67 | |
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| 68 | this_block.port('vin').useHDLVector(false); |
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| 69 | |
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| 70 | % (!) Port 'llr_b1' appeared to have dynamic type in the HDL -- please add type checking as appropriate; |
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| 71 | |
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| 72 | % (!) Port 'llr_b0' appeared to have dynamic type in the HDL -- please add type checking as appropriate; |
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| 73 | |
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[4394] | 74 | if (this_block.port('early_trace1').width ~= 1); |
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| 75 | this_block.setError('Input data type for port "early_trace1" must have width=1.'); |
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[2088] | 76 | end |
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| 77 | |
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[4394] | 78 | this_block.port('early_trace1').useHDLVector(false); |
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[2088] | 79 | |
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[4394] | 80 | if (this_block.port('early_trace2').width ~= 1); |
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| 81 | this_block.setError('Input data type for port "early_trace2" must have width=1.'); |
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| 82 | end |
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| 83 | |
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| 84 | this_block.port('early_trace2').useHDLVector(false); |
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| 85 | |
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[2088] | 86 | end % if(inputTypesKnown) |
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| 87 | % ----------------------------- |
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| 88 | |
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| 89 | % ----------------------------- |
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| 90 | if (this_block.inputRatesKnown) |
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| 91 | setup_as_single_rate(this_block,'clk','ce') |
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| 92 | end % if(inputRatesKnown) |
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| 93 | % ----------------------------- |
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| 94 | |
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| 95 | % (!) Set the inout port rate to be the same as the first input |
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| 96 | % rate. Change the following code if this is untrue. |
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| 97 | uniqueInputRates = unique(this_block.getInputRates); |
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| 98 | |
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| 99 | % Add addtional source files as needed. |
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| 100 | % |------------- |
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| 101 | % | Add files in the order in which they should be compiled. |
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| 102 | % | If two files "a.vhd" and "b.vhd" contain the entities |
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| 103 | % | entity_a and entity_b, and entity_a contains a |
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| 104 | % | component of type entity_b, the correct sequence of |
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| 105 | % | addFile() calls would be: |
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| 106 | % | this_block.addFile('b.vhd'); |
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| 107 | % | this_block.addFile('a.vhd'); |
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| 108 | % |------------- |
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| 109 | |
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| 110 | % this_block.addFile(''); |
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| 111 | % this_block.addFile(''); |
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| 112 | this_block.addFile('blackboxes/vb_decoder_top.v'); |
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| 113 | this_block.addFile('blackboxes/vb_decoder_rest.v'); |
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| 114 | |
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| 115 | return; |
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| 116 | |
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| 117 | |
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| 118 | % ------------------------------------------------------------ |
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| 119 | |
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| 120 | function setup_as_single_rate(block,clkname,cename) |
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| 121 | inputRates = block.inputRates; |
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| 122 | uniqueInputRates = unique(inputRates); |
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| 123 | if (length(uniqueInputRates)==1 & uniqueInputRates(1)==Inf) |
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| 124 | block.addError('The inputs to this block cannot all be constant.'); |
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| 125 | return; |
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| 126 | end |
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| 127 | if (uniqueInputRates(end) == Inf) |
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| 128 | hasConstantInput = true; |
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| 129 | uniqueInputRates = uniqueInputRates(1:end-1); |
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| 130 | end |
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| 131 | if (length(uniqueInputRates) ~= 1) |
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| 132 | block.addError('The inputs to this block must run at a single rate.'); |
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| 133 | return; |
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| 134 | end |
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| 135 | theInputRate = uniqueInputRates(1); |
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| 136 | for i = 1:block.numSimulinkOutports |
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| 137 | block.outport(i).setRate(theInputRate); |
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| 138 | end |
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| 139 | block.addClkCEPair(clkname,cename,theInputRate); |
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| 140 | return; |
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| 141 | |
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| 142 | % ------------------------------------------------------------ |
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| 143 | |
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