source: ReferenceDesigns/w3_802.11/sysgen/wlan_phy_rx_pmd/blackboxes/vb_decoder_top_config.m

function vb_decoder_top_config(this_block)

  % Revision History:
  %
  %   13-Jul-2013  (13:25 hours):
  %     Original code was machine generated by Xilinx's System Generator after parsing
  %     S:\work\wlan\sysgen\wlan_phy_rx\decoder_dev\blackboxes\vb_decoder_top.v
  %
  %

  this_block.setTopLevelLanguage('Verilog');

  this_block.setEntityName('vb_decoder_top');

  % System Generator has to assume that your entity  has a combinational feed through; 
  %   if it  doesn't, then comment out the following line:
  this_block.tagAsCombinational;

  this_block.addSimulinkInport('llr_b1');
  this_block.addSimulinkInport('llr_b0');
  this_block.addSimulinkInport('vin');
  this_block.addSimulinkInport('nrst');
  this_block.addSimulinkInport('packet_start');
  this_block.addSimulinkInport('packet_end');
  this_block.addSimulinkInport('early_trace1');
  this_block.addSimulinkInport('early_trace2');

  this_block.addSimulinkOutport('done');
  this_block.addSimulinkOutport('vout');
  this_block.addSimulinkOutport('dout_in_byte');

  done_port = this_block.port('done');
  done_port.setType('UFix_1_0');
  done_port.useHDLVector(false);
  vout_port = this_block.port('vout');
  vout_port.setType('UFix_1_0');
  vout_port.useHDLVector(false);
  dout_in_byte_port = this_block.port('dout_in_byte');
  dout_in_byte_port.setType('UFix_8_0');

  % -----------------------------
  if (this_block.inputTypesKnown)
    % do input type checking, dynamic output type and generic setup in this code block.

    if (this_block.port('nrst').width ~= 1);
      this_block.setError('Input data type for port "nrst" must have width=1.');
    end

    this_block.port('nrst').useHDLVector(false);

    if (this_block.port('packet_start').width ~= 1);
      this_block.setError('Input data type for port "packet_start" must have width=1.');
    end

    this_block.port('packet_start').useHDLVector(false);

    if (this_block.port('packet_end').width ~= 1);
      this_block.setError('Input data type for port "packet_end" must have width=1.');
    end

    this_block.port('packet_end').useHDLVector(false);

    if (this_block.port('vin').width ~= 1);
      this_block.setError('Input data type for port "vin" must have width=1.');
    end

    this_block.port('vin').useHDLVector(false);

    % (!) Port 'llr_b1' appeared to have dynamic type in the HDL -- please add type checking as appropriate;

    % (!) Port 'llr_b0' appeared to have dynamic type in the HDL -- please add type checking as appropriate;

    if (this_block.port('early_trace1').width ~= 1);
      this_block.setError('Input data type for port "early_trace1" must have width=1.');
    end

    this_block.port('early_trace1').useHDLVector(false);

    if (this_block.port('early_trace2').width ~= 1);
      this_block.setError('Input data type for port "early_trace2" must have width=1.');
    end

    this_block.port('early_trace2').useHDLVector(false);

  end  % if(inputTypesKnown)
  % -----------------------------

  % -----------------------------
   if (this_block.inputRatesKnown)
     setup_as_single_rate(this_block,'clk','ce')
   end  % if(inputRatesKnown)
  % -----------------------------

    % (!) Set the inout port rate to be the same as the first input 
    %     rate. Change the following code if this is untrue.
    uniqueInputRates = unique(this_block.getInputRates);

  % Add addtional source files as needed.
  %  |-------------
  %  | Add files in the order in which they should be compiled.
  %  | If two files "a.vhd" and "b.vhd" contain the entities
  %  | entity_a and entity_b, and entity_a contains a
  %  | component of type entity_b, the correct sequence of
  %  | addFile() calls would be:
  %  |    this_block.addFile('b.vhd');
  %  |    this_block.addFile('a.vhd');
  %  |-------------

  %    this_block.addFile('');
  %    this_block.addFile('');
  this_block.addFile('blackboxes/vb_decoder_top.v');
  this_block.addFile('blackboxes/vb_decoder_rest.v');

return;


% ------------------------------------------------------------

function setup_as_single_rate(block,clkname,cename) 
  inputRates = block.inputRates; 
  uniqueInputRates = unique(inputRates); 
  if (length(uniqueInputRates)==1 & uniqueInputRates(1)==Inf) 
    block.addError('The inputs to this block cannot all be constant.'); 
    return; 
  end 
  if (uniqueInputRates(end) == Inf) 
     hasConstantInput = true; 
     uniqueInputRates = uniqueInputRates(1:end-1); 
  end 
  if (length(uniqueInputRates) ~= 1) 
    block.addError('The inputs to this block must run at a single rate.'); 
    return; 
  end 
  theInputRate = uniqueInputRates(1); 
  for i = 1:block.numSimulinkOutports 
     block.outport(i).setRate(theInputRate); 
  end 
  block.addClkCEPair(clkname,cename,theInputRate); 
  return; 

% ------------------------------------------------------------