source: ReferenceDesigns/w3_802.11/sysgen/wlan_phy_tx_pmd/blackboxes

Name Size Rev Age Author Last Change
../
interleaver_ram.v 5.4 KB 5118   7 years murphpo Better comments in black box wrapper
interleaver_ram.m 3.6 KB 5112   7 years murphpo Fixed blackbox issue (verilog ports must be vectors if VHDL wrapper …
dp_ram_wr_1b_rd_8b_512b.xco 3.2 KB 5119   7 years murphpo adding coregen xco file for interleaver RAM core
dp_ram_wr_1b_rd_8b_512b.ngc 12.7 KB 5110   7 years murphpo Updating interleaver RAM black box
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