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Last change
on this file was
1733,
checked in by murphpo, 12 years ago
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Updated PHY model with two fec_decoder black boxes and sim mux to select between them for sim/implementation. Also added script for generating simulation-only verilog for fec_decoder. All this is workaround for MATLAB crashing during simulation due to a bug in isim/Sysgen 13.4 that's under investigation by Xilinx.
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File size:
367 bytes
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| 1 | @echo off |
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| 2 | REM Copyright 2012 Xilinx, Inc. All rights reserved. |
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| 3 | |
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| 4 | echo. |
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| 5 | echo Synthesizing netlists... |
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| 6 | echo. |
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| 7 | xflow.exe -p xc4vfx100ff1517-11 -synth xst_verilog.opt fec_decoder_top.prj |
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| 8 | |
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| 9 | mv fec_decoder_top.ngc fec_decoder_simOnly.ngc |
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| 10 | |
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| 11 | echo. |
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| 12 | echo Generating simulation model... |
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| 13 | echo. |
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| 14 | netgen -sim -ofmt verilog -tm fec_decoder_simOnly fec_decoder_simOnly.ngc |
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