[1609] | 1 | |
---|
| 2 | function fec_encoder_config(this_block) |
---|
| 3 | |
---|
| 4 | % Revision History: |
---|
| 5 | % |
---|
| 6 | % 11-Oct-2010 (22:47 hours): |
---|
| 7 | % Original code was machine generated by Xilinx's System Generator after parsing |
---|
| 8 | % E:\My Dropbox\Project\WARP\Sysgen\Rev4\fec_encoder.v |
---|
| 9 | % |
---|
| 10 | % |
---|
| 11 | |
---|
| 12 | this_block.setTopLevelLanguage('Verilog'); |
---|
| 13 | |
---|
| 14 | this_block.setEntityName('fec_encoder'); |
---|
| 15 | |
---|
| 16 | % System Generator has to assume that your entity has a combinational feed through; |
---|
| 17 | % if it doesn't, then comment out the following line: |
---|
| 18 | this_block.tagAsCombinational; |
---|
| 19 | |
---|
| 20 | this_block.addSimulinkInport('nrst'); |
---|
| 21 | this_block.addSimulinkInport('start'); |
---|
| 22 | this_block.addSimulinkInport('coding_en'); |
---|
| 23 | this_block.addSimulinkInport('pkt_done'); |
---|
| 24 | this_block.addSimulinkInport('fec_rd'); |
---|
| 25 | this_block.addSimulinkInport('info_data'); |
---|
| 26 | this_block.addSimulinkInport('info_scram'); |
---|
| 27 | this_block.addSimulinkInport('info_len'); |
---|
| 28 | |
---|
| 29 | this_block.addSimulinkOutport('codeword_len'); |
---|
| 30 | this_block.addSimulinkOutport('info_rd'); |
---|
| 31 | this_block.addSimulinkOutport('info_raddr'); |
---|
| 32 | this_block.addSimulinkOutport('fec_data'); |
---|
| 33 | |
---|
| 34 | codeword_len_port = this_block.port('codeword_len'); |
---|
| 35 | codeword_len_port.setType('UFix_16_0'); |
---|
| 36 | info_rd_port = this_block.port('info_rd'); |
---|
| 37 | info_rd_port.setType('Bool'); |
---|
| 38 | info_rd_port.useHDLVector(false); |
---|
| 39 | info_raddr_port = this_block.port('info_raddr'); |
---|
| 40 | info_raddr_port.setType('UFix_14_0'); |
---|
| 41 | fec_data_port = this_block.port('fec_data'); |
---|
| 42 | fec_data_port.setType('UFix_8_0'); |
---|
| 43 | |
---|
| 44 | % ----------------------------- |
---|
| 45 | if (this_block.inputTypesKnown) |
---|
| 46 | % do input type checking, dynamic output type and generic setup in this code block. |
---|
| 47 | |
---|
| 48 | if (this_block.port('nrst').width ~= 1); |
---|
| 49 | this_block.setError('Input data type for port "nrst" must have width=1.'); |
---|
| 50 | end |
---|
| 51 | |
---|
| 52 | this_block.port('nrst').useHDLVector(false); |
---|
| 53 | |
---|
| 54 | if (this_block.port('start').width ~= 1); |
---|
| 55 | this_block.setError('Input data type for port "start" must have width=1.'); |
---|
| 56 | end |
---|
| 57 | |
---|
| 58 | this_block.port('start').useHDLVector(false); |
---|
| 59 | |
---|
| 60 | if (this_block.port('coding_en').width ~= 1); |
---|
| 61 | this_block.setError('Input data type for port "coding_en" must have width=1.'); |
---|
| 62 | end |
---|
| 63 | |
---|
| 64 | this_block.port('coding_en').useHDLVector(false); |
---|
| 65 | |
---|
| 66 | if (this_block.port('pkt_done').width ~= 1); |
---|
| 67 | this_block.setError('Input data type for port "pkt_done" must have width=1.'); |
---|
| 68 | end |
---|
| 69 | |
---|
| 70 | this_block.port('pkt_done').useHDLVector(false); |
---|
| 71 | |
---|
| 72 | if (this_block.port('fec_rd').width ~= 1); |
---|
| 73 | this_block.setError('Input data type for port "fec_rd" must have width=1.'); |
---|
| 74 | end |
---|
| 75 | |
---|
| 76 | this_block.port('fec_rd').useHDLVector(false); |
---|
| 77 | |
---|
| 78 | if (this_block.port('info_data').width ~= 8); |
---|
| 79 | this_block.setError('Input data type for port "info_data" must have width=8.'); |
---|
| 80 | end |
---|
| 81 | |
---|
| 82 | if (this_block.port('info_scram').width ~= 8); |
---|
| 83 | this_block.setError('Input data type for port "info_scram" must have width=8.'); |
---|
| 84 | end |
---|
| 85 | |
---|
| 86 | if (this_block.port('info_len').width ~= 16); |
---|
| 87 | this_block.setError('Input data type for port "info_len" must have width=16.'); |
---|
| 88 | end |
---|
| 89 | |
---|
| 90 | end % if(inputTypesKnown) |
---|
| 91 | % ----------------------------- |
---|
| 92 | |
---|
| 93 | % ----------------------------- |
---|
| 94 | if (this_block.inputRatesKnown) |
---|
| 95 | setup_as_single_rate(this_block,'clk','ce') |
---|
| 96 | end % if(inputRatesKnown) |
---|
| 97 | % ----------------------------- |
---|
| 98 | |
---|
| 99 | % (!) Set the inout port rate to be the same as the first input |
---|
| 100 | % rate. Change the following code if this is untrue. |
---|
| 101 | uniqueInputRates = unique(this_block.getInputRates); |
---|
| 102 | |
---|
| 103 | |
---|
| 104 | % Add addtional source files as needed. |
---|
| 105 | % |------------- |
---|
| 106 | % | Add files in the order in which they should be compiled. |
---|
| 107 | % | If two files "a.vhd" and "b.vhd" contain the entities |
---|
| 108 | % | entity_a and entity_b, and entity_a contains a |
---|
| 109 | % | component of type entity_b, the correct sequence of |
---|
| 110 | % | addFile() calls would be: |
---|
| 111 | % | this_block.addFile('b.vhd'); |
---|
| 112 | % | this_block.addFile('a.vhd'); |
---|
| 113 | % |------------- |
---|
| 114 | |
---|
| 115 | % this_block.addFile(''); |
---|
| 116 | % this_block.addFile(''); |
---|
| 117 | this_block.addFile('fec_encoder.v'); |
---|
| 118 | |
---|
| 119 | return; |
---|
| 120 | |
---|
| 121 | |
---|
| 122 | % ------------------------------------------------------------ |
---|
| 123 | |
---|
| 124 | function setup_as_single_rate(block,clkname,cename) |
---|
| 125 | inputRates = block.inputRates; |
---|
| 126 | uniqueInputRates = unique(inputRates); |
---|
| 127 | if (length(uniqueInputRates)==1 & uniqueInputRates(1)==Inf) |
---|
| 128 | block.addError('The inputs to this block cannot all be constant.'); |
---|
| 129 | return; |
---|
| 130 | end |
---|
| 131 | if (uniqueInputRates(end) == Inf) |
---|
| 132 | hasConstantInput = true; |
---|
| 133 | uniqueInputRates = uniqueInputRates(1:end-1); |
---|
| 134 | end |
---|
| 135 | if (length(uniqueInputRates) ~= 1) |
---|
| 136 | block.addError('The inputs to this block must run at a single rate.'); |
---|
| 137 | return; |
---|
| 138 | end |
---|
| 139 | theInputRate = uniqueInputRates(1); |
---|
| 140 | for i = 1:block.numSimulinkOutports |
---|
| 141 | block.outport(i).setRate(theInputRate); |
---|
| 142 | end |
---|
| 143 | block.addClkCEPair(clkname,cename,theInputRate); |
---|
| 144 | return; |
---|
| 145 | |
---|
| 146 | % ------------------------------------------------------------ |
---|
| 147 | |
---|