source: ResearchApps/PHY/MIMO_OFDM/ofdm_rx_supermimo_init.m

Last change on this file was 1733, checked in by murphpo, 10 years ago

Updated PHY model with two fec_decoder black boxes and sim mux to select between them for sim/implementation. Also added script for generating simulation-only verilog for fec_decoder. All this is workaround for MATLAB crashing during simulation due to a bug in isim/Sysgen 13.4 that's under investigation by Xilinx.

File size: 8.9 KB
Line 
1%Make sure the Tx init has already been loaded
2ofdm_tx_supermimo_init;
3
4%Do not use 16! Breaks Alamouti Rx timing
5%Symbol_Timing_Offset = 15; %Use for no cyclic shift offset w/ antB preamble enabled, countLoad=229
6
7%Symbol_Timing_Offset = 12; %Use for no cyclic shift offset w/ SISO, antB channel disabled, countLoad=229
8Symbol_Timing_Offset = 10;
9
10PktDet_Delay = 58+32 + ... %UFix7_0 packet detect delay
11    Symbol_Timing_Offset*2^7 + ... %UFix6_0 FFT window offset
12    0*2^16 + ... %UFix5_0 CFO calc delay, in samples
13    (117* 2^24); %UFix8_8 threshold
14%    (round(0.15 * 2^8)* 2^24); %UFix8_8 threshold
15
16pktByteNums =   numHeaderBytes + ...
17                byteIndex_numPayloadBytes(1)*2^8 + ...
18                byteIndex_numPayloadBytes(2)*2^16 + ...
19                byteIndex_simpleDynModMasks * 2^24;
20
21rx_SISO_Mode = tx_SISO_Mode;
22
23pktTiming_controlCounter_bits = 16;
24
25%Structure of packet following detection
26%Short symbols
27pktTiming_ss_num = 6;
28pktTiming_ss_length = length(shortSymbol_time);
29%Long symbols
30pktTiming_ls_num = 2;
31pktTiming_ls_length = length(longSymbol_time);
32%Long symbol cyclic prefix
33pktTiming_lscp_length = 32;
34
35pktTiming_count_ssStart = 0;
36pktTiming_count_lscpStart = (pktTiming_count_ssStart + pktTiming_ss_num*pktTiming_ss_length);
37pktTiming_count_lsStart = (pktTiming_count_lscpStart + pktTiming_lscp_length);
38pktTiming_count_payloadStart = pktTiming_count_lsStart + pktTiming_ls_num*pktTiming_ls_length;
39
40%Packet detection threshold
41pkt_crossCorr_thresh = 0.7;
42pkt_energy_thresh = 0;
43
44rxReg_pktDetCorr = ...
45    2^00 * 90 + ...%(floor(0.7*128)) + ...  %min correlation/power ratio (UFix8_7)
46    2^08 * 5 + ...(300) + ...               %min power (UFix16_8)
47    0;
48
49%In alamouti mode, the Rx syncs to the earlier preamble
50%LongCorrCounterLoad = 229;
51%LongCorrCounterLoad = 232;
52LongCorrCounterLoad = 253-8;%234;
53
54Rx_PktDet_LongCorrThresholds = 8000;
55
56Rx_PktDet_LongCorr_Params = ...
57    2^0  * LongCorrCounterLoad + ...
58    2^8  * 255 + ... %LongCorr CFO capt index
59    2^16 * 0 + ...%90-32 + ... %LongCorr window start
60    2^24 * 255; %180+32; %LongCorr window end
61
62%Interrupt control register has 8 bits:
63%0: Rx Pkt Interrupts Reset
64%1: Rx Header Interrupts Reset
65%2: Tx Done Interrupt Reset
66%3: Rx Good Pkt Interrupt Enable
67%4: Rx Bad Pkt Interrupt Enable
68%5: Rx Good Header Interrupt Enable
69%6: Rx Bad Header Interrupt Enable
70%7: Tx Done Interrupt Enable
71reg_InterruptControl = ...
72    0 + ...  %3 bits [RxPkt, RxHeader, TxDone] interrupt resets
73    0*15 * 2^3 + ... %4 bits[LSB:MSB]=[goodPkt, badPkt, goodHdr, badHdr] interrupt enables
74    0 * 2^7; %1 bit for TxDone enable
75
76%32-bit register holds both pkt buffer offsets (16LSB+8) and interrupt control (8LSB)
77reg_Interrupt_PktBuf_Control = ...
78    reg_InterruptControl + ...
79    1 * 2^16 + ... %6 bits for Tx pkt buff offset
80    0 * 2^24; %6 bits for Rx pkt buff offset
81
82minPilotChanMag = (0.01 * 2^12); %UFix12_12
83reg_PilotCalcParams = (4 * 2^16) + (minPilotChanMag);
84
85regRx_preCFOoptions = ...
86    0 * 2^0 + ... %Use coarse CFO estimate
87    1 * 2^1 + ... %Use pilot CFO estimate
88    0;
89
90regRx_pilotCalcCorrection = round(1.00115 * 2^31);
91regRx_coarseCalcCorrection = round((1.3e-3 - 1.2982e-3)*2^32);
92%Initialization values for the long correlator
93% The correlator only stores the signs of the values in a long trainin symbol
94% This code and the correlator block were designed by Dr. Chris Dick
95
96%Fix2_0 version of longSym
97longCorr_coef_nbits = 3;
98longCorr_coef_bp = 0;
99LTS = fliplr(longSymbol_time./max(abs(longSymbol_time)));
100
101%longCorr_coef_i = [-1*sign(real(fliplr(LTS))) 0];
102%longCorr_coef_q = [sign(imag(fliplr(LTS))) 0];
103
104longCorr_coef_i = [-4*real(LTS) 0];
105longCorr_coef_q = [4*imag(LTS) 0];
106ii = find(longCorr_coef_i < -3.5);
107longCorr_coef_i(ii) = -3;
108ii = find(longCorr_coef_q < -3.5);
109longCorr_coef_q(ii) = -3;
110
111%Shift the correlation pattern by 16 to allow the calculation
112% to finish in time to decide the beginning of the payload
113%L = [longSymbol_time(50:64) longSymbol_time(1:49)];
114L = [longSymbol_time];
115
116ccr = -1*sign(real(fliplr(L)));
117ccr = [ccr 0];
118ii = find(ccr==0);
119ccr(ii)=1;
120
121cci = 1*sign(fliplr(imag(L)));
122cci = [cci 0];
123ii=find(cci==0);
124cci(ii)=1;
125
126ii = find(ccr==-1);
127hr = zeros(1,length(ccr));
128hr(ii) = 1;
129
130ii = find(cci==-1);
131hi = zeros(1,length(cci));
132hi(ii) = 1;
133
134long_cor_acc_n_bits = 6;
135%long_cor_acc_n_bits = 4;
136Tr1 = 1/4;
137
138%Demodulator input precision
139symbol_unmap_bp= 15;
140symbol_unmap_nb= 16;
141
142RxReg_FixedPktLen = 0;%2^32 + 512;
143
144%Popluate the RxControlBits register
145% Each bit has a different function
146%0x1:   1: Reset BER
147%0x2:   2: Require long correlation for pkt detection
148%0x4:   4: Enable dynamic packet lengths
149%0x8:   8: Big sub-pkt buffer mode (16KB max pkt size)
150%0x10:  16: Enable SISO mode
151%0x20:  32: Require 2 long correlations for pkt detection
152%0x40:  64: Require short correlation or ext pkt detection
153%0x80:  128: Record channel estimates
154%0x100: 256: Record channel estimate magnitudes
155%0x200: 512: bypass CFO correction
156%0x400: 1024: Enable coarse CFO estimation
157%0x800: 2048: CFO debug output selection
158%0x1000:4096: Compensate for RF gain in RSSI input
159%0x4000:16384: Bypass division during EQ
160%0x8000:32768: Disable Rx PHY on Tx (not useful for simulation!)
161%0x1_0000:65536: Enable simple dynamic modulation
162%0x2_0000:131072: Enable switching diversity
163%0x4_0000:262144: Use antenna B in SISO mode
164%0x8_0000:524288: Enable Rx reset on bad header CRC
165%0x10_0000: 1048576: Enable Rx Alamouti mode
166%0x20_0000: 2097152: Enable flexBER mode
167%0x40_0000: 4194304: Ignore headers for BER
168%0x80_0000: 8388608: Per-packet BER reset
169%0x100_0000: 16777216: Force-enable radio RxEn
170%0x200_0000: 33554432: SaveAF waveform
171%0x400_0000: Reset autoResponse flagA
172%0x800_0000: Reset autoResponse flagB
173%0x2000_0000: 536870912: Enable channel magnitude masking (only useful in Alamouti mode)
174%0x8000_0000: 2147483648: Global Rx reset
175
176rx_controlBits = 1 * 2 ... %Long correlation
177         + 1 * 4 ... %Dyn pkt lengths
178         + 0 * 8 ... %1=big sub-pkt buffers
179         + 1 * 16 * rx_SISO_Mode ...
180         + 1 * 32 ... %2 long correlations
181         + 1 * 64 ... %short correlation
182         + 1 * 128 ... %record channel estimates
183         + 1 * 256 ... %record channel estimate mags
184         + 0 * 512 ... %bypass CFO%%%%%%%%%%%%
185         + 1 * 1024 ... %1=Enable coarse CFO estimation
186         + 1 * 4096 ... %Compensate for RFgain in RSSI input
187         + 0 * 16384 ... %1=Bypass EQ division
188         + 0 * 32768 ... %0=Don't disable Rx during Tx
189         + 1 * 65536 ... %1=Use simple dynamic modulation
190         + 0 * 131072 ... %1=Use switching diversity in SISO mode
191         + 0 * 262144 ... %1=force AntB in SISO mode
192         + 1 * 524288 ... %1=Reset Rx on bad header
193         + 1 * 1048576 * tx_Alamouti_Mode ...
194         + 0 * 2097152 ... %1=flex BER mode
195         + 1 * 33554432 ... %1=Save AF waveform
196         + 0 * 4194304 ... %1=ignore headers (and header-only packets) for BER calculation
197         + 0 * 8388608 ... %1=Per-packet BER reset
198         + 0 * 16777216 ... %Don't force RxEn in simulation (used in hardware though)
199         + 1 * 536870912 * tx_Alamouti_Mode ... %Enables chan mag checking/masking
200         + 0 * 2147483648; %Global Rx reset
201     
202     
203%Min chan est magnitudes (Two UFix16_15 values, re-interpreted as UFix16_0)
204regRx_chanEst_minMag = ((0.5)*2^15) + ((0.5 * 2^15)*2^16);
205
206%Pkt detector control register
207pktDet_controlBits = 0 * 2^0 ... %Pkt det master reset
208    + 0 * 2^1 ... %Ignore all pktDet events
209    + 0 * 2^2 ... %Clock divider for RSSI ADC
210    + 1 * 2^3 ... %Enable the CSMA IDLEFORDIFS output
211    + 1 * 2^4 ... %Pkt det mode (1=antA OR antB, 0=antA AND antB)
212    + 1 * 2^5 ... %Accept pkt det events on antA
213    + 1 * 2^6 ... %Accept pkt det events on antB
214    + 0 * 2^7 ... %Enable the external pkt det input
215    + 0 * 2^8 ... %Enable the RSSI/energy-threshold detector
216    + 1 * 2^9 ... %Enable the auto-correlation detector
217    + 0;
218
219%Post-equalization scaling
220%This value is used to scale the equalizer's output before demodulation
221%This is used to correct for any fixed gain/attenuation the full system has
222% The value shouldn't be channel or modulation dependent
223% It does depend on the number of training symbols (1/training)
224if(tx_SISO_Mode)
225    rxScaling = 2;
226else
227    rxScaling = 1;
228end
229
230%AF scaling; UFix18_12
231reg_AF_Tx_Scaling = 2944;%2 * 2^12;
232
233reg_AF_Tx_Blanking = (320+80) + ( (320+80+79)*2^16);
234
235% This scaling value resides in a UFix_32_0 register
236%  The value is split into two 16 bit values, then
237%   each is re-interpreted as a UFix_16_11
238rx_postEq_scaling = round(rxScaling*2^11) * (1 + 2^16);
239%mod((rxScaling*2^11),2^16) + (2^16 * mod((rxScaling*2^11),2^16));
240
241%Load Chipscope capture data
242AntA_ADC_I = 0;AntA_ADC_Q = 0; csInterp = 1; t_start = 1; t_stop = 1;%2260;
243%xlLoadChipScopeData('chipscope_captures\PHY_c_badHdr_0.prn'); csInterp = 2; t_start = 1;
244
245rxAntI.time = [];
246rxAntQ.time = [];
247rxAntI.signals.values = AntA_ADC_I(t_start:csInterp:end);
248rxAntQ.signals.values = AntA_ADC_Q(t_start:csInterp:end);
249if(length(AntA_ADC_I) > 1)
250    simOnly_simLength = 1000 + 4*(length(AntA_ADC_I) - t_start);
251end
252
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