[4443] | 1 | |
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| 2 | |
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| 3 | %xlLoadChipScopeData('../wlan_phy_rx/cs_capt/wlan_cs_capt_5.prn'); cs_interp = 1; cs_start = 1; |
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| 4 | %payload_vec = [zeros(25,1); complex(ADC_I(cs_start:cs_interp:end), ADC_Q(cs_start:cs_interp:end));]; |
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| 5 | payload_vec = 0; |
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| 6 | raw_rx_I.time = []; |
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| 7 | raw_rx_Q.time = []; |
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| 8 | |
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| 9 | DCO_I = 0.05; |
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| 10 | DCO_Q = 0; |
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| 11 | G_I = 2; |
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| 12 | G_Q = 2; |
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| 13 | |
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| 14 | raw_rx_I.signals.values = DCO_I + G_I*real(payload_vec); |
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| 15 | raw_rx_Q.signals.values = DCO_Q + G_Q*imag(payload_vec); |
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| 16 | |
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| 17 | |
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| 18 | PHY_CONFIG_PKT_DET_CORR_THRESH = 90; |
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| 19 | PHY_CONFIG_PKT_DET_ENERGY_THRESH = 14; |
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| 20 | PHY_CONFIG_PKT_DET_MIN_DURR = 4; |
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| 21 | |
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| 22 | %% Register Init |
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| 23 | ACG_OVERRIDE = 0; |
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| 24 | |
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| 25 | |
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| 26 | % Timing registers |
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| 27 | AGC_TIMING_CAPT_RSSI_1 = 8; |
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| 28 | AGC_TIMING_CAPT_RSSI_2 = 24; |
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| 29 | AGC_TIMING_CAPT_V_DB = 48; |
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| 30 | AGC_TIMING_START_DCO = 60; |
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| 31 | |
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| 32 | AGC_TIMING_EN_IIR_FILT = 93; |
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| 33 | AGC_TIMING_DONE = 95; |
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| 34 | |
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| 35 | AGC_TIMING_RESET_RXHP = 0; |
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| 36 | AGC_TIMING_RESET_G_RF = 30; |
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| 37 | AGC_TIMING_RESET_G_BB = 25; |
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| 38 | |
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| 39 | % Config register |
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| 40 | AGC_G_RF_THRESH_32 = 256-52; % Reinterpret Fix8_0 to UFix8_0 |
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| 41 | AGC_G_RF_THRESH_21 = 256-40; % Reinterpret Fix8_0 to UFix8_0 |
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| 42 | AGC_RSSI_AVG_LEN_SEL = 0; |
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| 43 | AGC_V_DB_ADJ = 64-13; % Reinterpret Fix6_0 to UFix6_0 |
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| 44 | AGC_INIT_G_BB = 24; |
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| 45 | |
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| 46 | % Reset registers |
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| 47 | AGC_RESET_TIMEOUT_INIT = hex2dec('7FFFFFFF'); |
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| 48 | |
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| 49 | % Target register |
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| 50 | AGC_TARGET_PWR = 64-15; % Reinterpret Fix6_0 to UFix6_0 |
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| 51 | |
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| 52 | % IIR filt coefficients |
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| 53 | DCO_IIR_Coef_A1 = -0.98751192990731429; |
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| 54 | DCO_IIR_Coef_B0 = 0.99375596495365714; |
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| 55 | |
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| 56 | % Rx Power - RSSI calib register (-power values in dBm) |
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| 57 | RSSI_MIN_PWR_G_RF_3 = 100; |
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| 58 | RSSI_MIN_PWR_G_RF_2 = 85; |
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| 59 | RSSI_MIN_PWR_G_RF_1 = 70; |
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| 60 | |
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| 61 | REG_AGC_Timing_AGC = ... |
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| 62 | 2^0 * AGC_TIMING_CAPT_RSSI_1 + ... % UFix8_0 |
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| 63 | 2^8 * AGC_TIMING_CAPT_RSSI_2 + ... % UFix8_0 |
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| 64 | 2^16 * AGC_TIMING_CAPT_V_DB + ... % UFix8_0 |
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| 65 | 2^24 * AGC_TIMING_DONE; % UFix8_0 |
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| 66 | |
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| 67 | REG_AGC_Timing_DCO = ... |
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| 68 | 2^0 * AGC_TIMING_START_DCO + ... % UFix8_0 |
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| 69 | 2^8 * AGC_TIMING_EN_IIR_FILT + ... % UFix8_0 |
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| 70 | 0; |
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| 71 | |
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| 72 | REG_AGC_Timing_Reset = ... |
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| 73 | 2^0 * AGC_TIMING_RESET_RXHP + ... % UFix8_0 |
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| 74 | 2^8 * AGC_TIMING_RESET_G_RF + ... % UFix8_0 |
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| 75 | 2^16 * AGC_TIMING_RESET_G_BB + ... % UFix8_0 |
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| 76 | 0; |
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| 77 | |
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| 78 | REG_AGC_Config = ... |
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| 79 | 2^0 * AGC_G_RF_THRESH_32 + ... % Fix8_0 |
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| 80 | 2^8 * AGC_G_RF_THRESH_21 + ... % Fix8_0 |
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| 81 | 2^16 * AGC_RSSI_AVG_LEN_SEL + ... % UFix2_0 |
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| 82 | 2^18 * AGC_V_DB_ADJ + ... % Fix6_0 |
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| 83 | 2^24 * AGC_INIT_G_BB + ... % UFix5_0 |
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| 84 | 0; |
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| 85 | |
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| 86 | REG_AGC_Target = AGC_TARGET_PWR; |
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| 87 | |
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| 88 | REG_AGC_IIR_Coef_A1 = DCO_IIR_Coef_A1; |
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| 89 | REG_AGC_IIR_Coef_B0 = DCO_IIR_Coef_B0; |
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| 90 | |
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| 91 | REG_AGC_RSSI_RX_PWR_CALIB = ... |
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| 92 | 2^0 * RSSI_MIN_PWR_G_RF_3 + ... % UFix8_0 |
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| 93 | 2^8 * RSSI_MIN_PWR_G_RF_2 + ... % UFix8_0 |
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| 94 | 2^16 * RSSI_MIN_PWR_G_RF_1 + ... % UFix8_0 |
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| 95 | 0; |
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| 96 | |
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| 97 | |
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