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1 | README |
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2 | |
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3 | This WARPLab Buffers core was taken from the WARP v3 WARPLab 7.5.0 release. This is straight |
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4 | copy of the w3 Buffers core, renamed for the WARP v2 hardware, except for the following modifications: |
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5 | |
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6 | - Updated Model properties to reference w2_warplab_buffers_init.m |
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7 | - Updated EDK processor block to use PLB bus |
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8 | - Modified buffers interface block to use internal 32-bit memories vs external 128-bit memories |
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9 | - Updated bus definitions to remove external memories |
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10 | - Updated ADC inputs to be Fix_14_13 vs Fix_12_11 |
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11 | - Updated DAC outputs to be Fix_16_15 vs Fix_12_11 |
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12 | - Updated Config register to reserve *_WORD_ORDER |
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14 | NOTE: Logic exists in this core to support the same extended buffer addressing. However, the MPD has |
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15 | not been modified to declare the ports as interrupts and the interrupt ports have not been connected |
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16 | to the processor. Therefore, the Tx / Rx length should never be set greater than the supported |
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17 | number of samples (2^14 for WARPLab 7.5.1) and the Tx / Rx IQ Thesholds should be set to the supported |
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18 | number of samples (2^14 for WARPLab 7.5.1). |
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20 | |
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