1 | |
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2 | /******************************************************************* |
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3 | * |
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4 | * CAUTION: This file is automatically generated by libgen. |
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5 | * Version: Xilinx EDK 14.4 EDK_P.49d |
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6 | * DO NOT EDIT. |
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7 | * |
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8 | * Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved. |
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9 | |
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10 | * |
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11 | * Description: XilNet MAC Configuration File |
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12 | * |
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13 | *******************************************************************/ |
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14 | |
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15 | #include <string.h> |
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16 | #include <xilnet_config.h> |
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17 | |
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18 | // TODO: FIX TEMAC for WARP V2 |
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19 | #ifdef _CONFIG_TEMAC_ |
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20 | #include "xlltemac.h" |
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21 | #include "xllfifo.h" |
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22 | #include "xdmacentral.h" |
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23 | #include "xdmacentral_l.h" |
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24 | #endif |
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25 | |
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26 | |
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27 | |
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28 | // Variables for ETH 0 |
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29 | |
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30 | XLlFifo ETH_0_FIFO_Instance; |
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31 | |
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32 | #if 0 |
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33 | XAxiDma ETH_0_DMA_Instance; |
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34 | |
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35 | // Aligned memory segments to be used for buffer descriptors |
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36 | char ETH_0_RX_BD_space[XILNET_ETH_0_RXBD_SPACE_BYTES] __attribute__ ((aligned(XILNET_BD_ALIGNMENT))); |
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37 | char ETH_0_TX_BD_space[XILNET_ETH_0_RXBD_SPACE_BYTES] __attribute__ ((aligned(XILNET_BD_ALIGNMENT))); |
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38 | #endif |
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39 | |
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40 | |
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41 | // Variables for ETH 1 |
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42 | #if 0 |
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43 | XLlFifo ETH_1_FIFO_Instance; |
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44 | #endif |
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45 | |
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46 | XAxiDma ETH_1_DMA_Instance; |
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47 | |
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48 | // Aligned memory segments to be used for buffer descriptors |
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49 | char ETH_1_RX_BD_space[XILNET_ETH_1_RXBD_SPACE_BYTES] __attribute__ ((aligned(XILNET_BD_ALIGNMENT))); |
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50 | char ETH_1_TX_BD_space[XILNET_ETH_1_TXBD_SPACE_BYTES] __attribute__ ((aligned(XILNET_BD_ALIGNMENT))); |
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51 | |
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52 | |
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53 | |
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54 | // Ethernet Buffers |
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55 | |
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56 | // Buffers for ETH 0 |
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57 | unsigned int recvBuffer_eth_0[XILNET_ETH_0_NUM_RECV_BUF*((XILNET_ETH_0_BUF_SIZE+3)/4)]; |
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58 | unsigned int sendBuffer_eth_0[(XILNET_ETH_0_BUF_SIZE+3)/4]; |
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59 | struct xilsock_socket xilsock_sockets_eth_0[NO_OF_XILSOCKS]; |
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60 | struct xilnet_udp_conn xilnet_udp_conns_eth_0[XILNET_MAX_UDP_CONNS]; |
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61 | |
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62 | // Buffers for ETH 1 |
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63 | unsigned int recvBuffer_eth_1[XILNET_ETH_1_NUM_RECV_BUF*((XILNET_ETH_1_BUF_SIZE+3)/4)]; |
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64 | unsigned int sendBuffer_eth_1[(XILNET_ETH_1_BUF_SIZE+3)/4]; |
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65 | struct xilsock_socket xilsock_sockets_eth_1[NO_OF_XILSOCKS]; |
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66 | struct xilnet_udp_conn xilnet_udp_conns_eth_1[XILNET_MAX_UDP_CONNS]; |
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67 | |
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68 | |
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69 | |
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70 | // Ethernet Device Structure |
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71 | xilnet_eth_device eth_device[XILNET_NUM_ETH_DEVICES]; |
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72 | |
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73 | |
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74 | void xilnet_init_eth_device_struct(unsigned int eth_dev_num) { |
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75 | |
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76 | switch( eth_dev_num ) { |
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77 | case XILNET_ETH_0: |
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78 | eth_device[eth_dev_num].inf_type = XILNET_AXI_FIFO_INF; |
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79 | eth_device[eth_dev_num].inf_id = XILNET_ETH_0_INF_DEVICE_ID; |
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80 | eth_device[eth_dev_num].inf_ref = Ð_0_FIFO_Instance; |
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81 | eth_device[eth_dev_num].inf_cfg_ref = 0; |
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82 | eth_device[eth_dev_num].dma_rx_ring_ref = 0; |
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83 | eth_device[eth_dev_num].dma_tx_ring_ref = 0; |
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84 | eth_device[eth_dev_num].dma_rx_bd_ref = 0; |
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85 | eth_device[eth_dev_num].dma_tx_bd_ref = 0; |
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86 | eth_device[eth_dev_num].dma_rx_bd_cnt = 0; |
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87 | eth_device[eth_dev_num].dma_tx_bd_cnt = 0; |
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88 | eth_device[eth_dev_num].xilsock_status_flag = 0; |
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89 | eth_device[eth_dev_num].sync_IP_octet = 255; |
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90 | eth_device[eth_dev_num].is_xilsock_init = 0; |
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91 | eth_device[eth_dev_num].xilsock_sockets = &xilsock_sockets_eth_0; |
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92 | eth_device[eth_dev_num].is_udp_init = 0; |
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93 | eth_device[eth_dev_num].xilnet_udp_conns = &xilnet_udp_conns_eth_0; |
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94 | eth_device[eth_dev_num].buf_size = XILNET_ETH_0_BUF_SIZE; |
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95 | eth_device[eth_dev_num].num_recvbuf = XILNET_ETH_0_NUM_RECV_BUF; |
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96 | eth_device[eth_dev_num].recvbuf = (unsigned int *)&recvBuffer_eth_0; |
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97 | eth_device[eth_dev_num].sendbuf = (unsigned int *)&sendBuffer_eth_0; |
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98 | break; |
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99 | case XILNET_ETH_1: |
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100 | eth_device[eth_dev_num].inf_type = XILNET_AXI_DMA_INF; |
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101 | eth_device[eth_dev_num].inf_id = XILNET_ETH_1_INF_DEVICE_ID; |
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102 | eth_device[eth_dev_num].inf_ref = Ð_1_DMA_Instance; |
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103 | eth_device[eth_dev_num].inf_cfg_ref = 0; |
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104 | eth_device[eth_dev_num].dma_rx_ring_ref = 0; |
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105 | eth_device[eth_dev_num].dma_tx_ring_ref = 0; |
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106 | eth_device[eth_dev_num].dma_rx_bd_ref = Ð_1_RX_BD_space; |
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107 | eth_device[eth_dev_num].dma_tx_bd_ref = Ð_1_TX_BD_space; |
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108 | eth_device[eth_dev_num].dma_rx_bd_cnt = XILNET_ETH_1_RXBD_CNT; |
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109 | eth_device[eth_dev_num].dma_tx_bd_cnt = XILNET_ETH_1_TXBD_CNT; |
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110 | eth_device[eth_dev_num].xilsock_status_flag = 0; |
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111 | eth_device[eth_dev_num].sync_IP_octet = 255; |
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112 | eth_device[eth_dev_num].is_xilsock_init = 0; |
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113 | eth_device[eth_dev_num].xilsock_sockets = &xilsock_sockets_eth_1; |
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114 | eth_device[eth_dev_num].is_udp_init = 0; |
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115 | eth_device[eth_dev_num].xilnet_udp_conns = &xilnet_udp_conns_eth_1; |
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116 | eth_device[eth_dev_num].buf_size = XILNET_ETH_1_BUF_SIZE; |
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117 | eth_device[eth_dev_num].num_recvbuf = XILNET_ETH_1_NUM_RECV_BUF; |
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118 | eth_device[eth_dev_num].recvbuf = (unsigned int *)&recvBuffer_eth_1; |
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119 | eth_device[eth_dev_num].sendbuf = (unsigned int *)&sendBuffer_eth_1; |
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120 | break; |
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121 | default: |
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122 | xil_printf(" **** ERROR: Trying to initialize Ethernet device %d. Only %d configured in the HW.", (eth_dev_num+1), XILNET_NUM_ETH_DEVICES); |
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123 | break; |
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124 | } |
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125 | } |
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126 | |
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127 | |
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128 | |
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129 | #ifdef __cplusplus |
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130 | } |
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131 | #endif |
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132 | |
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133 | |
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134 | |
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