Model { Name "wlan_phy_rx_pmd" Version 7.8 MdlSubVersion 0 GraphicalInterface { NumRootInports 0 NumRootOutports 0 ParameterArgumentNames "" ComputedModelVersion "1.994" NumModelReferences 0 NumTestPointedSignals 0 } SavedCharacterEncoding "windows-1252" PostLoadFcn "wlan_phy_rx_init" SaveDefaultBlockParams on ScopeRefreshTime 0.035000 OverrideScopeRefreshTime on DisableAllScopes off DataTypeOverride "UseLocalSettings" DataTypeOverrideAppliesTo "AllNumericTypes" MinMaxOverflowLogging "UseLocalSettings" MinMaxOverflowArchiveMode "Overwrite" FPTRunName "Run 1" MaxMDLFileLineLength 120 InitFcn "wlan_phy_rx_init" StartFcn "wlan_phy_rx_init" Created "Fri Jan 15 15:32:18 2016" Creator "murphpo" UpdateHistory "UpdateHistoryNever" ModifiedByFormat "%" LastModifiedBy "murphpo" ModifiedDateFormat "%" LastModifiedDate "Wed Feb 26 16:21:49 2020" RTWModifiedTimeStamp 504634358 ModelVersionFormat "1.%" ConfigurationManager "None" SampleTimeColors off SampleTimeAnnotations off LibraryLinkDisplay "disabled" WideLines off ShowLineDimensions off ShowPortDataTypes on ShowDesignRanges off ShowLoopsOnError on IgnoreBidirectionalLines off ShowStorageClass off ShowTestPointIcons on ShowSignalResolutionIcons on ShowViewerIcons on SortedOrder off ExecutionContextIcon off ShowLinearizationAnnotations on BlockNameDataTip off BlockParametersDataTip off BlockDescriptionStringDataTip off ToolBar on StatusBar on BrowserShowLibraryLinks off BrowserLookUnderMasks off SimulationMode "normal" LinearizationMsg "none" Profile off ParamWorkspaceSource "MATLABWorkspace" AccelSystemTargetFile "accel.tlc" AccelTemplateMakefile "accel_default_tmf" AccelMakeCommand "make_rtw" TryForcingSFcnDF off Object { $PropName "DataLoggingOverride" $ObjectID 1 $ClassName "Simulink.SimulationData.ModelLoggingInfo" model_ "wlan_phy_rx_pmd" overrideMode_ [0.0] Array { Type "Cell" Dimension 1 Cell "wlan_phy_rx_pmd" PropName "logAsSpecifiedByModels_" } Array { Type "Cell" Dimension 1 Cell [] PropName "logAsSpecifiedByModelsSSIDs_" } } RecordCoverage off CovPath "/" CovSaveName "covdata" CovMetricSettings "dw" CovNameIncrementing off CovHtmlReporting on CovForceBlockReductionOff on covSaveCumulativeToWorkspaceVar on CovSaveSingleToWorkspaceVar on CovCumulativeVarName "covCumulativeData" CovCumulativeReport off CovReportOnPause on CovModelRefEnable "Off" CovExternalEMLEnable off ExtModeBatchMode off ExtModeEnableFloating on ExtModeTrigType "manual" ExtModeTrigMode "normal" ExtModeTrigPort "1" ExtModeTrigElement "any" ExtModeTrigDuration 1000 ExtModeTrigDurationFloating "auto" ExtModeTrigHoldOff 0 ExtModeTrigDelay 0 ExtModeTrigDirection "rising" ExtModeTrigLevel 0 ExtModeArchiveMode "off" ExtModeAutoIncOneShot off ExtModeIncDirWhenArm off ExtModeAddSuffixToVar off ExtModeWriteAllDataToWs off ExtModeArmWhenConnect on ExtModeSkipDownloadWhenConnect off ExtModeLogAll on ExtModeAutoUpdateStatusClock on BufferReuse on ShowModelReferenceBlockVersion off ShowModelReferenceBlockIO off Array { Type "Handle" Dimension 1 Simulink.ConfigSet { $ObjectID 2 Version "1.11.1" Array { Type "Handle" Dimension 8 Simulink.SolverCC { $ObjectID 3 Version "1.11.1" StartTime "0.0" StopTime "rx_sim.sim_time" AbsTol "auto" FixedStep "auto" InitialStep "auto" MaxNumMinSteps "-1" MaxOrder 5 ZcThreshold "auto" ConsecutiveZCsStepRelTol "10*128*eps" MaxConsecutiveZCs "1000" ExtrapolationOrder 4 NumberNewtonIterations 1 MaxStep "auto" MinStep "auto" MaxConsecutiveMinStep "1" RelTol "1e-3" SolverMode "SingleTasking" ConcurrentTasks off Solver "VariableStepDiscrete" SolverName "VariableStepDiscrete" SolverJacobianMethodControl "auto" ShapePreserveControl "DisableAll" ZeroCrossControl "UseLocalSettings" ZeroCrossAlgorithm "Nonadaptive" AlgebraicLoopSolver "TrustRegion" SolverResetMethod "Fast" PositivePriorityOrder off AutoInsertRateTranBlk off SampleTimeConstraint "Unconstrained" InsertRTBMode "Whenever possible" } Simulink.DataIOCC { $ObjectID 4 Version "1.11.1" Decimation "1" ExternalInput "[t, u]" FinalStateName "xFinal" InitialState "xInitial" LimitDataPoints on MaxDataPoints "1000" LoadExternalInput off LoadInitialState off SaveFinalState off SaveCompleteFinalSimState off SaveFormat "Array" SignalLoggingSaveFormat "ModelDataLogs" SaveOutput on SaveState off SignalLogging on DSMLogging on InspectSignalLogs off SaveTime on ReturnWorkspaceOutputs off StateSaveName "xout" TimeSaveName "tout" OutputSaveName "yout" SignalLoggingName "logsout" DSMLoggingName "dsmout" OutputOption "RefineOutputTimes" OutputTimes "[]" ReturnWorkspaceOutputsName "out" Refine "1" } Simulink.OptimizationCC { $ObjectID 5 Version "1.11.1" Array { Type "Cell" Dimension 8 Cell "BooleansAsBitfields" Cell "PassReuseOutputArgsAs" Cell "PassReuseOutputArgsThreshold" Cell "ZeroExternalMemoryAtStartup" Cell "ZeroInternalMemoryAtStartup" Cell "OptimizeModelRefInitCode" Cell "NoFixptDivByZeroProtection" Cell "UseSpecifiedMinMax" PropName "DisabledProps" } BlockReduction on BooleanDataType on ConditionallyExecuteInputs on InlineParams on UseIntDivNetSlope off UseFloatMulNetSlope off UseSpecifiedMinMax off InlineInvariantSignals off OptimizeBlockIOStorage on BufferReuse on EnhancedBackFolding off StrengthReduction off ExpressionFolding on BooleansAsBitfields off BitfieldContainerType "uint_T" EnableMemcpy on MemcpyThreshold 64 PassReuseOutputArgsAs "Structure reference" ExpressionDepthLimit 2147483647 FoldNonRolledExpr on LocalBlockOutputs on RollThreshold 5 SystemCodeInlineAuto off StateBitsets off DataBitsets off UseTempVars off ZeroExternalMemoryAtStartup on ZeroInternalMemoryAtStartup on InitFltsAndDblsToZero off NoFixptDivByZeroProtection off EfficientFloat2IntCast off EfficientMapNaN2IntZero on OptimizeModelRefInitCode off LifeSpan "inf" MaxStackSize "Inherit from target" BufferReusableBoundary on SimCompilerOptimization "Off" AccelVerboseBuild off AccelParallelForEachSubsystem on } Simulink.DebuggingCC { $ObjectID 6 Version "1.11.1" RTPrefix "error" ConsistencyChecking "none" ArrayBoundsChecking "none" SignalInfNanChecking "none" SignalRangeChecking "none" ReadBeforeWriteMsg "UseLocalSettings" WriteAfterWriteMsg "UseLocalSettings" WriteAfterReadMsg "UseLocalSettings" AlgebraicLoopMsg "warning" ArtificialAlgebraicLoopMsg "warning" SaveWithDisabledLinksMsg "warning" SaveWithParameterizedLinksMsg "warning" CheckSSInitialOutputMsg on UnderspecifiedInitializationDetection "Classic" MergeDetectMultiDrivingBlocksExec "none" CheckExecutionContextPreStartOutputMsg off CheckExecutionContextRuntimeOutputMsg off SignalResolutionControl "UseLocalSettings" BlockPriorityViolationMsg "warning" MinStepSizeMsg "warning" TimeAdjustmentMsg "none" MaxConsecutiveZCsMsg "error" MaskedZcDiagnostic "warning" IgnoredZcDiagnostic "warning" SolverPrmCheckMsg "warning" InheritedTsInSrcMsg "warning" DiscreteInheritContinuousMsg "warning" MultiTaskDSMMsg "error" MultiTaskCondExecSysMsg "error" MultiTaskRateTransMsg "error" SingleTaskRateTransMsg "none" TasksWithSamePriorityMsg "warning" SigSpecEnsureSampleTimeMsg "warning" CheckMatrixSingularityMsg "none" IntegerOverflowMsg "warning" Int32ToFloatConvMsg "warning" ParameterDowncastMsg "error" ParameterOverflowMsg "error" ParameterUnderflowMsg "none" ParameterPrecisionLossMsg "warning" ParameterTunabilityLossMsg "warning" FixptConstUnderflowMsg "none" FixptConstOverflowMsg "none" FixptConstPrecisionLossMsg "none" UnderSpecifiedDataTypeMsg "none" UnnecessaryDatatypeConvMsg "none" VectorMatrixConversionMsg "none" InvalidFcnCallConnMsg "error" FcnCallInpInsideContextMsg "Enable All" SignalLabelMismatchMsg "none" UnconnectedInputMsg "none" UnconnectedOutputMsg "none" UnconnectedLineMsg "none" SFcnCompatibilityMsg "none" FrameProcessingCompatibilityMsg "warning" UniqueDataStoreMsg "none" BusObjectLabelMismatch "warning" RootOutportRequireBusObject "warning" AssertControl "UseLocalSettings" EnableOverflowDetection off ModelReferenceIOMsg "none" ModelReferenceMultiInstanceNormalModeStructChecksumCheck "error" ModelReferenceVersionMismatchMessage "none" ModelReferenceIOMismatchMessage "none" ModelReferenceCSMismatchMessage "none" UnknownTsInhSupMsg "warning" ModelReferenceDataLoggingMessage "warning" ModelReferenceSymbolNameMessage "warning" ModelReferenceExtraNoncontSigs "error" StateNameClashWarn "warning" SimStateInterfaceChecksumMismatchMsg "warning" SimStateOlderReleaseMsg "error" InitInArrayFormatMsg "warning" StrictBusMsg "ErrorLevel1" BusNameAdapt "WarnAndRepair" NonBusSignalsTreatedAsBus "none" LoggingUnavailableSignals "error" BlockIODiagnostic "none" SFUnusedDataAndEventsDiag "warning" SFUnexpectedBacktrackingDiag "warning" SFInvalidInputDataAccessInChartInitDiag "warning" SFNoUnconditionalDefaultTransitionDiag "warning" SFTransitionOutsideNaturalParentDiag "warning" SFUnconditionalTransitionShadowingDiag "warning" } Simulink.HardwareCC { $ObjectID 7 Version "1.11.1" ProdBitPerChar 8 ProdBitPerShort 16 ProdBitPerInt 32 ProdBitPerLong 32 ProdBitPerFloat 32 ProdBitPerDouble 64 ProdBitPerPointer 32 ProdLargestAtomicInteger "Char" ProdLargestAtomicFloat "None" ProdIntDivRoundTo "Undefined" ProdEndianess "Unspecified" ProdWordSize 32 ProdShiftRightIntArith on ProdHWDeviceType "32-bit Generic" TargetBitPerChar 8 TargetBitPerShort 16 TargetBitPerInt 32 TargetBitPerLong 32 TargetBitPerFloat 32 TargetBitPerDouble 64 TargetBitPerPointer 32 TargetLargestAtomicInteger "Char" TargetLargestAtomicFloat "None" TargetShiftRightIntArith on TargetIntDivRoundTo "Undefined" TargetEndianess "Unspecified" TargetWordSize 32 TargetTypeEmulationWarnSuppressLevel 0 TargetPreprocMaxBitsSint 32 TargetPreprocMaxBitsUint 32 TargetHWDeviceType "Specified" TargetUnknown off ProdEqTarget on } Simulink.ModelReferenceCC { $ObjectID 8 Version "1.11.1" UpdateModelReferenceTargets "IfOutOfDateOrStructuralChange" CheckModelReferenceTargetMessage "error" EnableParallelModelReferenceBuilds off ParallelModelReferenceErrorOnInvalidPool on ParallelModelReferenceMATLABWorkerInit "None" ModelReferenceNumInstancesAllowed "Multi" PropagateVarSize "Infer from blocks in model" ModelReferencePassRootInputsByReference on ModelReferenceMinAlgLoopOccurrences off PropagateSignalLabelsOutOfModel off SupportModelReferenceSimTargetCustomCode off } Simulink.SFSimCC { $ObjectID 9 Version "1.11.1" SFSimEnableDebug on SFSimOverflowDetection on SFSimEcho on SimBlas on SimCtrlC on SimExtrinsic on SimIntegrity on SimUseLocalCustomCode off SimParseCustomCode on SimBuildMode "sf_incremental_build" } Simulink.RTWCC { $BackupClass "Simulink.RTWCC" $ObjectID 10 Version "1.11.1" Array { Type "Cell" Dimension 8 Cell "IncludeHyperlinkInReport" Cell "GenerateTraceInfo" Cell "GenerateTraceReport" Cell "GenerateTraceReportSl" Cell "GenerateTraceReportSf" Cell "GenerateTraceReportEml" Cell "GenerateSLWebview" Cell "GenerateCodeMetricsReport" PropName "DisabledProps" } SystemTargetFile "grt.tlc" GenCodeOnly off MakeCommand "make_rtw" GenerateMakefile on TemplateMakefile "grt_default_tmf" GenerateReport off SaveLog off RTWVerbose on RetainRTWFile off ProfileTLC off TLCDebug off TLCCoverage off TLCAssert off ProcessScriptMode "Default" ConfigurationMode "Optimized" ConfigAtBuild off RTWUseLocalCustomCode off RTWUseSimCustomCode off IncludeHyperlinkInReport off LaunchReport off TargetLang "C" IncludeBusHierarchyInRTWFileBlockHierarchyMap off IncludeERTFirstTime off GenerateTraceInfo off GenerateTraceReport off GenerateTraceReportSl off GenerateTraceReportSf off GenerateTraceReportEml off GenerateCodeInfo off GenerateSLWebview off GenerateCodeMetricsReport off RTWCompilerOptimization "Off" CheckMdlBeforeBuild "Off" CustomRebuildMode "OnUpdate" Array { Type "Handle" Dimension 2 Simulink.CodeAppCC { $ObjectID 11 Version "1.11.1" Array { Type "Cell" Dimension 21 Cell "IgnoreCustomStorageClasses" Cell "IgnoreTestpoints" Cell "InsertBlockDesc" Cell "InsertPolySpaceComments" Cell "SFDataObjDesc" Cell "MATLABFcnDesc" Cell "SimulinkDataObjDesc" Cell "DefineNamingRule" Cell "SignalNamingRule" Cell "ParamNamingRule" Cell "InlinedPrmAccess" Cell "CustomSymbolStr" Cell "CustomSymbolStrGlobalVar" Cell "CustomSymbolStrType" Cell "CustomSymbolStrField" Cell "CustomSymbolStrFcn" Cell "CustomSymbolStrFcnArg" Cell "CustomSymbolStrBlkIO" Cell "CustomSymbolStrTmpVar" Cell "CustomSymbolStrMacro" Cell "ReqsInCode" PropName "DisabledProps" } ForceParamTrailComments off GenerateComments on IgnoreCustomStorageClasses on IgnoreTestpoints off IncHierarchyInIds off MaxIdLength 31 PreserveName off PreserveNameWithParent off ShowEliminatedStatement off IncAutoGenComments off SimulinkDataObjDesc off SFDataObjDesc off MATLABFcnDesc off IncDataTypeInIds off MangleLength 1 CustomSymbolStrGlobalVar "$R$N$M" CustomSymbolStrType "$N$R$M" CustomSymbolStrField "$N$M" CustomSymbolStrFcn "$R$N$M$F" CustomSymbolStrFcnArg "rt$I$N$M" CustomSymbolStrBlkIO "rtb_$N$M" CustomSymbolStrTmpVar "$N$M" CustomSymbolStrMacro "$R$N$M" DefineNamingRule "None" ParamNamingRule "None" SignalNamingRule "None" InsertBlockDesc off InsertPolySpaceComments off SimulinkBlockComments on MATLABSourceComments off EnableCustomComments off InlinedPrmAccess "Literals" ReqsInCode off UseSimReservedNames off } Simulink.GRTTargetCC { $BackupClass "Simulink.TargetCC" $ObjectID 12 Version "1.11.1" Array { Type "Cell" Dimension 16 Cell "GeneratePreprocessorConditionals" Cell "IncludeMdlTerminateFcn" Cell "CombineOutputUpdateFcns" Cell "SuppressErrorStatus" Cell "ERTCustomFileBanners" Cell "GenerateSampleERTMain" Cell "GenerateTestInterfaces" Cell "ModelStepFunctionPrototypeControlCompliant" Cell "CPPClassGenCompliant" Cell "MultiInstanceERTCode" Cell "PurelyIntegerCode" Cell "SupportComplex" Cell "SupportAbsoluteTime" Cell "SupportContinuousTime" Cell "SupportNonInlinedSFcns" Cell "PortableWordSizes" PropName "DisabledProps" } TargetFcnLib "ansi_tfl_table_tmw.mat" TargetLibSuffix "" TargetPreCompLibLocation "" TargetFunctionLibrary "ANSI_C" UtilityFuncGeneration "Auto" ERTMultiwordTypeDef "System defined" CodeExecutionProfiling off ERTMultiwordLength 256 MultiwordLength 2048 GenerateFullHeader on GenerateSampleERTMain off GenerateTestInterfaces off IsPILTarget off ModelReferenceCompliant on ParMdlRefBuildCompliant on CompOptLevelCompliant on ConcurrentExecutionCompliant on IncludeMdlTerminateFcn on GeneratePreprocessorConditionals "Disable all" CombineOutputUpdateFcns off CombineSignalStateStructs off SuppressErrorStatus off ERTFirstTimeCompliant off IncludeFileDelimiter "Auto" ERTCustomFileBanners off SupportAbsoluteTime on LogVarNameModifier "rt_" MatFileLogging on MultiInstanceERTCode off SupportNonFinite on SupportComplex on PurelyIntegerCode off SupportContinuousTime on SupportNonInlinedSFcns on SupportVariableSizeSignals off EnableShiftOperators on ParenthesesLevel "Nominal" PortableWordSizes off ModelStepFunctionPrototypeControlCompliant off CPPClassGenCompliant off AutosarCompliant off UseMalloc off ExtMode off ExtModeStaticAlloc off ExtModeTesting off ExtModeStaticAllocSize 1000000 ExtModeTransport 0 ExtModeMexFile "ext_comm" ExtModeIntrfLevel "Level1" RTWCAPISignals off RTWCAPIParams off RTWCAPIStates off RTWCAPIRootIO off GenerateASAP2 off } PropName "Components" } } PropName "Components" } Name "Configuration" CurrentDlgPage "Solver" ConfigPrmDlgPosition [ 840, 485, 1720, 1115 ] } PropName "ConfigurationSets" } Simulink.ConfigSet { $PropName "ActiveConfigurationSet" $ObjectID 2 } BlockDefaults { ForegroundColor "black" BackgroundColor "white" DropShadow off NamePlacement "normal" FontName "Helvetica" FontSize 10 FontWeight "normal" FontAngle "normal" ShowName on BlockRotation 0 BlockMirror off } AnnotationDefaults { HorizontalAlignment "center" VerticalAlignment "middle" ForegroundColor "black" BackgroundColor "white" DropShadow off FontName "Helvetica" FontSize 10 FontWeight "normal" FontAngle "normal" UseDisplayTextAsClickCallback off } LineDefaults { FontName "Helvetica" FontSize 9 FontWeight "normal" FontAngle "normal" } BlockParameterDefaults { Block { BlockType Abs ZeroCross on SampleTime "-1" OutMin "[]" OutMax "[]" OutDataTypeStr "Inherit: Same as input" LockScale off RndMeth "Floor" SaturateOnIntegerOverflow on } Block { BlockType BusCreator Inputs "4" DisplayOption "none" OutDataTypeStr "Inherit: auto" NonVirtualBus off } Block { BlockType BusSelector OutputAsBus off } Block { BlockType ComplexToRealImag Output "Real and imag" SampleTime "-1" } Block { BlockType Constant Value "1" VectorParams1D on SamplingMode "Sample based" OutMin "[]" OutMax "[]" OutDataTypeStr "Inherit: Inherit from 'Constant value'" LockScale off SampleTime "inf" FramePeriod "inf" PreserveConstantTs off } Block { BlockType DiscretePulseGenerator PulseType "Sample based" TimeSource "Use simulation time" Amplitude "1" Period "2" PulseWidth "1" PhaseDelay "0" SampleTime "1" VectorParams1D on } Block { BlockType Display Format "short" Decimation "10" Floating off SampleTime "-1" } Block { BlockType From IconDisplay "Tag" TagVisibility "local" } Block { BlockType FromWorkspace VariableName "simulink_input" SampleTime "-1" Interpolate on ZeroCross off OutputAfterFinalValue "Extrapolation" } Block { BlockType Goto IconDisplay "Tag" } Block { BlockType GotoTagVisibility GotoTag "A" } Block { BlockType Inport Port "1" OutputFunctionCall off OutMin "[]" OutMax "[]" OutDataTypeStr "Inherit: auto" LockScale off BusOutputAsStruct off PortDimensions "-1" VarSizeSig "Inherit" SampleTime "-1" SignalType "auto" SamplingMode "auto" LatchByDelayingOutsideSignal off LatchInputForFeedbackSignals off Interpolate on } Block { BlockType Outport Port "1" OutMin "[]" OutMax "[]" OutDataTypeStr "Inherit: auto" LockScale off BusOutputAsStruct off PortDimensions "-1" VarSizeSig "Inherit" SampleTime "-1" SignalType "auto" SamplingMode "auto" SourceOfInitialOutputValue "Dialog" OutputWhenDisabled "held" InitialOutput "[]" } Block { BlockType Product Inputs "2" Multiplication "Element-wise(.*)" CollapseMode "All dimensions" CollapseDim "1" InputSameDT on OutMin "[]" OutMax "[]" OutDataTypeStr "Inherit: Same as first input" LockScale off RndMeth "Zero" SaturateOnIntegerOverflow on SampleTime "-1" } Block { BlockType RealImagToComplex Input "Real and imag" ConstantPart "0" SampleTime "-1" } Block { BlockType Scope ModelBased off TickLabels "OneTimeTick" ZoomMode "on" Grid "on" TimeRange "auto" YMin "-5" YMax "5" SaveToWorkspace off SaveName "ScopeData" LimitDataPoints on MaxDataPoints "5000" Decimation "1" SampleInput off SampleTime "-1" } Block { BlockType Signum ZeroCross on SampleTime "-1" } Block { BlockType SubSystem ShowPortLabels "FromPortIcon" Permissions "ReadWrite" PermitHierarchicalResolution "All" TreatAsAtomicUnit off CheckFcnCallInpInsideContextMsg off SystemSampleTime "-1" RTWFcnNameOpts "Auto" RTWFileNameOpts "Auto" RTWMemSecFuncInitTerm "Inherit from model" RTWMemSecFuncExecute "Inherit from model" RTWMemSecDataConstants "Inherit from model" RTWMemSecDataInternal "Inherit from model" RTWMemSecDataParameters "Inherit from model" SimViewingDevice off DataTypeOverride "UseLocalSettings" DataTypeOverrideAppliesTo "AllNumericTypes" MinMaxOverflowLogging "UseLocalSettings" SFBlockType "NONE" Variant off GeneratePreprocessorConditionals off } Block { BlockType Sum IconShape "rectangular" Inputs "++" CollapseMode "All dimensions" CollapseDim "1" InputSameDT on AccumDataTypeStr "Inherit: Inherit via internal rule" OutMin "[]" OutMax "[]" OutDataTypeStr "Inherit: Same as first input" LockScale off RndMeth "Floor" SaturateOnIntegerOverflow on SampleTime "-1" } Block { BlockType Terminator } Block { BlockType ToWorkspace VariableName "simulink_output" MaxDataPoints "1000" Decimation "1" SampleTime "0" FixptAsFi off NumInputs "1" } Block { BlockType ZeroOrderHold SampleTime "1" } } System { Name "wlan_phy_rx_pmd" Location [202, 70, 1808, 1180] Open on ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "126" ReportName "simulink-default.rpt" SIDHighWatermark "18166" Block { BlockType Reference Name " System Generator" SID "1" Tag "genX" Ports [] Position [427, 282, 477, 332] ShowName off AttributesFormatString "System\\nGenerator" LibraryVersion "1.2" UserDataPersistent on UserData "DataTag0" SourceBlock "xbsIndex_r4/ System Generator" SourceType "Xilinx System Generator Block" infoedit " System Generator" xilinxfamily "virtex6" part "xc6vlx240t" speed "-2" package "ff1156" synthesis_tool "XST" clock_wrapper "Clock Enables" directory "./pcore_rx_v402a" proj_type "Project Navigator" Synth_file "XST Defaults" Impl_file "ISE Defaults" testbench off simulink_period "1" sysclk_period "6.25" dcm_input_clock_period "10" incr_netlist off trim_vbits "Everywhere in SubSystem" dbl_ovrd "According to Block Masks" core_generation "According to Block Masks" run_coregen off deprecated_control off eval_field "0" has_advanced_control "0" sggui_pos "766,488,464,470" block_type "sysgen" sg_icon_stat "50,50,0,0,token,white,0,58c5b5770fe5f7c311f53dbc6e73f0f6,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 50 50 0 0 ],[0 0 50 50 0 ],[1 1 1 ]" ");\npatch([1.6375 16.81 27.31 37.81 48.31 27.31 12.1375 1.6375 ],[36.655 36.655 47.155 36.655 47.155 47.155 47.1" "55 36.655 ],[0.933333 0.203922 0.141176 ]);\npatch([12.1375 27.31 16.81 1.6375 12.1375 ],[26.155 26.155 36.655 3" "6.655 26.155 ],[0.698039 0.0313725 0.219608 ]);\npatch([1.6375 16.81 27.31 12.1375 1.6375 ],[15.655 15.655 26.15" "5 26.155 15.655 ],[0.933333 0.203922 0.141176 ]);\npatch([12.1375 48.31 37.81 27.31 16.81 1.6375 12.1375 ],[5.15" "5 5.155 15.655 5.155 15.655 15.655 5.155 ],[0.698039 0.0313725 0.219608 ]);\nfprintf('','COMMENT: end icon graph" "ics');\nfprintf('','COMMENT: begin icon text');\nfprintf('','COMMENT: end icon text');" } Block { BlockType SubSystem Name "CFO & Samp Buffer" SID "2" Ports [7, 4] Position [375, 142, 495, 228] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "CFO & Samp Buffer" Location [88, 301, 2330, 1285] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "110" Block { BlockType Inport Name "FFT tready" SID "3" Position [1060, 543, 1090, 557] IconDisplay "Port number" } Block { BlockType Inport Name "Rx I" SID "4" Position [155, 393, 185, 407] NamePlacement "alternate" Port "2" IconDisplay "Port number" } Block { BlockType Inport Name "Rx Q" SID "5" Position [120, 413, 150, 427] NamePlacement "alternate" Port "3" IconDisplay "Port number" } Block { BlockType Inport Name "IQ Valid" SID "6" Position [80, 433, 110, 447] NamePlacement "alternate" Port "4" IconDisplay "Port number" } Block { BlockType Inport Name "Pkt Det" SID "7" Position [80, 353, 110, 367] NamePlacement "alternate" Port "5" IconDisplay "Port number" } Block { BlockType Inport Name "LTS Sync" SID "8" Position [340, 503, 370, 517] Port "6" IconDisplay "Port number" } Block { BlockType Inport Name "Reset" SID "9" Position [340, 563, 370, 577] NamePlacement "alternate" Port "7" IconDisplay "Port number" } Block { BlockType Scope Name "ADC/Corr" SID "10" Ports [8] Position [855, 178, 890, 307] ZOrder -3 Floating off Location [705, 125, 1643, 1184] Open off NumInputPorts "8" ZoomMode "xonly" List { ListType AxesTitles axes1 "%" axes2 "%" axes3 "%" axes4 "%" axes5 "%" axes6 "%" axes7 "%" axes8 "%" } List { ListType ScopeGraphics FigureColor "[0.5 0.5 0.5]" AxesColor "[0 0 0]" AxesTickColor "[1 1 1]" LineColors "[1 1 0;1 0 1;0 1 1;1 0 0;0 1 0;0 0 1]" LineStyles "-|-|-|-|-|-" LineWidths "[0.5 0.5 0.5 0.5 0.5 0.5]" MarkerStyles "none|none|none|none|none|none" } TimeRange "10000 " YMin "-1~-1~0~-1~-1~-1~-1~-1" YMax "1~1~1~1~1~1~1~1" SaveName "ScopeData8" DataFormat "StructureWithTime" LimitDataPoints off SampleTime "0" } Block { BlockType SubSystem Name "CFO\nCorrection" SID "11" Ports [7, 4] Position [890, 349, 955, 521] NamePlacement "alternate" MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "CFO\nCorrection" Location [88, 301, 2330, 1301] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "178" Block { BlockType Inport Name "I " SID "12" Position [245, 248, 275, 262] IconDisplay "Port number" } Block { BlockType Inport Name "Q " SID "13" Position [245, 228, 275, 242] NamePlacement "alternate" Port "2" IconDisplay "Port number" } Block { BlockType Inport Name "DDS Run" SID "14" Position [120, 503, 150, 517] NamePlacement "alternate" Port "3" IconDisplay "Port number" } Block { BlockType Inport Name "Valid" SID "15" Position [245, 273, 275, 287] Port "4" IconDisplay "Port number" } Block { BlockType Inport Name "tlast" SID "16" Position [245, 313, 275, 327] Port "5" IconDisplay "Port number" } Block { BlockType Inport Name "CFO Est" SID "17" Position [185, 388, 215, 402] Port "6" IconDisplay "Port number" } Block { BlockType Inport Name "Reset" SID "14922" Position [120, 428, 150, 442] Port "7" IconDisplay "Port number" } Block { BlockType Scope Name "CFO Corr" SID "18" Ports [9] Position [1085, 111, 1120, 269] ZOrder -3 Floating off Location [1, 45, 1833, 1199] Open off NumInputPorts "9" ZoomMode "xonly" List { ListType AxesTitles axes1 "%" axes2 "%" axes3 "%" axes4 "%" axes5 "%" axes6 "%" axes7 "%" axes8 "%" axes9 "%" } List { ListType ScopeGraphics FigureColor "[0.5 0.5 0.5]" AxesColor "[0 0 0]" AxesTickColor "[1 1 1]" LineColors "[1 1 0;1 0 1;0 1 1;1 0 0;0 1 0;0 0 1]" LineStyles "-|-|-|-|-|-" LineWidths "[0.5 0.5 0.5 0.5 0.5 0.5]" MarkerStyles "none|none|none|none|none|none" } TimeRange "35000" YMin "0~-0.4~0~-1~0~0~-0.4~0~-5" YMax "1~0.4~1~2~1~1~0.4~1~5" SaveName "ScopeData3" DataFormat "StructureWithTime" LimitDataPoints off SampleTime "0" } Block { BlockType Reference Name "Complex Multiplier 5.0 " SID "19" Ports [7, 4] Position [675, 298, 860, 402] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Complex Multiplier 5.0 " SourceType "Xilinx Complex Multiplier 5.0 Block" hasatlast off hasatuser on atuserwidth "1" hasbtlast off hasbtuser off btuserwidth "1" multtype "Use_Mults" optimizegoal "Performance" flowcontrol "NonBlocking" outputwidth "16" roundmode "Truncate" hasctrltlast off hasctrltuser off ctrltuserwidth "1" outtlastbehv "Null" latencyconfig "Manual" minimumlatency "2" aclken off aresetn off trim_axipin_name on aportwidth "63" bportwidth "63" ip_name "Complex Multiplier" ip_version "5.0" dsptool_ready "true" ipcore_usecache "true" ipcore_useipmodelcache "true" ipcore_verbose "false" ipcore_latency_parameter "'minimumlatency'" wrapper_available "true" port_translation_map "{ 'aclken' => 'en', 'aresetn' => 'rst'}" structural_sim "false" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "cmpy_v5_0" sg_icon_stat "185,104,7,4,white,blue,0,18f8c464,right,,[2 2 2 2 3 3 3 ],[4 4 4 4 ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 0 3 3 ],[103 46 46 103 ],[6.025000" "e-001 6.400000e-001 7.075000e-001 ]);\npatch([0 0 3 3 ],[43 1 1 43 ],[4.350000e-001 4.600000e-001 5.050000e-001" " ]);\npatch([182 182 185 185 ],[96 3 3 96 ],[2.675000e-001 2.800000e-001 3.025000e-001 ]);\npatch([3 181 181 3 " "3 ],[0 0 104 104 0 ],[7.700000e-001 8.200000e-001 9.100000e-001 ]);\nplot([3 181 181 3 3 ],[0 0 104 104 0 ]);\n" "\n\npatch([60.85 81.08 95.08 109.08 123.08 95.08 74.85 60.85 ],[67.54 67.54 81.54 67.54 81.54 81.54 81.54 67.54" " ],[1 1 1 ]);\npatch([74.85 95.08 81.08 60.85 74.85 ],[53.54 53.54 67.54 67.54 53.54 ],[0.931 0.946 0.973 ]);\n" "patch([60.85 81.08 95.08 74.85 60.85 ],[39.54 39.54 53.54 53.54 39.54 ],[1 1 1 ]);\npatch([74.85 123.08 109.08 " "95.08 81.08 60.85 74.85 ],[25.54 25.54 39.54 25.54 39.54 39.54 25.54 ],[0.931 0.946 0.973 ]);\nfprintf('','COMM" "ENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,' a_tv" "alid ');\ncolor('black');port_label('input',2,' a_tdata_imag ');\ncolor('black');port_label('input',3,' a_t" "data_real ');\ncolor('black');port_label('input',4,' a_tuser ');\ncolor('black');port_label('input',5,' b_t" "valid ');\ncolor('black');port_label('input',6,' b_tdata_imag ');\ncolor('black');port_label('input',7,' b_" "tdata_real ');\ncolor('black');port_label('output',1,' dout_tvalid ');\ncolor('black');port_label('output',2" ",' dout_tdata_imag ');\ncolor('black');port_label('output',3,' dout_tdata_real ');\ncolor('black');port_lab" "el('output',4,' dout_tuser ');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Constant1" SID "20" Ports [0, 1] Position [300, 349, 330, 371] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "1" gui_display_data_type "Boolean" arith_type "Boolean" n_bits "16" bin_pt "14" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "8" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" sg_icon_stat "30,22,0,1,white,blue,0,1c72b5be,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 22 22 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 22 22 0 ]);\npatch([8.325 12.66 15.66 18.66 21.66 15.66 11.325 8.325 ],[" "14.33 14.33 17.33 14.33 17.33 17.33 17.33 14.33 ],[1 1 1 ]);\npatch([11.325 15.66 12.66 8.325 11.325 ],[11.33 1" "1.33 14.33 14.33 11.33 ],[0.931 0.946 0.973 ]);\npatch([8.325 12.66 15.66 11.325 8.325 ],[8.33 8.33 11.33 11.33" " 8.33 ],[1 1 1 ]);\npatch([11.325 21.66 18.66 15.66 12.66 8.325 11.325 ],[5.33 5.33 8.33 5.33 8.33 8.33 5.33 ]," "[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncol" "or('black');port_label('output',1,'1');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Constant2" SID "21" Ports [0, 1] Position [555, 494, 585, 516] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "1" gui_display_data_type "Fixed-point" arith_type "Signed (2's comp)" n_bits "16" bin_pt "15" preci_type "Single" exp_width "8" frac_width "24" explicit_period on period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" sg_icon_stat "30,22,0,1,white,blue,0,170720a6,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 22 22 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 22 22 0 ]);\npatch([8.325 12.66 15.66 18.66 21.66 15.66 11.325 8.325 ],[" "14.33 14.33 17.33 14.33 17.33 17.33 17.33 14.33 ],[1 1 1 ]);\npatch([11.325 15.66 12.66 8.325 11.325 ],[11.33 1" "1.33 14.33 14.33 11.33 ],[0.931 0.946 0.973 ]);\npatch([8.325 12.66 15.66 11.325 8.325 ],[8.33 8.33 11.33 11.33" " 8.33 ],[1 1 1 ]);\npatch([11.325 21.66 18.66 15.66 12.66 8.325 11.325 ],[5.33 5.33 8.33 5.33 8.33 8.33 5.33 ]," "[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncol" "or('black');port_label('output',1,'0.999969482421875');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Constant3" SID "22" Ports [0, 1] Position [555, 469, 585, 491] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "0" gui_display_data_type "Fixed-point" arith_type "Signed (2's comp)" n_bits "16" bin_pt "15" preci_type "Single" exp_width "8" frac_width "24" explicit_period on period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" sg_icon_stat "30,22,0,1,white,blue,0,bf4ddd8b,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 22 22 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 22 22 0 ]);\npatch([8.325 12.66 15.66 18.66 21.66 15.66 11.325 8.325 ],[" "14.33 14.33 17.33 14.33 17.33 17.33 17.33 14.33 ],[1 1 1 ]);\npatch([11.325 15.66 12.66 8.325 11.325 ],[11.33 1" "1.33 14.33 14.33 11.33 ],[0.931 0.946 0.973 ]);\npatch([8.325 12.66 15.66 11.325 8.325 ],[8.33 8.33 11.33 11.33" " 8.33 ],[1 1 1 ]);\npatch([11.325 21.66 18.66 15.66 12.66 8.325 11.325 ],[5.33 5.33 8.33 5.33 8.33 8.33 5.33 ]," "[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncol" "or('black');port_label('output',1,'0');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Constant5" SID "23" Ports [0, 1] Position [580, 354, 610, 376] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "1" gui_display_data_type "Boolean" arith_type "Boolean" n_bits "16" bin_pt "14" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "8" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" sg_icon_stat "30,22,0,1,white,blue,0,1c72b5be,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 22 22 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 22 22 0 ]);\npatch([8.325 12.66 15.66 18.66 21.66 15.66 11.325 8.325 ],[" "14.33 14.33 17.33 14.33 17.33 17.33 17.33 14.33 ],[1 1 1 ]);\npatch([11.325 15.66 12.66 8.325 11.325 ],[11.33 1" "1.33 14.33 14.33 11.33 ],[0.931 0.946 0.973 ]);\npatch([8.325 12.66 15.66 11.325 8.325 ],[8.33 8.33 11.33 11.33" " 8.33 ],[1 1 1 ]);\npatch([11.325 21.66 18.66 15.66 12.66 8.325 11.325 ],[5.33 5.33 8.33 5.33 8.33 8.33 5.33 ]," "[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncol" "or('black');port_label('output',1,'1');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Convert1" SID "24" Ports [1, 1] Position [930, 356, 955, 374] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do" " not." gui_display_data_type "Fixed-point" arith_type "Signed (2's comp)" n_bits "16" bin_pt "15" float_type "Single" exp_bits "8" fraction_bits "24" quantization "Truncate" overflow "Wrap" en off latency "0" dbl_ovrd off pipeline off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "convert" sg_icon_stat "25,18,1,1,white,blue,0,edca21da,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 18 18 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 18 18 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[11.2" "2 11.22 13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[9.22 9.22 11.22 " "11.22 9.22 ],[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);" "\npatch([9.55 16.44 14.44 12.44 10.44 7.55 9.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\n" "fprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label" "('output',1,'cast');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Convert2" SID "25" Ports [1, 1] Position [930, 331, 955, 349] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do" " not." gui_display_data_type "Fixed-point" arith_type "Signed (2's comp)" n_bits "16" bin_pt "15" float_type "Single" exp_bits "8" fraction_bits "24" quantization "Truncate" overflow "Wrap" en off latency "0" dbl_ovrd off pipeline off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "convert" sg_icon_stat "25,18,1,1,white,blue,0,edca21da,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 18 18 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 18 18 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[11.2" "2 11.22 13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[9.22 9.22 11.22 " "11.22 9.22 ],[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);" "\npatch([9.55 16.44 14.44 12.44 10.44 7.55 9.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\n" "fprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label" "('output',1,'cast');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Convert3" SID "26" Ports [1, 1] Position [275, 386, 300, 404] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do" " not." gui_display_data_type "Fixed-point" arith_type "Signed (2's comp)" n_bits "26" bin_pt "26" float_type "Single" exp_bits "8" fraction_bits "24" quantization "Truncate" overflow "Flag as error" en off latency "0" dbl_ovrd off pipeline off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "convert" sg_icon_stat "25,18,1,1,white,blue,0,edca21da,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 18 18 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 18 18 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[11.2" "2 11.22 13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[9.22 9.22 11.22 " "11.22 9.22 ],[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);" "\npatch([9.55 16.44 14.44 12.44 10.44 7.55 9.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\n" "fprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label" "('output',1,'cast');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Convert4" SID "27" Ports [1, 1] Position [300, 311, 325, 329] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do" " not." gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "1" bin_pt "0" float_type "Single" exp_bits "8" fraction_bits "24" quantization "Truncate" overflow "Flag as error" en off latency "0" dbl_ovrd off pipeline off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "convert" sg_icon_stat "25,18,1,1,white,blue,0,edca21da,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 18 18 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 18 18 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[11.2" "2 11.22 13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[9.22 9.22 11.22 " "11.22 9.22 ],[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);" "\npatch([9.55 16.44 14.44 12.44 10.44 7.55 9.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\n" "fprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label" "('output',1,'cast');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Convert5" SID "28" Ports [1, 1] Position [930, 381, 955, 399] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do" " not." gui_display_data_type "Boolean" arith_type "Boolean" n_bits "1" bin_pt "0" float_type "Single" exp_bits "8" fraction_bits "24" quantization "Truncate" overflow "Flag as error" en off latency "0" dbl_ovrd off pipeline off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "convert" sg_icon_stat "25,18,1,1,white,blue,0,edca21da,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 18 18 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 18 18 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[11.2" "2 11.22 13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[9.22 9.22 11.22 " "11.22 9.22 ],[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);" "\npatch([9.55 16.44 14.44 12.44 10.44 7.55 9.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\n" "fprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label" "('output',1,'cast');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "DDS Compiler 4.0" SID "29" Ports [4, 3] Position [410, 343, 495, 452] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/DDS Compiler 4.0 " SourceType "Xilinx DDS Compiler 4.0 Block" partspresent "Phase_Generator_and_SIN_COS_LUT" dds_clock_rate "160" channels "1" parameter_entry "Hardware_Parameters" spurious_free_dynamic_range "36" frequency_resolution "0.4" noise_shaping "None" phase_width "26" output_width "16" output_selection "Sine_and_Cosine" negative_sine off negative_cosine off amplitude_mode "Full_Range" memory_type "Auto" optimization_goal "Auto" dsp48_use "Minimal" latency_configuration "Auto" latency "6" has_phase_out off sclr_pin on clock_enable on rfd off rdy on channel_pin off explicit_period off period "1" phase_increment "Programmable" output_frequency1 "0" output_frequency2 "0" output_frequency3 "0" output_frequency4 "0" output_frequency5 "0" output_frequency6 "0" output_frequency7 "0" output_frequency8 "0" output_frequency9 "0" output_frequency10 "0" output_frequency11 "0" output_frequency12 "0" output_frequency13 "0" output_frequency14 "0" output_frequency15 "0" output_frequency16 "0" pinc1 "'0'" pinc2 "'0'" pinc3 "'0'" pinc4 "'0'" pinc5 "'0'" pinc6 "'0'" pinc7 "'0'" pinc8 "'0'" pinc9 "'0'" pinc10 "'0'" pinc11 "'0'" pinc12 "'0'" pinc13 "'0'" pinc14 "'0'" pinc15 "'0'" pinc16 "'0'" phase_offset "None" phase_offset_angles1 "0" phase_offset_angles2 "0" phase_offset_angles3 "0" phase_offset_angles4 "0" phase_offset_angles5 "0" phase_offset_angles6 "0" phase_offset_angles7 "0" phase_offset_angles8 "0" phase_offset_angles9 "0" phase_offset_angles10 "0" phase_offset_angles11 "0" phase_offset_angles12 "0" phase_offset_angles13 "0" phase_offset_angles14 "0" phase_offset_angles15 "0" phase_offset_angles16 "0" poff1 "'0'" poff2 "'0'" poff3 "'0'" poff4 "'0'" poff5 "'0'" poff6 "'0'" poff7 "'0'" poff8 "'0'" poff9 "'0'" poff10 "'0'" poff11 "'0'" poff12 "'0'" poff13 "'0'" poff14 "'0'" poff15 "'0'" poff16 "'0'" por_mode "false" gui_behaviour "Sysgen" ip_name "DDS Compiler" ip_version "4.0" dsptool_ready "true" wrapper_available "true" port_translation_map "{ 'ce' => 'en', 'sclr' => 'rst' }" ipcore_xco_need_fpga_part "true" ipcore_fpga_part "xlipgetpartsetting(gcb, {'virtex4', 'xc4vsx35', '-10', 'ff668'})" ipcore_usecache "true" ipcore_useipmodelcache "true" ipcore_verbose "false" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "dds_compiler_v4_0" sg_icon_stat "85,109,4,3,white,blue,0,37cfbb6d,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 85 85 0 0 ],[0 0 109 109 0 ],[0.77" " 0.82 0.91 ]);\nplot([0 85 85 0 0 ],[0 0 109 109 0 ]);\npatch([15.3 32.64 44.64 56.64 68.64 44.64 27.3 15.3 ],[" "67.32 67.32 79.32 67.32 79.32 79.32 79.32 67.32 ],[1 1 1 ]);\npatch([27.3 44.64 32.64 15.3 27.3 ],[55.32 55.32 " "67.32 67.32 55.32 ],[0.931 0.946 0.973 ]);\npatch([15.3 32.64 44.64 27.3 15.3 ],[43.32 43.32 55.32 55.32 43.32 " "],[1 1 1 ]);\npatch([27.3 68.64 56.64 44.64 32.64 15.3 27.3 ],[31.32 31.32 43.32 31.32 43.32 43.32 31.32 ],[0.9" "31 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('" "black');port_label('input',1,'we');\ncolor('black');port_label('input',2,'data');\ncolor('black');port_label('i" "nput',3,'rst');\ncolor('black');port_label('input',4,'en');\ncolor('black');port_label('output',1,'rdy');\ncolo" "r('black');port_label('output',2,'sine');\ncolor('black');port_label('output',3,'cosine');\nfprintf('','COMMENT" ": end icon text');" } Block { BlockType Reference Name "Gateway Out1" SID "31" Ports [1, 1] Position [935, 139, 970, 151] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of t" "ype Simulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become t" "op level output ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0" ".88 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ]" ",[7.11 7.11 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7." "11 7.11 6.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1" " 1 1 ]);\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0." "964 0.964 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black" "');port_label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nf" "printf('','COMMENT: end icon text');" Port { PortNumber 1 Name "I In" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out17" SID "32" Ports [1, 1] Position [935, 124, 970, 136] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of t" "ype Simulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become t" "op level output ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0" ".88 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ]" ",[7.11 7.11 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7." "11 7.11 6.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1" " 1 1 ]);\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0." "964 0.964 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black" "');port_label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nf" "printf('','COMMENT: end icon text');" Port { PortNumber 1 Name "DDS En" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out2" SID "33" Ports [1, 1] Position [935, 154, 970, 166] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of t" "ype Simulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become t" "op level output ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0" ".88 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ]" ",[7.11 7.11 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7." "11 7.11 6.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1" " 1 1 ]);\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0." "964 0.964 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black" "');port_label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nf" "printf('','COMMENT: end icon text');" Port { PortNumber 1 Name "IQ Valid In" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out3" SID "34" Ports [1, 1] Position [935, 169, 970, 181] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of t" "ype Simulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become t" "op level output ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0" ".88 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ]" ",[7.11 7.11 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7." "11 7.11 6.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1" " 1 1 ]);\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0." "964 0.964 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black" "');port_label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nf" "printf('','COMMENT: end icon text');" Port { PortNumber 1 Name "DDS Q" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out4" SID "35" Ports [1, 1] Position [935, 184, 970, 196] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of t" "ype Simulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become t" "op level output ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0" ".88 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ]" ",[7.11 7.11 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7." "11 7.11 6.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1" " 1 1 ]);\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0." "964 0.964 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black" "');port_label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nf" "printf('','COMMENT: end icon text');" Port { PortNumber 1 Name "tlast In" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out5" SID "36" Ports [1, 1] Position [935, 199, 970, 211] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of t" "ype Simulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become t" "op level output ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0" ".88 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ]" ",[7.11 7.11 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7." "11 7.11 6.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1" " 1 1 ]);\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0." "964 0.964 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black" "');port_label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nf" "printf('','COMMENT: end icon text');" Port { PortNumber 1 Name "Mult tvalid out" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out6" SID "37" Ports [1, 1] Position [935, 214, 970, 226] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of t" "ype Simulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become t" "op level output ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0" ".88 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ]" ",[7.11 7.11 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7." "11 7.11 6.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1" " 1 1 ]);\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0." "964 0.964 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black" "');port_label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nf" "printf('','COMMENT: end icon text');" Port { PortNumber 1 Name "Mult Q" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out7" SID "38" Ports [1, 1] Position [935, 229, 970, 241] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of t" "ype Simulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become t" "op level output ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0" ".88 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ]" ",[7.11 7.11 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7." "11 7.11 6.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1" " 1 1 ]);\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0." "964 0.964 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black" "');port_label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nf" "printf('','COMMENT: end icon text');" Port { PortNumber 1 Name "Mult tlast" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out8" SID "14923" Ports [1, 1] Position [935, 244, 970, 256] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of t" "ype Simulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become t" "op level output ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0" ".88 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ]" ",[7.11 7.11 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7." "11 7.11 6.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1" " 1 1 ]);\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0." "964 0.964 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black" "');port_label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nf" "printf('','COMMENT: end icon text');" Port { PortNumber 1 Name "DDS Reset" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType SubSystem Name "Reset-En Logic" SID "14924" Ports [2, 2] Position [225, 440, 315, 500] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "Reset-En Logic" Location [-890, 709, -213, 1055] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "125" Block { BlockType Inport Name "Reset" SID "14925" Position [265, 43, 295, 57] NamePlacement "alternate" IconDisplay "Port number" } Block { BlockType Inport Name "DDS Run" SID "14927" Position [265, 218, 295, 232] NamePlacement "alternate" Port "2" IconDisplay "Port number" } Block { BlockType Reference Name "Delay" SID "14936" Ports [1, 1] Position [600, 190, 635, 220] BlockMirror on NamePlacement "alternate" ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flop." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en off latency "8" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" sg_icon_stat "35,30,1,1,white,blue,0,e47f993a,left,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 30 30 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 35 35 0 0 ],[0 0 30 30 0 ]);\npatch([8.1 13.88 17.88 21.88 25.88 17.88 12.1 8.1 ],[19.44 19.44 23.4" "4 19.44 23.44 23.44 23.44 19.44 ],[1 1 1 ]);\npatch([12.1 17.88 13.88 8.1 12.1 ],[15.44 15.44 19.44 19.44 15.44 ]," "[0.931 0.946 0.973 ]);\npatch([8.1 13.88 17.88 12.1 8.1 ],[11.44 11.44 15.44 15.44 11.44 ],[1 1 1 ]);\npatch([12.1" " 25.88 21.88 17.88 13.88 8.1 12.1 ],[7.44 7.44 11.44 7.44 11.44 11.44 7.44 ],[0.931 0.946 0.973 ]);\nfprintf('','C" "OMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');disp('z^{-8}','texmode'," "'on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType From Name "From2" SID "14929" Position [105, 71, 235, 89] ShowName off CloseFcn "tagdialog Close" GotoTag "RX_GLOBAL_RESET" TagVisibility "global" } Block { BlockType Reference Name "Logical1" SID "14921" Ports [3, 1] Position [365, 36, 405, 124] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "OR" inputs "3" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" sg_icon_stat "40,88,3,1,white,blue,0,a2abe52d,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 88 88 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 40 40 0 0 ],[0 0 88 88 0 ]);\npatch([8.875 16.1 21.1 26.1 31.1 21.1 13.875 8.875 ],[49.55 49.55 54." "55 49.55 54.55 54.55 54.55 49.55 ],[1 1 1 ]);\npatch([13.875 21.1 16.1 8.875 13.875 ],[44.55 44.55 49.55 49.55 44." "55 ],[0.931 0.946 0.973 ]);\npatch([8.875 16.1 21.1 13.875 8.875 ],[39.55 39.55 44.55 44.55 39.55 ],[1 1 1 ]);\npa" "tch([13.875 31.1 26.1 21.1 16.1 8.875 13.875 ],[34.55 34.55 39.55 34.55 39.55 39.55 34.55 ],[0.931 0.946 0.973 ]);" "\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\n\ncolor('black');disp(" "'or');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical2" SID "39" Ports [2, 1] Position [695, 155, 735, 250] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "OR" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" sg_icon_stat "40,95,2,1,white,blue,0,7ede7d88,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 95 95 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 40 40 0 0 ],[0 0 95 95 0 ]);\npatch([8.875 16.1 21.1 26.1 31.1 21.1 13.875 8.875 ],[52.55 52.55 57." "55 52.55 57.55 57.55 57.55 52.55 ],[1 1 1 ]);\npatch([13.875 21.1 16.1 8.875 13.875 ],[47.55 47.55 52.55 52.55 47." "55 ],[0.931 0.946 0.973 ]);\npatch([8.875 16.1 21.1 13.875 8.875 ],[42.55 42.55 47.55 47.55 42.55 ],[1 1 1 ]);\npa" "tch([13.875 31.1 26.1 21.1 16.1 8.875 13.875 ],[37.55 37.55 42.55 37.55 42.55 42.55 37.55 ],[0.931 0.946 0.973 ]);" "\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\ncolor('black');disp('o" "r');\nfprintf('','COMMENT: end icon text');" } Block { BlockType SubSystem Name "S-R Latch1" SID "14938" Ports [2, 1] Position [600, 133, 635, 162] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "S-R Latch1" Location [351, 366, 2001, 1172] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "S" SID "14939" Position [140, 103, 170, 117] IconDisplay "Port number" } Block { BlockType Inport Name "R" SID "14940" Position [140, 88, 170, 102] NamePlacement "alternate" Port "2" IconDisplay "Port number" } Block { BlockType Reference Name "Constant1" SID "14941" Ports [0, 1] Position [195, 71, 210, 89] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "1" gui_display_data_type "Fixed-point" arith_type "Boolean" n_bits "1" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" block_version "VER_STRING_GOES_HERE" sg_icon_stat "15,18,0,1,white,blue,0,1c72b5be,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 15 15 0 0 ],[0 0 18 18 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 15 15 0 0 ],[0 0 18 18 0 ]);\npatch([2.55 5.44 7.44 9.44 11.44 7.44 4.55 2.55 ],[11.22 11.22 " "13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([4.55 7.44 5.44 2.55 4.55 ],[9.22 9.22 11.22 11.22 9.22 " "],[0.931 0.946 0.973 ]);\npatch([2.55 5.44 7.44 4.55 2.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);\npatch([4.55 " "11.44 9.44 7.44 5.44 2.55 4.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\nfprintf('','COMME" "NT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'1');\nf" "printf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Convert1" SID "14942" Ports [1, 1] Position [210, 86, 235, 104] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do no" "t." gui_display_data_type "Boolean" arith_type "Boolean" n_bits "1" bin_pt "0" float_type "Single" exp_bits "8" fraction_bits "24" quantization "Truncate" overflow "Wrap" en off latency "0" dbl_ovrd off pipeline off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "convert" sg_icon_stat "25,18,1,1,white,blue,0,edca21da,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 18 18 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 18 18 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[11.22 11" ".22 13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[9.22 9.22 11.22 11.22" " 9.22 ],[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);\npatc" "h([9.55 16.44 14.44 12.44 10.44 7.55 9.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\nfprint" "f('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('outpu" "t',1,'cast');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Convert2" SID "14943" Ports [1, 1] Position [210, 101, 235, 119] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do no" "t." gui_display_data_type "Boolean" arith_type "Boolean" n_bits "1" bin_pt "0" float_type "Single" exp_bits "8" fraction_bits "24" quantization "Truncate" overflow "Wrap" en off latency "0" dbl_ovrd off pipeline off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "convert" sg_icon_stat "25,18,1,1,white,blue,0,edca21da,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 18 18 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 18 18 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[11.22 11" ".22 13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[9.22 9.22 11.22 11.22" " 9.22 ],[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);\npatc" "h([9.55 16.44 14.44 12.44 10.44 7.55 9.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\nfprint" "f('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('outpu" "t',1,'cast');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register2" SID "14944" Ports [3, 1] Position [255, 71, 300, 119] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst on en on dbl_ovrd off xl_use_area off xl_area "[1 1 0 0 0 0 0]" has_advanced_control "0" sggui_pos "20,20,348,193" block_type "register" block_version "VER_STRING_GOES_HERE" sg_icon_stat "45,48,3,1,white,blue,0,30546de1,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 48 48 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 45 45 0 0 ],[0 0 48 48 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[30.66 3" "0.66 36.66 30.66 36.66 36.66 36.66 30.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[24.66 24.66 30.66 " "30.66 24.66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[18.66 18.66 24.66 24.66 18.66 ],[1 1" " 1 ]);\npatch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[12.66 12.66 18.66 12.66 18.66 18.66 12.66 ],[0.931 0." "946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black'" ");port_label('input',1,'d');\ncolor('black');port_label('input',2,'rst');\ncolor('black');port_label('input',3,'" "en');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','CO" "MMENT: end icon text');" } Block { BlockType Outport Name "Q" SID "14945" Position [325, 88, 355, 102] IconDisplay "Port number" } Line { SrcBlock "S" SrcPort 1 DstBlock "Convert2" DstPort 1 } Line { SrcBlock "Register2" SrcPort 1 DstBlock "Q" DstPort 1 } Line { SrcBlock "R" SrcPort 1 DstBlock "Convert1" DstPort 1 } Line { SrcBlock "Constant1" SrcPort 1 DstBlock "Register2" DstPort 1 } Line { SrcBlock "Convert1" SrcPort 1 DstBlock "Register2" DstPort 2 } Line { SrcBlock "Convert2" SrcPort 1 DstBlock "Register2" DstPort 3 } } } Block { BlockType SubSystem Name "Sim Reset" SID "40" Ports [0, 1] Position [190, 95, 235, 125] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "Sim Reset" Location [177, 931, 726, 1168] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Reference Name "Constant4" SID "41" Ports [0, 1] Position [320, 169, 350, 191] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "0" gui_display_data_type "Boolean" arith_type "Boolean" n_bits "16" bin_pt "14" preci_type "Single" exp_width "8" frac_width "24" explicit_period on period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" sg_icon_stat "30,22,0,1,white,blue,0,bf4ddd8b,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 22 22 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 22 22 0 ]);\npatch([8.325 12.66 15.66 18.66 21.66 15.66 11.325 8.325 ],[14.3" "3 14.33 17.33 14.33 17.33 17.33 17.33 14.33 ],[1 1 1 ]);\npatch([11.325 15.66 12.66 8.325 11.325 ],[11.33 11.33 " "14.33 14.33 11.33 ],[0.931 0.946 0.973 ]);\npatch([8.325 12.66 15.66 11.325 8.325 ],[8.33 8.33 11.33 11.33 8.33 " "],[1 1 1 ]);\npatch([11.325 21.66 18.66 15.66 12.66 8.325 11.325 ],[5.33 5.33 8.33 5.33 8.33 8.33 5.33 ],[0.931 " "0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('blac" "k');port_label('output',1,'0');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Simulation Multiplexer" SID "42" Ports [2, 1] Position [415, 122, 465, 173] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Simulation Multiplexer" SourceType "Xilinx Simulation Multiplexer Block" infoedit "Distinguish input subsystems as \"simulation only\" and \"generation only\". The input specified" " For Simulation will be used during Simulink simulation. The input specified For Generation will be used during" " code generation. This block will typically be used on the output of a HW Co-Simulation, Black Box, or ModelSim" " subsystem.

Hardware Notes: This block costs nothing." sim_sel "1" hw_sel "2" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "simmux" sg_icon_stat "50,51,2,1,white,blue,0,4170dd71,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 50 50 0 0 ],[0 0 51 51 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 50 50 0 0 ],[0 0 51 51 0 ]);\npatch([9.425 19.54 26.54 33.54 40.54 26.54 16.425 9.425 ],[32.7" "7 32.77 39.77 32.77 39.77 39.77 39.77 32.77 ],[1 1 1 ]);\npatch([16.425 26.54 19.54 9.425 16.425 ],[25.77 25.77 " "32.77 32.77 25.77 ],[0.931 0.946 0.973 ]);\npatch([9.425 19.54 26.54 16.425 9.425 ],[18.77 18.77 25.77 25.77 18." "77 ],[1 1 1 ]);\npatch([16.425 40.54 33.54 26.54 19.54 9.425 16.425 ],[11.77 11.77 18.77 11.77 18.77 18.77 11.77" " ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n" "\n\nfprintf('','COMMENT: end icon text');color('red');\nplot(swLineX,simSwLineY);\ncolor('black');\nplot(swLineX" ",hwSwLineY);\n" } Block { BlockType SubSystem Name "Subsystem" SID "43" Ports [0, 1] Position [210, 85, 250, 145] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "Subsystem" Location [386, 369, 716, 654] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Reference Name "Disregard Subsystem" SID "44" Tag "discardX" Ports [] Position [228, 177, 286, 235] ShowName off AttributesFormatString "Disregard Subsystem\\nFor Generation" LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Disregard Subsystem" SourceType "Xilinx Disregard Subsystem For Generation Block" infoedit "Place this block into a subsystem to have System Generator ignore the subsystem during code gener" "ation. This block can be used in combination with the Simulation Multiplexer block to provide an alternative sim" "ulation model for another subsystem (e.g., to provide a simulation model for a black box)." has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "disregard" sg_icon_stat "58,58,-1,-1,darkgray,black,0,07734,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 58 58 0 0 ],[0 0 58 58 0 ],[0.1 0.1 0" ".1 ]);\nplot([0 58 58 0 0 ],[0 0 58 58 0 ]);\npatch([11.2 22.76 30.76 38.76 46.76 30.76 19.2 11.2 ],[37.88 37.88" " 45.88 37.88 45.88 45.88 45.88 37.88 ],[0.33 0.33 0.33 ]);\npatch([19.2 30.76 22.76 11.2 19.2 ],[29.88 29.88 37." "88 37.88 29.88 ],[0.261 0.261 0.261 ]);\npatch([11.2 22.76 30.76 19.2 11.2 ],[21.88 21.88 29.88 29.88 21.88 ],[0" ".33 0.33 0.33 ]);\npatch([19.2 46.76 38.76 30.76 22.76 11.2 19.2 ],[13.88 13.88 21.88 13.88 21.88 21.88 13.88 ]," "[0.261 0.261 0.261 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\nfpri" "ntf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway In" SID "45" Ports [1, 1] Position [105, 40, 170, 60] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway In" SourceType "Xilinx Gateway In Block" infoedit "Gateway in block. Converts inputs of type Simulink integer, single, double and fixed-point to X" "ilinx fixed-point or floating-point data type.

Hardware notes: In hardware these blocks become top level" " input ports." gui_display_data_type "Boolean" arith_type "Boolean" n_bits "16" bin_pt "14" preci_type "Single" exp_width "8" frac_width "24" quantization "Round (unbiased: +/- Inf)" overflow "Saturate" period "1" dbl_ovrd off timing_constraint "None" locs_specified off LOCs "{}" UseAsADC off ADCChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" inherit_from_input off hdl_port "on" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayin" sg_icon_stat "65,20,1,1,white,yellow,1,00d3666e,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 65 65 0 0 ],[0 0 20 20 0 ],[0.95 0.93" " 0.65 ]);\nplot([0 65 65 0 0 ],[0 0 20 20 0 ]);\npatch([27.55 30.44 32.44 34.44 36.44 32.44 29.55 27.55 ],[12.22" " 12.22 14.22 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([29.55 32.44 30.44 27.55 29.55 ],[10.22 10.22 12." "22 12.22 10.22 ],[0.985 0.979 0.895 ]);\npatch([27.55 30.44 32.44 29.55 27.55 ],[8.22 8.22 10.22 10.22 8.22 ],[1" " 1 1 ]);\npatch([29.55 36.44 34.44 32.44 30.44 27.55 29.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.985 0.979 " "0.895 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');po" "rt_label('input',1,'\\fontsize{11pt}\\bf In ','texmode','on');\ncolor('black');port_label('output',1,' ');\nfpri" "ntf('','COMMENT: end icon text');" } Block { BlockType DiscretePulseGenerator Name "Pulse\nGenerator" SID "46" Ports [0, 1] Position [25, 29, 55, 61] ZOrder -13 Period "1e9" PulseWidth "16" PhaseDelay "1" } Block { BlockType Outport Name "Out1" SID "47" Position [195, 43, 225, 57] IconDisplay "Port number" } Line { SrcBlock "Pulse\nGenerator" SrcPort 1 Points [15, 0; 0, 5] DstBlock "Gateway In" DstPort 1 } Line { SrcBlock "Gateway In" SrcPort 1 DstBlock "Out1" DstPort 1 } } } Block { BlockType Outport Name "Out1" SID "48" Position [490, 143, 520, 157] IconDisplay "Port number" } Line { SrcBlock "Subsystem" SrcPort 1 Points [0, 20] DstBlock "Simulation Multiplexer" DstPort 1 } Line { SrcBlock "Constant4" SrcPort 1 Points [20, 0; 0, -20] DstBlock "Simulation Multiplexer" DstPort 2 } Line { SrcBlock "Simulation Multiplexer" SrcPort 1 DstBlock "Out1" DstPort 1 } } } Block { BlockType SubSystem Name "negedge" SID "14930" Ports [1, 1] Position [465, 128, 520, 152] NamePlacement "alternate" MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "negedge" Location [88, 301, 2330, 1301] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "D" SID "14931" Position [275, 178, 305, 192] IconDisplay "Port number" } Block { BlockType Reference Name "Delay" SID "14932" Ports [1, 1] Position [425, 153, 460, 177] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flop. " "If register retiming is enabled, the delay line is a chain of flip-flops." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en off latency "1" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[1 1 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,24,1,1,white,blue,0,07b98262,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 24 24 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 24 24 0 ]);\npatch([10.325 14.66 17.66 20.66 23.66 17.66 13.325 10.325 ],[15" ".33 15.33 18.33 15.33 18.33 18.33 18.33 15.33 ],[1 1 1 ]);\npatch([13.325 17.66 14.66 10.325 13.325 ],[12.33 12." "33 15.33 15.33 12.33 ],[0.931 0.946 0.973 ]);\npatch([10.325 14.66 17.66 13.325 10.325 ],[9.33 9.33 12.33 12.33 " "9.33 ],[1 1 1 ]);\npatch([13.325 23.66 20.66 17.66 14.66 10.325 13.325 ],[6.33 6.33 9.33 6.33 9.33 9.33 6.33 ],[" "0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\nc" "olor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Inverter" SID "14933" Ports [1, 1] Position [490, 181, 515, 199] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Inverter" SourceType "Xilinx Inverter Block" infoedit "Bitwise logical negation (one's complement) operator." en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "inv" block_version "VER_STRING_GOES_HERE" sg_icon_stat "25,18,1,1,white,blue,0,267846e5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 18 18 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 18 18 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[11.22 11" ".22 13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[9.22 9.22 11.22 11.22" " 9.22 ],[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);\npatc" "h([9.55 16.44 14.44 12.44 10.44 7.55 9.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\nfprint" "f('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');disp('not');\nf" "printf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical1" SID "14934" Ports [2, 1] Position [540, 151, 585, 204] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "AND" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "8" bin_pt "2" align_bp on dbl_ovrd off xl_use_area off xl_area "[1 0 0 1 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" block_version "VER_STRING_GOES_HERE" sg_icon_stat "45,53,2,1,white,blue,0,83a4b621,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 53 53 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 45 45 0 0 ],[0 0 53 53 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[32.66 3" "2.66 38.66 32.66 38.66 38.66 38.66 32.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[26.66 26.66 32.66 " "32.66 26.66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[20.66 20.66 26.66 26.66 20.66 ],[1 1" " 1 ]);\npatch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[14.66 14.66 20.66 14.66 20.66 20.66 14.66 ],[0.931 0." "946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\ncolor('" "black');disp('and');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Outport Name "Q" SID "14935" Position [610, 173, 640, 187] IconDisplay "Port number" } Line { SrcBlock "D" SrcPort 1 Points [75, 0; 0, 5] Branch { Points [0, -25] DstBlock "Delay" DstPort 1 } Branch { DstBlock "Inverter" DstPort 1 } } Line { SrcBlock "Logical1" SrcPort 1 DstBlock "Q" DstPort 1 } Line { SrcBlock "Delay" SrcPort 1 DstBlock "Logical1" DstPort 1 } Line { SrcBlock "Inverter" SrcPort 1 DstBlock "Logical1" DstPort 2 } } } Block { BlockType Outport Name "Rst" SID "14926" Position [755, 73, 785, 87] IconDisplay "Port number" } Block { BlockType Outport Name "En" SID "14928" Position [755, 198, 785, 212] Port "2" IconDisplay "Port number" } Line { SrcBlock "DDS Run" SrcPort 1 DstBlock "Logical2" DstPort 2 } Line { SrcBlock "Reset" SrcPort 1 DstBlock "Logical1" DstPort 1 } Line { SrcBlock "Logical1" SrcPort 1 Points [30, 0] Branch { DstBlock "Rst" DstPort 1 } Branch { Points [0, 60] DstBlock "negedge" DstPort 1 } } Line { SrcBlock "Logical2" SrcPort 1 DstBlock "En" DstPort 1 } Line { SrcBlock "From2" SrcPort 1 DstBlock "Logical1" DstPort 2 } Line { SrcBlock "Sim Reset" SrcPort 1 DstBlock "Logical1" DstPort 3 } Line { SrcBlock "negedge" SrcPort 1 DstBlock "S-R Latch1" DstPort 1 } Line { SrcBlock "Delay" SrcPort 1 Points [-20, 0; 0, -50] DstBlock "S-R Latch1" DstPort 2 } Line { SrcBlock "S-R Latch1" SrcPort 1 Points [20, 0; 0, 30] Branch { DstBlock "Logical2" DstPort 1 } Branch { Points [0, 25] DstBlock "Delay" DstPort 1 } } Annotation { Name "DDS requires >4(?) cycle EN early to get setup after\nconfig and after every reset event.\nOtherwise its" " outputs are invalid for a few cycles,\nleading to invalid FFT outputs. It is not clear what\nhappens in hardware," " but in sim this post-rst invalid\nstate breaks Rx entirely." Position [442, 381] } } } Block { BlockType Outport Name "valid" SID "49" Position [1015, 308, 1045, 322] NamePlacement "alternate" IconDisplay "Port number" } Block { BlockType Outport Name "I" SID "50" Position [1015, 358, 1045, 372] Port "2" IconDisplay "Port number" } Block { BlockType Outport Name "Q" SID "51" Position [1015, 333, 1045, 347] NamePlacement "alternate" Port "3" IconDisplay "Port number" } Block { BlockType Outport Name " tlast" SID "52" Position [1015, 383, 1045, 397] Port "4" IconDisplay "Port number" } Line { SrcBlock "Constant1" SrcPort 1 DstBlock "DDS Compiler 4.0" DstPort 1 } Line { SrcBlock "CFO Est" SrcPort 1 DstBlock "Convert3" DstPort 1 } Line { SrcBlock "Complex Multiplier 5.0 " SrcPort 2 Points [20, 0] Branch { DstBlock "Convert2" DstPort 1 } Branch { Points [0, -120] DstBlock "Gateway Out6" DstPort 1 } } Line { SrcBlock "Complex Multiplier 5.0 " SrcPort 3 DstBlock "Convert1" DstPort 1 } Line { SrcBlock "I " SrcPort 1 Points [205, 0] Branch { Points [125, 0; 0, 80] DstBlock "Complex Multiplier 5.0 " DstPort 3 } Branch { Points [0, -110] DstBlock "Gateway Out1" DstPort 1 } } Line { SrcBlock "Q " SrcPort 1 Points [335, 0; 0, 85] DstBlock "Complex Multiplier 5.0 " DstPort 2 } Line { Name "DDS En" Labels [0, 0] SrcBlock "Gateway Out17" SrcPort 1 DstBlock "CFO Corr" DstPort 1 } Line { Name "I In" Labels [0, 0] SrcBlock "Gateway Out1" SrcPort 1 DstBlock "CFO Corr" DstPort 2 } Line { Name "IQ Valid In" Labels [0, 0] SrcBlock "Gateway Out2" SrcPort 1 DstBlock "CFO Corr" DstPort 3 } Line { Name "DDS Q" Labels [0, 0] SrcBlock "Gateway Out3" SrcPort 1 DstBlock "CFO Corr" DstPort 4 } Line { Name "tlast In" Labels [0, 0] SrcBlock "Gateway Out4" SrcPort 1 DstBlock "CFO Corr" DstPort 5 } Line { SrcBlock "DDS Compiler 4.0" SrcPort 2 Points [0, -5; 20, 0] Branch { Points [120, 0; 0, -15] DstBlock "Complex Multiplier 5.0 " DstPort 6 } Branch { Points [0, -220] DstBlock "Gateway Out3" DstPort 1 } } Line { SrcBlock "Valid" SrcPort 1 Points [220, 0] Branch { Points [130, 0; 0, 25] DstBlock "Complex Multiplier 5.0 " DstPort 1 } Branch { Points [0, -120] DstBlock "Gateway Out2" DstPort 1 } } Line { SrcBlock "Convert1" SrcPort 1 DstBlock "I" DstPort 1 } Line { SrcBlock "Convert2" SrcPort 1 DstBlock "Q" DstPort 1 } Line { SrcBlock "Complex Multiplier 5.0 " SrcPort 1 Points [15, 0] Branch { DstBlock "valid" DstPort 1 } Branch { Points [0, -110] DstBlock "Gateway Out5" DstPort 1 } } Line { SrcBlock "DDS Compiler 4.0" SrcPort 3 Points [160, 0] DstBlock "Complex Multiplier 5.0 " DstPort 7 } Line { SrcBlock "Reset-En Logic" SrcPort 2 Points [50, 0; 0, -50] Branch { Points [0, -305] DstBlock "Gateway Out17" DstPort 1 } Branch { DstBlock "DDS Compiler 4.0" DstPort 4 } } Line { SrcBlock "Convert3" SrcPort 1 Points [90, 0] DstBlock "DDS Compiler 4.0" DstPort 2 } Line { SrcBlock "Constant5" SrcPort 1 DstBlock "Complex Multiplier 5.0 " DstPort 5 } Line { SrcBlock "tlast" SrcPort 1 DstBlock "Convert4" DstPort 1 } Line { SrcBlock "Complex Multiplier 5.0 " SrcPort 4 Points [25, 0] Branch { Points [0, -155] DstBlock "Gateway Out7" DstPort 1 } Branch { DstBlock "Convert5" DstPort 1 } } Line { Name "Mult tvalid out" Labels [0, 0] SrcBlock "Gateway Out5" SrcPort 1 DstBlock "CFO Corr" DstPort 6 } Line { Name "Mult Q" Labels [0, 0] SrcBlock "Gateway Out6" SrcPort 1 DstBlock "CFO Corr" DstPort 7 } Line { Name "Mult tlast" Labels [0, 0] SrcBlock "Gateway Out7" SrcPort 1 DstBlock "CFO Corr" DstPort 8 } Line { SrcBlock "Convert4" SrcPort 1 Points [205, 0] Branch { Points [55, 0; 0, 30] DstBlock "Complex Multiplier 5.0 " DstPort 4 } Branch { Points [0, -130] DstBlock "Gateway Out4" DstPort 1 } } Line { SrcBlock "Convert5" SrcPort 1 DstBlock " tlast" DstPort 1 } Line { SrcBlock "Reset-En Logic" SrcPort 1 Points [40, 0; 0, -45] Branch { DstBlock "DDS Compiler 4.0" DstPort 3 } Branch { Points [0, -160] DstBlock "Gateway Out8" DstPort 1 } } Line { Name "DDS Reset" Labels [0, 0] SrcBlock "Gateway Out8" SrcPort 1 DstBlock "CFO Corr" DstPort 9 } Line { SrcBlock "Reset" SrcPort 1 Points [10, 0; 0, 20] DstBlock "Reset-En Logic" DstPort 1 } Line { SrcBlock "DDS Run" SrcPort 1 Points [10, 0; 0, -25] DstBlock "Reset-En Logic" DstPort 2 } Annotation { Name "\n\nDDS updates once per input sample\nSince the FFT only consumes 64 samples\nper OFDM symbol (ig" "noring the CP),\nthe DDS keeps running after each FFT \nframe is loaded. This is fine, since the FFT is\nconfig" "ured for non-streaming (it ignores its\nI/Q inputs while computing a transform)" Position [452, 594] } } } Block { BlockType SubSystem Name "CFO Estimation" SID "53" Ports [5, 1] Position [700, 502, 775, 578] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "CFO Estimation" Location [442, 320, 2429, 1372] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "112" Block { BlockType Inport Name "LTS_Sync" SID "54" Position [140, 533, 170, 547] IconDisplay "Port number" } Block { BlockType Inport Name "rx_I" SID "55" Position [140, 223, 170, 237] NamePlacement "alternate" Port "2" IconDisplay "Port number" } Block { BlockType Inport Name "rx_Q" SID "56" Position [140, 253, 170, 267] NamePlacement "alternate" Port "3" IconDisplay "Port number" } Block { BlockType Inport Name "rx_valid" SID "57" Position [140, 193, 170, 207] NamePlacement "alternate" Port "4" IconDisplay "Port number" } Block { BlockType Inport Name "Reset" SID "14918" Position [140, 603, 170, 617] Port "5" IconDisplay "Port number" } Block { BlockType Scope Name "CFO Est" SID "58" Ports [10] Position [1370, 45, 1405, 255] ZOrder -3 Floating off Location [6, 40, 1841, 1194] Open off NumInputPorts "10" ZoomMode "yonly" List { ListType AxesTitles axes1 "%" axes2 "%" axes3 "%" axes4 "%" axes5 "%" axes6 "%" axes7 "%" axes8 "%" axes9 "%" axes10 "%" } List { ListType ScopeGraphics FigureColor "[0.5 0.5 0.5]" AxesColor "[0 0 0]" AxesTickColor "[1 1 1]" LineColors "[1 1 0;1 0 1;0 1 1;1 0 0;0 1 0;0 0 1]" LineStyles "-|-|-|-|-|-" LineWidths "[0.5 0.5 0.5 0.5 0.5 0.5]" MarkerStyles "none|none|none|none|none|none" } TimeRange "10000" YMin "-1~-1~-0.25~-1~-10~-2.5~-1~0~0~-1" YMax "1~1~2~2~50~15~1~1~0.001~1" SaveName "ScopeData1" DataFormat "StructureWithTime" LimitDataPoints off SampleTime "0" } Block { BlockType SubSystem Name "Conj Mult" SID "59" Ports [5, 3] Position [480, 180, 540, 340] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "Conj Mult" Location [227, 108, 1983, 1242] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "Valid" SID "60" Position [150, 293, 180, 307] NamePlacement "alternate" IconDisplay "Port number" } Block { BlockType Inport Name "A I" SID "61" Position [150, 333, 180, 347] NamePlacement "alternate" Port "2" IconDisplay "Port number" } Block { BlockType Inport Name "A Q" SID "62" Position [150, 418, 180, 432] NamePlacement "alternate" Port "3" IconDisplay "Port number" } Block { BlockType Inport Name "B I" SID "63" Position [150, 363, 180, 377] NamePlacement "alternate" Port "4" IconDisplay "Port number" } Block { BlockType Inport Name "B Q" SID "64" Position [150, 448, 180, 462] NamePlacement "alternate" Port "5" IconDisplay "Port number" } Block { BlockType Reference Name "AddSub" SID "65" Ports [2, 1] Position [490, 351, 520, 409] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/AddSub" SourceType "Xilinx Adder/Subtracter Block" mode "Addition" use_carryin off use_carryout off en off latency "1" precision "User Defined" arith_type "Signed (2's comp)" n_bits "17" bin_pt "14" quantization "Truncate" overflow "Flag as error" dbl_ovrd off use_behavioral_HDL off hw_selection "Fabric" pipelined off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "addsub" sg_icon_stat "30,58,2,1,white,blue,0,e85d8a90,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 58 58 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 30 30 0 0 ],[0 0 58 58 0 ]);\npatch([6.1 11.88 15.88 19.88 23.88 15.88 10.1 6.1 ],[33.44 33.44 37.4" "4 33.44 37.44 37.44 37.44 33.44 ],[1 1 1 ]);\npatch([10.1 15.88 11.88 6.1 10.1 ],[29.44 29.44 33.44 33.44 29.44 ]," "[0.931 0.946 0.973 ]);\npatch([6.1 11.88 15.88 10.1 6.1 ],[25.44 25.44 29.44 29.44 25.44 ],[1 1 1 ]);\npatch([10.1" " 23.88 19.88 15.88 11.88 6.1 10.1 ],[21.44 21.44 25.44 21.44 25.44 25.44 21.44 ],[0.931 0.946 0.973 ]);\nfprintf('" "','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'a'" ");\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('output',1,'\\bf{a + b}','texmode','on');" "\ncolor('black');disp('z^{-1}\\newline ','texmode','on');\ncolor('black');disp(' \\newline\\bf{}','texmode','on');" "\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "AddSub1" SID "66" Ports [2, 1] Position [490, 546, 520, 604] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/AddSub" SourceType "Xilinx Adder/Subtracter Block" mode "Subtraction" use_carryin off use_carryout off en off latency "1" precision "User Defined" arith_type "Signed (2's comp)" n_bits "17" bin_pt "14" quantization "Truncate" overflow "Flag as error" dbl_ovrd off use_behavioral_HDL off hw_selection "Fabric" pipelined off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "addsub" sg_icon_stat "30,58,2,1,white,blue,0,8a00a986,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 58 58 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 30 30 0 0 ],[0 0 58 58 0 ]);\npatch([6.1 11.88 15.88 19.88 23.88 15.88 10.1 6.1 ],[33.44 33.44 37.4" "4 33.44 37.44 37.44 37.44 33.44 ],[1 1 1 ]);\npatch([10.1 15.88 11.88 6.1 10.1 ],[29.44 29.44 33.44 33.44 29.44 ]," "[0.931 0.946 0.973 ]);\npatch([6.1 11.88 15.88 10.1 6.1 ],[25.44 25.44 29.44 29.44 25.44 ],[1 1 1 ]);\npatch([10.1" " 23.88 19.88 15.88 11.88 6.1 10.1 ],[21.44 21.44 25.44 21.44 25.44 25.44 21.44 ],[0.931 0.946 0.973 ]);\nfprintf('" "','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'a'" ");\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('output',1,'\\bf{a - b}','texmode','on');" "\ncolor('black');disp('z^{-1}\\newline ','texmode','on');\ncolor('black');disp(' \\newline\\bf{}','texmode','on');" "\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Delay" SID "67" Ports [1, 1] Position [430, 286, 465, 314] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flop." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en off latency "5" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" sg_icon_stat "35,28,1,1,white,blue,0,ec356abf,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 28 28 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 35 35 0 0 ],[0 0 28 28 0 ]);\npatch([8.1 13.88 17.88 21.88 25.88 17.88 12.1 8.1 ],[18.44 18.44 22.4" "4 18.44 22.44 22.44 22.44 18.44 ],[1 1 1 ]);\npatch([12.1 17.88 13.88 8.1 12.1 ],[14.44 14.44 18.44 18.44 14.44 ]," "[0.931 0.946 0.973 ]);\npatch([8.1 13.88 17.88 12.1 8.1 ],[10.44 10.44 14.44 14.44 10.44 ],[1 1 1 ]);\npatch([12.1" " 25.88 21.88 17.88 13.88 8.1 12.1 ],[6.44 6.44 10.44 6.44 10.44 10.44 6.44 ],[0.931 0.946 0.973 ]);\nfprintf('','C" "OMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');disp('z^{-5}','texmode'," "'on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Mult" SID "68" Ports [2, 1] Position [360, 334, 395, 396] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Mult" SourceType "Xilinx Multiplier Block" infoedit "Hardware notes: To check for the optimum internal pipeline stages of the dedicated multiplier you mus" "t select 'Test for optimum pipelining'.

Optimization Goal: For implementation into device fabric (LUTs), th" "e Speed or Area optimization will take effect only if it's supported by IP for the particular device family. Other" "wise, the results will be identical regardless of the selection." precision "User Defined" arith_type "Signed (2's comp)" n_bits "16" bin_pt "14" quantization "Truncate" overflow "Flag as error" en off latency "3" dbl_ovrd off use_behavioral_HDL off opt "Speed" use_embedded on optimum_pipeline on xl_use_area off xl_area "[0,0,0,0,0,0,0]" pipeline "on" use_rpm "on" placement_style "Triangular" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "mult" sg_icon_stat "35,62,2,1,white,blue,0,7028354c,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 62 62 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 35 35 0 0 ],[0 0 62 62 0 ]);\npatch([5.875 13.1 18.1 23.1 28.1 18.1 10.875 5.875 ],[36.55 36.55 41." "55 36.55 41.55 41.55 41.55 36.55 ],[1 1 1 ]);\npatch([10.875 18.1 13.1 5.875 10.875 ],[31.55 31.55 36.55 36.55 31." "55 ],[0.931 0.946 0.973 ]);\npatch([5.875 13.1 18.1 10.875 5.875 ],[26.55 26.55 31.55 31.55 26.55 ],[1 1 1 ]);\npa" "tch([10.875 28.1 23.1 18.1 13.1 5.875 10.875 ],[21.55 21.55 26.55 21.55 26.55 26.55 21.55 ],[0.931 0.946 0.973 ]);" "\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('i" "nput',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('output',1,'\\bfa \\times b','" "texmode','on');\ncolor('black');disp('z^{-3}\\newline ','texmode','on');\ncolor('black');disp(' \\n ');\nfprintf('" "','COMMENT: end icon text');" } Block { BlockType Reference Name "Mult1" SID "14844" Ports [2, 1] Position [360, 419, 395, 481] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Mult" SourceType "Xilinx Multiplier Block" infoedit "Hardware notes: To check for the optimum internal pipeline stages of the dedicated multiplier you mus" "t select 'Test for optimum pipelining'.

Optimization Goal: For implementation into device fabric (LUTs), th" "e Speed or Area optimization will take effect only if it's supported by IP for the particular device family. Other" "wise, the results will be identical regardless of the selection." precision "User Defined" arith_type "Signed (2's comp)" n_bits "16" bin_pt "14" quantization "Truncate" overflow "Flag as error" en off latency "3" dbl_ovrd off use_behavioral_HDL off opt "Speed" use_embedded on optimum_pipeline on xl_use_area off xl_area "[0,0,0,0,0,0,0]" pipeline "on" use_rpm "on" placement_style "Triangular" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "mult" sg_icon_stat "35,62,2,1,white,blue,0,7028354c,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 62 62 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 35 35 0 0 ],[0 0 62 62 0 ]);\npatch([5.875 13.1 18.1 23.1 28.1 18.1 10.875 5.875 ],[36.55 36.55 41." "55 36.55 41.55 41.55 41.55 36.55 ],[1 1 1 ]);\npatch([10.875 18.1 13.1 5.875 10.875 ],[31.55 31.55 36.55 36.55 31." "55 ],[0.931 0.946 0.973 ]);\npatch([5.875 13.1 18.1 10.875 5.875 ],[26.55 26.55 31.55 31.55 26.55 ],[1 1 1 ]);\npa" "tch([10.875 28.1 23.1 18.1 13.1 5.875 10.875 ],[21.55 21.55 26.55 21.55 26.55 26.55 21.55 ],[0.931 0.946 0.973 ]);" "\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('i" "nput',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('output',1,'\\bfa \\times b','" "texmode','on');\ncolor('black');disp('z^{-3}\\newline ','texmode','on');\ncolor('black');disp(' \\n ');\nfprintf('" "','COMMENT: end icon text');" } Block { BlockType Reference Name "Mult2" SID "14845" Ports [2, 1] Position [360, 529, 395, 591] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Mult" SourceType "Xilinx Multiplier Block" infoedit "Hardware notes: To check for the optimum internal pipeline stages of the dedicated multiplier you mus" "t select 'Test for optimum pipelining'.

Optimization Goal: For implementation into device fabric (LUTs), th" "e Speed or Area optimization will take effect only if it's supported by IP for the particular device family. Other" "wise, the results will be identical regardless of the selection." precision "User Defined" arith_type "Signed (2's comp)" n_bits "16" bin_pt "14" quantization "Truncate" overflow "Flag as error" en off latency "3" dbl_ovrd off use_behavioral_HDL off opt "Speed" use_embedded on optimum_pipeline on xl_use_area off xl_area "[0,0,0,0,0,0,0]" pipeline "on" use_rpm "on" placement_style "Triangular" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "mult" sg_icon_stat "35,62,2,1,white,blue,0,7028354c,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 62 62 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 35 35 0 0 ],[0 0 62 62 0 ]);\npatch([5.875 13.1 18.1 23.1 28.1 18.1 10.875 5.875 ],[36.55 36.55 41." "55 36.55 41.55 41.55 41.55 36.55 ],[1 1 1 ]);\npatch([10.875 18.1 13.1 5.875 10.875 ],[31.55 31.55 36.55 36.55 31." "55 ],[0.931 0.946 0.973 ]);\npatch([5.875 13.1 18.1 10.875 5.875 ],[26.55 26.55 31.55 31.55 26.55 ],[1 1 1 ]);\npa" "tch([10.875 28.1 23.1 18.1 13.1 5.875 10.875 ],[21.55 21.55 26.55 21.55 26.55 26.55 21.55 ],[0.931 0.946 0.973 ]);" "\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('i" "nput',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('output',1,'\\bfa \\times b','" "texmode','on');\ncolor('black');disp('z^{-3}\\newline ','texmode','on');\ncolor('black');disp(' \\n ');\nfprintf('" "','COMMENT: end icon text');" } Block { BlockType Reference Name "Mult3" SID "14846" Ports [2, 1] Position [360, 599, 395, 661] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Mult" SourceType "Xilinx Multiplier Block" infoedit "Hardware notes: To check for the optimum internal pipeline stages of the dedicated multiplier you mus" "t select 'Test for optimum pipelining'.

Optimization Goal: For implementation into device fabric (LUTs), th" "e Speed or Area optimization will take effect only if it's supported by IP for the particular device family. Other" "wise, the results will be identical regardless of the selection." precision "User Defined" arith_type "Signed (2's comp)" n_bits "16" bin_pt "14" quantization "Truncate" overflow "Flag as error" en off latency "3" dbl_ovrd off use_behavioral_HDL off opt "Speed" use_embedded on optimum_pipeline on xl_use_area off xl_area "[0,0,0,0,0,0,0]" pipeline "on" use_rpm "on" placement_style "Triangular" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "mult" sg_icon_stat "35,62,2,1,white,blue,0,7028354c,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 62 62 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 35 35 0 0 ],[0 0 62 62 0 ]);\npatch([5.875 13.1 18.1 23.1 28.1 18.1 10.875 5.875 ],[36.55 36.55 41." "55 36.55 41.55 41.55 41.55 36.55 ],[1 1 1 ]);\npatch([10.875 18.1 13.1 5.875 10.875 ],[31.55 31.55 36.55 36.55 31." "55 ],[0.931 0.946 0.973 ]);\npatch([5.875 13.1 18.1 10.875 5.875 ],[26.55 26.55 31.55 31.55 26.55 ],[1 1 1 ]);\npa" "tch([10.875 28.1 23.1 18.1 13.1 5.875 10.875 ],[21.55 21.55 26.55 21.55 26.55 26.55 21.55 ],[0.931 0.946 0.973 ]);" "\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('i" "nput',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('output',1,'\\bfa \\times b','" "texmode','on');\ncolor('black');disp('z^{-3}\\newline ','texmode','on');\ncolor('black');disp(' \\n ');\nfprintf('" "','COMMENT: end icon text');" } Block { BlockType Reference Name "Register1" SID "72" Ports [2, 1] Position [230, 333, 260, 362] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "30,29,2,1,white,blue,0,6bd0930c,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 29 29 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 30 30 0 0 ],[0 0 29 29 0 ]);\npatch([6.1 11.88 15.88 19.88 23.88 15.88 10.1 6.1 ],[18.44 18.44 22.4" "4 18.44 22.44 22.44 22.44 18.44 ],[1 1 1 ]);\npatch([10.1 15.88 11.88 6.1 10.1 ],[14.44 14.44 18.44 18.44 14.44 ]," "[0.931 0.946 0.973 ]);\npatch([6.1 11.88 15.88 10.1 6.1 ],[10.44 10.44 14.44 14.44 10.44 ],[1 1 1 ]);\npatch([10.1" " 23.88 19.88 15.88 11.88 6.1 10.1 ],[6.44 6.44 10.44 6.44 10.44 10.44 6.44 ],[0.931 0.946 0.973 ]);\nfprintf('','C" "OMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'d');\n" "color('black');port_label('input',2,'en');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1" "}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register2" SID "73" Ports [2, 1] Position [230, 363, 260, 392] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "30,29,2,1,white,blue,0,6bd0930c,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 29 29 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 30 30 0 0 ],[0 0 29 29 0 ]);\npatch([6.1 11.88 15.88 19.88 23.88 15.88 10.1 6.1 ],[18.44 18.44 22.4" "4 18.44 22.44 22.44 22.44 18.44 ],[1 1 1 ]);\npatch([10.1 15.88 11.88 6.1 10.1 ],[14.44 14.44 18.44 18.44 14.44 ]," "[0.931 0.946 0.973 ]);\npatch([6.1 11.88 15.88 10.1 6.1 ],[10.44 10.44 14.44 14.44 10.44 ],[1 1 1 ]);\npatch([10.1" " 23.88 19.88 15.88 11.88 6.1 10.1 ],[6.44 6.44 10.44 6.44 10.44 10.44 6.44 ],[0.931 0.946 0.973 ]);\nfprintf('','C" "OMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'d');\n" "color('black');port_label('input',2,'en');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1" "}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register3" SID "74" Ports [2, 1] Position [230, 418, 260, 447] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "30,29,2,1,white,blue,0,6bd0930c,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 29 29 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 30 30 0 0 ],[0 0 29 29 0 ]);\npatch([6.1 11.88 15.88 19.88 23.88 15.88 10.1 6.1 ],[18.44 18.44 22.4" "4 18.44 22.44 22.44 22.44 18.44 ],[1 1 1 ]);\npatch([10.1 15.88 11.88 6.1 10.1 ],[14.44 14.44 18.44 18.44 14.44 ]," "[0.931 0.946 0.973 ]);\npatch([6.1 11.88 15.88 10.1 6.1 ],[10.44 10.44 14.44 14.44 10.44 ],[1 1 1 ]);\npatch([10.1" " 23.88 19.88 15.88 11.88 6.1 10.1 ],[6.44 6.44 10.44 6.44 10.44 10.44 6.44 ],[0.931 0.946 0.973 ]);\nfprintf('','C" "OMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'d');\n" "color('black');port_label('input',2,'en');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1" "}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register4" SID "75" Ports [2, 1] Position [230, 448, 260, 477] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "30,29,2,1,white,blue,0,6bd0930c,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 29 29 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 30 30 0 0 ],[0 0 29 29 0 ]);\npatch([6.1 11.88 15.88 19.88 23.88 15.88 10.1 6.1 ],[18.44 18.44 22.4" "4 18.44 22.44 22.44 22.44 18.44 ],[1 1 1 ]);\npatch([10.1 15.88 11.88 6.1 10.1 ],[14.44 14.44 18.44 18.44 14.44 ]," "[0.931 0.946 0.973 ]);\npatch([6.1 11.88 15.88 10.1 6.1 ],[10.44 10.44 14.44 14.44 10.44 ],[1 1 1 ]);\npatch([10.1" " 23.88 19.88 15.88 11.88 6.1 10.1 ],[6.44 6.44 10.44 6.44 10.44 10.44 6.44 ],[0.931 0.946 0.973 ]);\nfprintf('','C" "OMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'d');\n" "color('black');port_label('input',2,'en');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1" "}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Outport Name " Valid" SID "76" Position [815, 293, 845, 307] IconDisplay "Port number" } Block { BlockType Outport Name " I" SID "77" Position [630, 373, 660, 387] Port "2" IconDisplay "Port number" } Block { BlockType Outport Name " Q" SID "78" Position [630, 568, 660, 582] Port "3" IconDisplay "Port number" } Line { SrcBlock "B Q" SrcPort 1 DstBlock "Register4" DstPort 1 } Line { SrcBlock "Valid" SrcPort 1 Points [15, 0] Branch { DstBlock "Delay" DstPort 1 } Branch { Points [0, 55] Branch { DstBlock "Register1" DstPort 2 } Branch { Points [0, 30] Branch { DstBlock "Register2" DstPort 2 } Branch { Points [0, 55] Branch { DstBlock "Register3" DstPort 2 } Branch { Points [0, 30] DstBlock "Register4" DstPort 2 } } } } } Line { SrcBlock "A I" SrcPort 1 DstBlock "Register1" DstPort 1 } Line { SrcBlock "B I" SrcPort 1 DstBlock "Register2" DstPort 1 } Line { SrcBlock "Mult" SrcPort 1 DstBlock "AddSub" DstPort 1 } Line { SrcBlock "Mult1" SrcPort 1 Points [15, 0; 0, -55] DstBlock "AddSub" DstPort 2 } Line { SrcBlock "AddSub" SrcPort 1 DstBlock " I" DstPort 1 } Line { SrcBlock "Delay" SrcPort 1 DstBlock " Valid" DstPort 1 } Line { SrcBlock "AddSub1" SrcPort 1 DstBlock " Q" DstPort 1 } Line { SrcBlock "Register1" SrcPort 1 Points [65, 0] Branch { DstBlock "Mult" DstPort 1 } Branch { Points [0, 195] DstBlock "Mult2" DstPort 1 } } Line { SrcBlock "Register2" SrcPort 1 Points [50, 0] Branch { DstBlock "Mult" DstPort 2 } Branch { Points [0, 235] DstBlock "Mult3" DstPort 1 } } Line { SrcBlock "Register3" SrcPort 1 Points [40, 0] Branch { DstBlock "Mult1" DstPort 1 } Branch { Points [0, 210] DstBlock "Mult3" DstPort 2 } } Line { SrcBlock "Register4" SrcPort 1 Points [60, 0] Branch { DstBlock "Mult1" DstPort 2 } Branch { Points [0, 110] DstBlock "Mult2" DstPort 2 } } Line { SrcBlock "A Q" SrcPort 1 DstBlock "Register3" DstPort 1 } Line { SrcBlock "Mult2" SrcPort 1 DstBlock "AddSub1" DstPort 1 } Line { SrcBlock "Mult3" SrcPort 1 Points [35, 0; 0, -40] DstBlock "AddSub1" DstPort 2 } } } Block { BlockType Reference Name "Constant" SID "9539" Ports [0, 1] Position [1335, 627, 1390, 653] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "-1e-4" gui_display_data_type "Fixed-point" arith_type "Signed (2's comp)" n_bits "21" bin_pt "20" preci_type "Single" exp_width "8" frac_width "24" explicit_period on period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" sg_icon_stat "55,26,0,1,white,blue,0,cd5eb3c2,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 55 55 0 0 ],[0 0 26 26 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 55 55 0 0 ],[0 0 26 26 0 ]);\npatch([20.325 24.66 27.66 30.66 33.66 27.66 23.325 20.325 ]" ",[16.33 16.33 19.33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([23.325 27.66 24.66 20.325 23.325 ],[13.3" "3 13.33 16.33 16.33 13.33 ],[0.931 0.946 0.973 ]);\npatch([20.325 24.66 27.66 23.325 20.325 ],[10.33 10.33 13.3" "3 13.33 10.33 ],[1 1 1 ]);\npatch([23.325 33.66 30.66 27.66 24.66 20.325 23.325 ],[7.33 7.33 10.33 7.33 10.33 1" "0.33 7.33 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon " "text');\ncolor('black');port_label('output',1,'-0.00010013580322265625');\nfprintf('','COMMENT: end icon text')" ";" } Block { BlockType Reference Name "Convert1" SID "15035" Ports [1, 1] Position [1250, 441, 1285, 459] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do" " not." gui_display_data_type "Fixed-point" arith_type "Signed (2's comp)" n_bits "21" bin_pt "13" float_type "Single" exp_bits "8" fraction_bits "24" quantization "Truncate" overflow "Flag as error" en off latency "0" dbl_ovrd off pipeline off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "convert" sg_icon_stat "35,18,1,1,white,blue,0,edca21da,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 18 18 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 18 18 0 ]);\npatch([12.55 15.44 17.44 19.44 21.44 17.44 14.55 12.55 ],[1" "1.22 11.22 13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([14.55 17.44 15.44 12.55 14.55 ],[9.22 9.22 " "11.22 11.22 9.22 ],[0.931 0.946 0.973 ]);\npatch([12.55 15.44 17.44 14.55 12.55 ],[7.22 7.22 9.22 9.22 7.22 ],[" "1 1 1 ]);\npatch([14.55 21.44 19.44 17.44 15.44 12.55 14.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.94" "6 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black" "');port_label('output',1,'cast');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Convert2" SID "79" Ports [1, 1] Position [1250, 546, 1285, 564] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do" " not." gui_display_data_type "Fixed-point" arith_type "Signed (2's comp)" n_bits "21" bin_pt "13" float_type "Single" exp_bits "8" fraction_bits "24" quantization "Truncate" overflow "Flag as error" en off latency "0" dbl_ovrd off pipeline off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "convert" sg_icon_stat "35,18,1,1,white,blue,0,edca21da,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 18 18 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 18 18 0 ]);\npatch([12.55 15.44 17.44 19.44 21.44 17.44 14.55 12.55 ],[1" "1.22 11.22 13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([14.55 17.44 15.44 12.55 14.55 ],[9.22 9.22 " "11.22 11.22 9.22 ],[0.931 0.946 0.973 ]);\npatch([12.55 15.44 17.44 14.55 12.55 ],[7.22 7.22 9.22 9.22 7.22 ],[" "1 1 1 ]);\npatch([14.55 21.44 19.44 17.44 15.44 12.55 14.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.94" "6 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black" "');port_label('output',1,'cast');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Delay" SID "14843" Ports [2, 1] Position [745, 541, 785, 579] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flo" "p." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en on latency "2" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" sg_icon_stat "40,38,2,1,white,blue,0,3e0a7e79,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 38 38 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 38 38 0 ]);\npatch([8.875 16.1 21.1 26.1 31.1 21.1 13.875 8.875 ],[24.55" " 24.55 29.55 24.55 29.55 29.55 29.55 24.55 ],[1 1 1 ]);\npatch([13.875 21.1 16.1 8.875 13.875 ],[19.55 19.55 24" ".55 24.55 19.55 ],[0.931 0.946 0.973 ]);\npatch([8.875 16.1 21.1 13.875 8.875 ],[14.55 14.55 19.55 19.55 14.55 " "],[1 1 1 ]);\npatch([13.875 31.1 26.1 21.1 16.1 8.875 13.875 ],[9.55 9.55 14.55 9.55 14.55 14.55 9.55 ],[0.931 " "0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('b" "lack');port_label('input',2,'en');\n\ncolor('black');disp('z^{-2}','texmode','on');\nfprintf('','COMMENT: end i" "con text');" } Block { BlockType Reference Name "Delay1" SID "81" Ports [2, 1] Position [395, 310, 430, 330] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flo" "p." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en on latency "64" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[7 14 0 14 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,20,2,1,white,blue,0,bf433b8b,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 20 20 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 20 20 0 ]);\npatch([12.55 15.44 17.44 19.44 21.44 17.44 14.55 12.55 ],[1" "2.22 12.22 14.22 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([14.55 17.44 15.44 12.55 14.55 ],[10.22 10.2" "2 12.22 12.22 10.22 ],[0.931 0.946 0.973 ]);\npatch([12.55 15.44 17.44 14.55 12.55 ],[8.22 8.22 10.22 10.22 8.2" "2 ],[1 1 1 ]);\npatch([14.55 21.44 19.44 17.44 15.44 12.55 14.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.931" " 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('" "black');port_label('input',2,'en');\n\ncolor('black');disp('z^{-64}','texmode','on');\nfprintf('','COMMENT: end" " icon text');" } Block { BlockType Reference Name "Delay2" SID "82" Ports [2, 1] Position [395, 280, 430, 300] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flo" "p." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en on latency "64" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[7 14 0 14 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,20,2,1,white,blue,0,bf433b8b,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 20 20 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 20 20 0 ]);\npatch([12.55 15.44 17.44 19.44 21.44 17.44 14.55 12.55 ],[1" "2.22 12.22 14.22 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([14.55 17.44 15.44 12.55 14.55 ],[10.22 10.2" "2 12.22 12.22 10.22 ],[0.931 0.946 0.973 ]);\npatch([12.55 15.44 17.44 14.55 12.55 ],[8.22 8.22 10.22 10.22 8.2" "2 ],[1 1 1 ]);\npatch([14.55 21.44 19.44 17.44 15.44 12.55 14.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.931" " 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('" "black');port_label('input',2,'en');\n\ncolor('black');disp('z^{-64}','texmode','on');\nfprintf('','COMMENT: end" " icon text');" } Block { BlockType From Name "From2" SID "84" Position [880, 616, 1010, 634] ShowName off CloseFcn "tagdialog Close" GotoTag "regRx_BYPASS_CFO_EST" TagVisibility "global" } Block { BlockType Reference Name "Gateway Out" SID "85" Ports [1, 1] Position [1195, 55, 1225, 65] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of t" "ype Simulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become t" "op level output ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "30,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 10 10 0 ],[0.88 0" ".88 0.88 ]);\nplot([0 30 30 0 0 ],[0 0 10 10 0 ]);\npatch([12.775 14.22 15.22 16.22 17.22 15.22 13.775 12.775 ]" ",[6.11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([13.775 15.22 14.22 12.775 13.775 ],[5.11 5.11 6." "11 6.11 5.11 ],[0.964 0.964 0.964 ]);\npatch([12.775 14.22 15.22 13.775 12.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1" " 1 1 ]);\npatch([13.775 17.22 16.22 15.22 14.22 12.775 13.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0." "964 0.964 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black" "');port_label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nf" "printf('','COMMENT: end icon text');" Port { PortNumber 1 Name "ADC I" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out1" SID "86" Ports [1, 1] Position [1195, 75, 1225, 85] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of t" "ype Simulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become t" "op level output ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "30,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 10 10 0 ],[0.88 0" ".88 0.88 ]);\nplot([0 30 30 0 0 ],[0 0 10 10 0 ]);\npatch([12.775 14.22 15.22 16.22 17.22 15.22 13.775 12.775 ]" ",[6.11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([13.775 15.22 14.22 12.775 13.775 ],[5.11 5.11 6." "11 6.11 5.11 ],[0.964 0.964 0.964 ]);\npatch([12.775 14.22 15.22 13.775 12.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1" " 1 1 ]);\npatch([13.775 17.22 16.22 15.22 14.22 12.775 13.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0." "964 0.964 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black" "');port_label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nf" "printf('','COMMENT: end icon text');" Port { PortNumber 1 Name "ADC Q" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out2" SID "87" Ports [1, 1] Position [1195, 95, 1225, 105] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of t" "ype Simulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become t" "op level output ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "30,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 10 10 0 ],[0.88 0" ".88 0.88 ]);\nplot([0 30 30 0 0 ],[0 0 10 10 0 ]);\npatch([12.775 14.22 15.22 16.22 17.22 15.22 13.775 12.775 ]" ",[6.11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([13.775 15.22 14.22 12.775 13.775 ],[5.11 5.11 6." "11 6.11 5.11 ],[0.964 0.964 0.964 ]);\npatch([12.775 14.22 15.22 13.775 12.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1" " 1 1 ]);\npatch([13.775 17.22 16.22 15.22 14.22 12.775 13.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0." "964 0.964 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black" "');port_label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nf" "printf('','COMMENT: end icon text');" Port { PortNumber 1 Name "Conj Prod I" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out3" SID "88" Ports [1, 1] Position [1195, 115, 1225, 125] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of t" "ype Simulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become t" "op level output ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "30,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 10 10 0 ],[0.88 0" ".88 0.88 ]);\nplot([0 30 30 0 0 ],[0 0 10 10 0 ]);\npatch([12.775 14.22 15.22 16.22 17.22 15.22 13.775 12.775 ]" ",[6.11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([13.775 15.22 14.22 12.775 13.775 ],[5.11 5.11 6." "11 6.11 5.11 ],[0.964 0.964 0.964 ]);\npatch([12.775 14.22 15.22 13.775 12.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1" " 1 1 ]);\npatch([13.775 17.22 16.22 15.22 14.22 12.775 13.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0." "964 0.964 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black" "');port_label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nf" "printf('','COMMENT: end icon text');" Port { PortNumber 1 Name "Conj Prod Q" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out4" SID "89" Ports [1, 1] Position [1195, 135, 1225, 145] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of t" "ype Simulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become t" "op level output ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "30,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 10 10 0 ],[0.88 0" ".88 0.88 ]);\nplot([0 30 30 0 0 ],[0 0 10 10 0 ]);\npatch([12.775 14.22 15.22 16.22 17.22 15.22 13.775 12.775 ]" ",[6.11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([13.775 15.22 14.22 12.775 13.775 ],[5.11 5.11 6." "11 6.11 5.11 ],[0.964 0.964 0.964 ]);\npatch([12.775 14.22 15.22 13.775 12.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1" " 1 1 ]);\npatch([13.775 17.22 16.22 15.22 14.22 12.775 13.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0." "964 0.964 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black" "');port_label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nf" "printf('','COMMENT: end icon text');" Port { PortNumber 1 Name "Sum I" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out5" SID "90" Ports [1, 1] Position [1195, 155, 1225, 165] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of t" "ype Simulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become t" "op level output ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "30,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 10 10 0 ],[0.88 0" ".88 0.88 ]);\nplot([0 30 30 0 0 ],[0 0 10 10 0 ]);\npatch([12.775 14.22 15.22 16.22 17.22 15.22 13.775 12.775 ]" ",[6.11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([13.775 15.22 14.22 12.775 13.775 ],[5.11 5.11 6." "11 6.11 5.11 ],[0.964 0.964 0.964 ]);\npatch([12.775 14.22 15.22 13.775 12.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1" " 1 1 ]);\npatch([13.775 17.22 16.22 15.22 14.22 12.775 13.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0." "964 0.964 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black" "');port_label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nf" "printf('','COMMENT: end icon text');" Port { PortNumber 1 Name "Sum Q" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out6" SID "91" Ports [1, 1] Position [1195, 175, 1225, 185] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of t" "ype Simulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become t" "op level output ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "30,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 10 10 0 ],[0.88 0" ".88 0.88 ]);\nplot([0 30 30 0 0 ],[0 0 10 10 0 ]);\npatch([12.775 14.22 15.22 16.22 17.22 15.22 13.775 12.775 ]" ",[6.11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([13.775 15.22 14.22 12.775 13.775 ],[5.11 5.11 6." "11 6.11 5.11 ],[0.964 0.964 0.964 ]);\npatch([12.775 14.22 15.22 13.775 12.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1" " 1 1 ]);\npatch([13.775 17.22 16.22 15.22 14.22 12.775 13.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0." "964 0.964 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black" "');port_label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nf" "printf('','COMMENT: end icon text');" Port { PortNumber 1 Name "Phase(Sum)" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out7" SID "92" Ports [1, 1] Position [1195, 195, 1225, 205] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of t" "ype Simulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become t" "op level output ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "30,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 10 10 0 ],[0.88 0" ".88 0.88 ]);\nplot([0 30 30 0 0 ],[0 0 10 10 0 ]);\npatch([12.775 14.22 15.22 16.22 17.22 15.22 13.775 12.775 ]" ",[6.11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([13.775 15.22 14.22 12.775 13.775 ],[5.11 5.11 6." "11 6.11 5.11 ],[0.964 0.964 0.964 ]);\npatch([12.775 14.22 15.22 13.775 12.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1" " 1 1 ]);\npatch([13.775 17.22 16.22 15.22 14.22 12.775 13.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0." "964 0.964 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black" "');port_label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nf" "printf('','COMMENT: end icon text');" Port { PortNumber 1 Name "LTS Sync" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out8" SID "93" Ports [1, 1] Position [1195, 215, 1225, 225] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of t" "ype Simulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become t" "op level output ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "30,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 10 10 0 ],[0.88 0" ".88 0.88 ]);\nplot([0 30 30 0 0 ],[0 0 10 10 0 ]);\npatch([12.775 14.22 15.22 16.22 17.22 15.22 13.775 12.775 ]" ",[6.11 6.11 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([13.775 15.22 14.22 12.775 13.775 ],[5.11 5.11 6." "11 6.11 5.11 ],[0.964 0.964 0.964 ]);\npatch([12.775 14.22 15.22 13.775 12.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1" " 1 1 ]);\npatch([13.775 17.22 16.22 15.22 14.22 12.775 13.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0." "964 0.964 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black" "');port_label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nf" "printf('','COMMENT: end icon text');" Port { PortNumber 1 Name "CFO Est Out" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Goto Name "Goto" SID "94" Position [1440, 440, 1575, 460] ZOrder -10 ShowName off GotoTag "regRx_CFO_Estimate" TagVisibility "global" } Block { BlockType Reference Name "Logical" SID "14919" Ports [2, 1] Position [1060, 602, 1090, 633] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "OR" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" sg_icon_stat "30,31,2,1,white,blue,0,7ede7d88,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 31 31 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 31 31 0 ]);\npatch([6.1 11.88 15.88 19.88 23.88 15.88 10.1 6.1 ],[19.44 " "19.44 23.44 19.44 23.44 23.44 23.44 19.44 ],[1 1 1 ]);\npatch([10.1 15.88 11.88 6.1 10.1 ],[15.44 15.44 19.44 1" "9.44 15.44 ],[0.931 0.946 0.973 ]);\npatch([6.1 11.88 15.88 10.1 6.1 ],[11.44 11.44 15.44 15.44 11.44 ],[1 1 1 " "]);\npatch([10.1 23.88 19.88 15.88 11.88 6.1 10.1 ],[7.44 7.44 11.44 7.44 11.44 11.44 7.44 ],[0.931 0.946 0.973" " ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\ncolor('black');" "disp('or');\nfprintf('','COMMENT: end icon text');" } Block { BlockType SubSystem Name "Phase" SID "95" Ports [3, 2] Position [830, 231, 905, 289] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "Phase" Location [1206, 455, 1593, 700] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "Valid" SID "96" Position [210, 228, 240, 242] IconDisplay "Port number" } Block { BlockType Inport Name "Re" SID "97" Position [95, 338, 125, 352] Port "2" IconDisplay "Port number" } Block { BlockType Inport Name "Im" SID "98" Position [95, 283, 125, 297] Port "3" IconDisplay "Port number" } Block { BlockType Reference Name "CORDIC 5.0 " SID "99" Ports [3, 2] Position [430, 207, 605, 373] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/CORDIC 5.0 " SourceType "Xilinx CORDIC 5.0 Block" infoedit "CORDIC 5.0" functional_selection "Arc_Tan" architectural_configuration "Parallel" pipelining_mode "Optimal" data_format "SignedFraction" phase_format "Scaled_Radians" input_width "18" output_width "18" round_mode "Truncate" iterations "0" precision "0" compensation_scaling "No_Scale_Compensation" coarse_rotation on aclken off aresetn off out_tready off cartesian_has_tuser off cartesian_has_tlast off cartesian_tuser_width "1" phase_has_tuser off phase_has_tlast off phase_tuser_width "1" out_tlast_behv "Null" flow_control "NonBlocking" optimize_goal "Performance" trim_axipin_name on xl_use_area off xl_area "[0,0,0,0,0,0,0]" ip_name "CORDIC" ip_version "5.0" dsptool_ready "true" ipcore_usecache "true" ipcore_useipmodelcache "true" wrapper_available "true" port_translation_map "{ 'aclken' => 'en', 'aresetn' => 'rst' }" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "cordic_v5_0" sg_icon_stat "175,166,3,2,white,blue,0,219bdc80,right,,[2 2 2 ],[3 3 ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 0 3 3 ],[157 9 9 157 ],[5.466667e-001 5.8" "00000e-001 6.400000e-001 ]);\npatch([172 172 175 175 ],[152 9 9 152 ],[3.233333e-001 3.400000e-001 3.700000e-001 ]" ");\npatch([3 171 171 3 3 ],[0 0 166 166 0 ],[7.700000e-001 8.200000e-001 9.100000e-001 ]);\nplot([3 171 171 3 3 ]," "[0 0 166 166 0 ]);\n\n\npatch([35.825 69.06 92.06 115.06 138.06 92.06 58.825 35.825 ],[108.53 108.53 131.53 108.53" " 131.53 131.53 131.53 108.53 ],[1 1 1 ]);\npatch([58.825 92.06 69.06 35.825 58.825 ],[85.53 85.53 108.53 108.53 85" ".53 ],[0.931 0.946 0.973 ]);\npatch([35.825 69.06 92.06 58.825 35.825 ],[62.53 62.53 85.53 85.53 62.53 ],[1 1 1 ])" ";\npatch([58.825 138.06 115.06 92.06 69.06 35.825 58.825 ],[39.53 39.53 62.53 39.53 62.53 62.53 39.53 ],[0.931 0.9" "46 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');p" "ort_label('input',1,' cartesian_tvalid ');\ncolor('black');port_label('input',2,' cartesian_tdata_imag ');\nco" "lor('black');port_label('input',3,' cartesian_tdata_real ');\ncolor('black');port_label('output',1,' dout_tvali" "d ');\ncolor('black');port_label('output',2,' dout_tdata_phase ');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Convert" SID "100" Ports [1, 1] Position [185, 281, 220, 299] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do not." gui_display_data_type "Fixed-point" arith_type "Signed (2's comp)" n_bits "18" bin_pt "12" float_type "Single" exp_bits "8" fraction_bits "24" quantization "Truncate" overflow "Wrap" en off latency "0" dbl_ovrd off pipeline off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "convert" sg_icon_stat "35,18,1,1,white,blue,0,edca21da,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 18 18 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 35 35 0 0 ],[0 0 18 18 0 ]);\npatch([12.55 15.44 17.44 19.44 21.44 17.44 14.55 12.55 ],[11.22 11.22" " 13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([14.55 17.44 15.44 12.55 14.55 ],[9.22 9.22 11.22 11.22 9" ".22 ],[0.931 0.946 0.973 ]);\npatch([12.55 15.44 17.44 14.55 12.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);\npatch" "([14.55 21.44 19.44 17.44 15.44 12.55 14.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\nfprint" "f('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('output'" ",1,'cast');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Convert1" SID "101" Ports [1, 1] Position [185, 336, 220, 354] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do not." gui_display_data_type "Fixed-point" arith_type "Signed (2's comp)" n_bits "18" bin_pt "12" float_type "Single" exp_bits "8" fraction_bits "24" quantization "Truncate" overflow "Wrap" en off latency "0" dbl_ovrd off pipeline off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "convert" sg_icon_stat "35,18,1,1,white,blue,0,edca21da,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 18 18 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 35 35 0 0 ],[0 0 18 18 0 ]);\npatch([12.55 15.44 17.44 19.44 21.44 17.44 14.55 12.55 ],[11.22 11.22" " 13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([14.55 17.44 15.44 12.55 14.55 ],[9.22 9.22 11.22 11.22 9" ".22 ],[0.931 0.946 0.973 ]);\npatch([12.55 15.44 17.44 14.55 12.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);\npatch" "([14.55 21.44 19.44 17.44 15.44 12.55 14.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\nfprint" "f('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('output'" ",1,'cast');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out" SID "102" Ports [1, 1] Position [670, 505, 700, 515] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type Sim" "ulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top level o" "utput ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "30,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 10 10 0 ],[0.88 0.88 0.8" "8 ]);\nplot([0 30 30 0 0 ],[0 0 10 10 0 ]);\npatch([12.775 14.22 15.22 16.22 17.22 15.22 13.775 12.775 ],[6.11 6.1" "1 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([13.775 15.22 14.22 12.775 13.775 ],[5.11 5.11 6.11 6.11 5.11 " "],[0.964 0.964 0.964 ]);\npatch([12.775 14.22 15.22 13.775 12.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]);\npatch(" "[13.775 17.22 16.22 15.22 14.22 12.775 13.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.964 ]);\nfpri" "ntf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input'," "1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf('','COMMENT: end i" "con text');" } Block { BlockType Reference Name "Gateway Out1" SID "103" Ports [1, 1] Position [670, 525, 700, 535] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type Sim" "ulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top level o" "utput ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "30,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 10 10 0 ],[0.88 0.88 0.8" "8 ]);\nplot([0 30 30 0 0 ],[0 0 10 10 0 ]);\npatch([12.775 14.22 15.22 16.22 17.22 15.22 13.775 12.775 ],[6.11 6.1" "1 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([13.775 15.22 14.22 12.775 13.775 ],[5.11 5.11 6.11 6.11 5.11 " "],[0.964 0.964 0.964 ]);\npatch([12.775 14.22 15.22 13.775 12.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]);\npatch(" "[13.775 17.22 16.22 15.22 14.22 12.775 13.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.964 ]);\nfpri" "ntf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input'," "1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf('','COMMENT: end i" "con text');" } Block { BlockType Reference Name "Gateway Out2" SID "104" Ports [1, 1] Position [670, 545, 700, 555] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type Sim" "ulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top level o" "utput ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "30,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 10 10 0 ],[0.88 0.88 0.8" "8 ]);\nplot([0 30 30 0 0 ],[0 0 10 10 0 ]);\npatch([12.775 14.22 15.22 16.22 17.22 15.22 13.775 12.775 ],[6.11 6.1" "1 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([13.775 15.22 14.22 12.775 13.775 ],[5.11 5.11 6.11 6.11 5.11 " "],[0.964 0.964 0.964 ]);\npatch([12.775 14.22 15.22 13.775 12.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]);\npatch(" "[13.775 17.22 16.22 15.22 14.22 12.775 13.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.964 ]);\nfpri" "ntf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input'," "1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf('','COMMENT: end i" "con text');" } Block { BlockType Reference Name "Gateway Out3" SID "105" Ports [1, 1] Position [670, 565, 700, 575] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type Sim" "ulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top level o" "utput ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "30,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 10 10 0 ],[0.88 0.88 0.8" "8 ]);\nplot([0 30 30 0 0 ],[0 0 10 10 0 ]);\npatch([12.775 14.22 15.22 16.22 17.22 15.22 13.775 12.775 ],[6.11 6.1" "1 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([13.775 15.22 14.22 12.775 13.775 ],[5.11 5.11 6.11 6.11 5.11 " "],[0.964 0.964 0.964 ]);\npatch([12.775 14.22 15.22 13.775 12.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]);\npatch(" "[13.775 17.22 16.22 15.22 14.22 12.775 13.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.964 ]);\nfpri" "ntf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input'," "1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf('','COMMENT: end i" "con text');" } Block { BlockType Reference Name "Gateway Out4" SID "106" Ports [1, 1] Position [670, 585, 700, 595] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type Sim" "ulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top level o" "utput ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "30,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 10 10 0 ],[0.88 0.88 0.8" "8 ]);\nplot([0 30 30 0 0 ],[0 0 10 10 0 ]);\npatch([12.775 14.22 15.22 16.22 17.22 15.22 13.775 12.775 ],[6.11 6.1" "1 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([13.775 15.22 14.22 12.775 13.775 ],[5.11 5.11 6.11 6.11 5.11 " "],[0.964 0.964 0.964 ]);\npatch([12.775 14.22 15.22 13.775 12.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]);\npatch(" "[13.775 17.22 16.22 15.22 14.22 12.775 13.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.964 ]);\nfpri" "ntf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input'," "1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf('','COMMENT: end i" "con text');" } Block { BlockType Reference Name "Gateway Out5" SID "107" Ports [1, 1] Position [670, 605, 700, 615] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type Sim" "ulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top level o" "utput ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "30,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 10 10 0 ],[0.88 0.88 0.8" "8 ]);\nplot([0 30 30 0 0 ],[0 0 10 10 0 ]);\npatch([12.775 14.22 15.22 16.22 17.22 15.22 13.775 12.775 ],[6.11 6.1" "1 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([13.775 15.22 14.22 12.775 13.775 ],[5.11 5.11 6.11 6.11 5.11 " "],[0.964 0.964 0.964 ]);\npatch([12.775 14.22 15.22 13.775 12.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]);\npatch(" "[13.775 17.22 16.22 15.22 14.22 12.775 13.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.964 ]);\nfpri" "ntf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input'," "1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf('','COMMENT: end i" "con text');" } Block { BlockType Reference Name "Gateway Out6" SID "108" Ports [1, 1] Position [670, 625, 700, 635] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type Sim" "ulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top level o" "utput ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "30,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 10 10 0 ],[0.88 0.88 0.8" "8 ]);\nplot([0 30 30 0 0 ],[0 0 10 10 0 ]);\npatch([12.775 14.22 15.22 16.22 17.22 15.22 13.775 12.775 ],[6.11 6.1" "1 7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([13.775 15.22 14.22 12.775 13.775 ],[5.11 5.11 6.11 6.11 5.11 " "],[0.964 0.964 0.964 ]);\npatch([12.775 14.22 15.22 13.775 12.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]);\npatch(" "[13.775 17.22 16.22 15.22 14.22 12.775 13.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.964 ]);\nfpri" "ntf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input'," "1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf('','COMMENT: end i" "con text');" } Block { BlockType Scope Name "Phase " SID "109" Ports [7] Position [765, 499, 795, 641] ZOrder -3 Floating off Location [97, 316, 1777, 1320] Open off NumInputPorts "7" ZoomMode "yonly" List { ListType AxesTitles axes1 "%" axes2 "%" axes3 "%" axes4 "%" axes5 "%" axes6 "%" axes7 "%" } TimeRange "10000" YMin "-2~-5~-2~-5~-0.4~-1~-1" YMax "4~15~4~15~0.4~2~1" SaveName "ScopeData35" DataFormat "StructureWithTime" LimitDataPoints off SampleTime "0" } Block { BlockType Reference Name "Scale" SID "110" Ports [1, 1] Position [305, 278, 340, 302] NamePlacement "alternate" ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Scale" SourceType "Xilinx Input Scaler Block" infoedit "Scales input by a power of two by adjusting the binary point position.

Hardware notes: In hard" "ware this block costs nothing." scale_factor "-4" dbl_ovrd off has_advanced_control "0" sggui_pos "20,20,336,191" block_type "scale" block_version "10.1.2" sg_icon_stat "35,24,1,1,white,blue,0,df643265,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 24 24 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 35 35 0 0 ],[0 0 24 24 0 ]);\npatch([10.325 14.66 17.66 20.66 23.66 17.66 13.325 10.325 ],[15.33 15" ".33 18.33 15.33 18.33 18.33 18.33 15.33 ],[1 1 1 ]);\npatch([13.325 17.66 14.66 10.325 13.325 ],[12.33 12.33 15.33" " 15.33 12.33 ],[0.931 0.946 0.973 ]);\npatch([10.325 14.66 17.66 13.325 10.325 ],[9.33 9.33 12.33 12.33 9.33 ],[1 " "1 1 ]);\npatch([13.325 23.66 20.66 17.66 14.66 10.325 13.325 ],[6.33 6.33 9.33 6.33 9.33 9.33 6.33 ],[0.931 0.946 " "0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');" "disp('\\bf{2^{-4}}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Scale1" SID "111" Ports [1, 1] Position [305, 333, 340, 357] NamePlacement "alternate" ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Scale" SourceType "Xilinx Input Scaler Block" infoedit "Scales input by a power of two by adjusting the binary point position.

Hardware notes: In hard" "ware this block costs nothing." scale_factor "-4" dbl_ovrd off has_advanced_control "0" sggui_pos "20,20,336,191" block_type "scale" block_version "10.1.2" sg_icon_stat "35,24,1,1,white,blue,0,df643265,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 24 24 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 35 35 0 0 ],[0 0 24 24 0 ]);\npatch([10.325 14.66 17.66 20.66 23.66 17.66 13.325 10.325 ],[15.33 15" ".33 18.33 15.33 18.33 18.33 18.33 15.33 ],[1 1 1 ]);\npatch([13.325 17.66 14.66 10.325 13.325 ],[12.33 12.33 15.33" " 15.33 12.33 ],[0.931 0.946 0.973 ]);\npatch([10.325 14.66 17.66 13.325 10.325 ],[9.33 9.33 12.33 12.33 9.33 ],[1 " "1 1 ]);\npatch([13.325 23.66 20.66 17.66 14.66 10.325 13.325 ],[6.33 6.33 9.33 6.33 9.33 9.33 6.33 ],[0.931 0.946 " "0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');" "disp('\\bf{2^{-4}}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Outport Name " Valid" SID "112" Position [680, 243, 710, 257] IconDisplay "Port number" } Block { BlockType Outport Name "Phase" SID "113" Position [680, 323, 710, 337] Port "2" IconDisplay "Port number" } Line { SrcBlock "Convert1" SrcPort 1 Points [35, 0] Branch { DstBlock "Scale1" DstPort 1 } Branch { Points [0, 225] DstBlock "Gateway Out3" DstPort 1 } } Line { SrcBlock "Valid" SrcPort 1 DstBlock "CORDIC 5.0 " DstPort 1 } Line { SrcBlock "CORDIC 5.0 " SrcPort 1 DstBlock " Valid" DstPort 1 } Line { SrcBlock "CORDIC 5.0 " SrcPort 2 Points [15, 0] Branch { DstBlock "Phase" DstPort 1 } Branch { Points [0, 300] DstBlock "Gateway Out6" DstPort 1 } } Line { SrcBlock "Convert" SrcPort 1 Points [45, 0] Branch { DstBlock "Scale" DstPort 1 } Branch { Points [0, 260] DstBlock "Gateway Out2" DstPort 1 } } Line { SrcBlock "Scale" SrcPort 1 Points [45, 0] Branch { DstBlock "CORDIC 5.0 " DstPort 2 } Branch { Points [0, 300] DstBlock "Gateway Out4" DstPort 1 } } Line { SrcBlock "Scale1" SrcPort 1 Points [40, 0] Branch { DstBlock "CORDIC 5.0 " DstPort 3 } Branch { Points [0, 265] DstBlock "Gateway Out5" DstPort 1 } } Line { SrcBlock "Im" SrcPort 1 Points [30, 0] Branch { DstBlock "Convert" DstPort 1 } Branch { Points [0, 220] DstBlock "Gateway Out" DstPort 1 } } Line { SrcBlock "Re" SrcPort 1 Points [25, 0] Branch { DstBlock "Convert1" DstPort 1 } Branch { Points [0, 185] DstBlock "Gateway Out1" DstPort 1 } } Line { SrcBlock "Gateway Out3" SrcPort 1 DstBlock "Phase " DstPort 4 } Line { SrcBlock "Gateway Out2" SrcPort 1 DstBlock "Phase " DstPort 3 } Line { SrcBlock "Gateway Out1" SrcPort 1 DstBlock "Phase " DstPort 2 } Line { SrcBlock "Gateway Out" SrcPort 1 DstBlock "Phase " DstPort 1 } Line { SrcBlock "Gateway Out4" SrcPort 1 DstBlock "Phase " DstPort 5 } Line { SrcBlock "Gateway Out5" SrcPort 1 DstBlock "Phase " DstPort 6 } Line { SrcBlock "Gateway Out6" SrcPort 1 DstBlock "Phase " DstPort 7 } } } Block { BlockType SubSystem Name "Posedge3" SID "114" Ports [1, 1] Position [865, 548, 920, 572] NamePlacement "alternate" MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "Posedge3" Location [88, 301, 2330, 1301] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "D" SID "115" Position [200, 253, 230, 267] IconDisplay "Port number" } Block { BlockType Reference Name "Delay" SID "116" Ports [1, 1] Position [425, 153, 460, 177] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flop. If r" "egister retiming is enabled, the delay line is a chain of flip-flops." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en off latency "1" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[1 1 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,24,1,1,white,blue,0,07b98262,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 24 24 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 35 35 0 0 ],[0 0 24 24 0 ]);\npatch([10.325 14.66 17.66 20.66 23.66 17.66 13.325 10.325 ],[15.33 15" ".33 18.33 15.33 18.33 18.33 18.33 15.33 ],[1 1 1 ]);\npatch([13.325 17.66 14.66 10.325 13.325 ],[12.33 12.33 15.33" " 15.33 12.33 ],[0.931 0.946 0.973 ]);\npatch([10.325 14.66 17.66 13.325 10.325 ],[9.33 9.33 12.33 12.33 9.33 ],[1 " "1 1 ]);\npatch([13.325 23.66 20.66 17.66 14.66 10.325 13.325 ],[6.33 6.33 9.33 6.33 9.33 9.33 6.33 ],[0.931 0.946 " "0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');" "disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Inverter" SID "117" Ports [1, 1] Position [490, 156, 515, 174] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Inverter" SourceType "Xilinx Inverter Block" infoedit "Bitwise logical negation (one's complement) operator." en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "inv" block_version "VER_STRING_GOES_HERE" sg_icon_stat "25,18,1,1,white,blue,0,267846e5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 18 18 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 25 25 0 0 ],[0 0 18 18 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[11.22 11.22 13" ".22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[9.22 9.22 11.22 11.22 9.22 ]," "[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);\npatch([9.55 16" ".44 14.44 12.44 10.44 7.55 9.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMEN" "T: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');disp('not');\nfprintf('','COM" "MENT: end icon text');" } Block { BlockType Reference Name "Logical1" SID "118" Ports [2, 1] Position [540, 151, 585, 204] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "AND" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "8" bin_pt "2" align_bp on dbl_ovrd off xl_use_area off xl_area "[1 0 0 1 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" block_version "VER_STRING_GOES_HERE" sg_icon_stat "45,53,2,1,white,blue,0,83a4b621,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 53 53 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 45 45 0 0 ],[0 0 53 53 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[32.66 32.66 3" "8.66 32.66 38.66 38.66 38.66 32.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[26.66 26.66 32.66 32.66 26" ".66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[20.66 20.66 26.66 26.66 20.66 ],[1 1 1 ]);\npa" "tch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[14.66 14.66 20.66 14.66 20.66 20.66 14.66 ],[0.931 0.946 0.973 ])" ";\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\ncolor('black');disp('" "and');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Outport Name "Q" SID "119" Position [610, 173, 640, 187] IconDisplay "Port number" } Line { SrcBlock "D" SrcPort 1 Points [150, 0; 0, -70] Branch { DstBlock "Logical1" DstPort 2 } Branch { Points [0, -25] DstBlock "Delay" DstPort 1 } } Line { SrcBlock "Logical1" SrcPort 1 DstBlock "Q" DstPort 1 } Line { SrcBlock "Inverter" SrcPort 1 DstBlock "Logical1" DstPort 1 } Line { SrcBlock "Delay" SrcPort 1 DstBlock "Inverter" DstPort 1 } Annotation { Name "Rising Edge Detection" Position [500, 112] } } } Block { BlockType Reference Name "Register" SID "120" Ports [3, 1] Position [1145, 516, 1190, 594] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst on en on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "45,78,3,1,white,blue,0,30546de1,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 78 78 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 45 45 0 0 ],[0 0 78 78 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[45." "66 45.66 51.66 45.66 51.66 51.66 51.66 45.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[39.66 39.66 4" "5.66 45.66 39.66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[33.66 33.66 39.66 39.66 33.66 " "],[1 1 1 ]);\npatch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[27.66 27.66 33.66 27.66 33.66 33.66 27.66 ],[0" ".931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor" "('black');port_label('input',1,'d');\ncolor('black');port_label('input',2,'rst');\ncolor('black');port_label('i" "nput',3,'en');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfpri" "ntf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register1" SID "14920" Ports [2, 1] Position [1145, 411, 1190, 489] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "45,78,2,1,white,blue,0,6bd0930c,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 78 78 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 45 45 0 0 ],[0 0 78 78 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[45." "66 45.66 51.66 45.66 51.66 51.66 51.66 45.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[39.66 39.66 4" "5.66 45.66 39.66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[33.66 33.66 39.66 39.66 33.66 " "],[1 1 1 ]);\npatch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[27.66 27.66 33.66 27.66 33.66 33.66 27.66 ],[0" ".931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor" "('black');port_label('input',1,'d');\ncolor('black');port_label('input',2,'en');\ncolor('black');port_label('ou" "tput',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType SubSystem Name "Running Sum" SID "121" Ports [2, 2] Position [610, 243, 675, 267] NamePlacement "alternate" MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "Running Sum" Location [227, 108, 1983, 1242] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "En" SID "122" Position [195, 183, 225, 197] IconDisplay "Port number" } Block { BlockType Inport Name "D" SID "123" Position [195, 123, 225, 137] Port "2" IconDisplay "Port number" } Block { BlockType Reference Name "Accum1" SID "124" Ports [2, 1] Position [485, 131, 535, 184] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Accumulator" SourceType "Xilinx Accumulator Block" infoedit "Adder or subtracter-based accumulator. Output type and binary point position match the input.
Hardware notes: When \"Reinitialize with input 'b' on reset\" is selected, the accumulator is forced to run at t" "he system rate even if the input 'b' is running at a slower rate." operation "Add" n_bits "25" overflow "Flag as error" scale "1" rst off infoeditControl "reset for floating point data type must be asserted for a minimum of 2 cycles" hasbypass off en on latency "0" dbl_ovrd off msb_inp "100" msb "100" lsb "-100" use_behavioral_HDL on implementation "Fabric" xl_use_area off xl_area "[12 23 0 22 0 0 0]" has_advanced_control "0" sggui_pos "20,20,367,457" block_type "accum" block_version "VER_STRING_GOES_HERE" sg_icon_stat "50,53,2,1,white,blue,0,debef366,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 50 50 0 0 ],[0 0 53 53 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 50 50 0 0 ],[0 0 53 53 0 ]);\npatch([9.425 19.54 26.54 33.54 40.54 26.54 16.425 9.425 ],[33.77 33.7" "7 40.77 33.77 40.77 40.77 40.77 33.77 ],[1 1 1 ]);\npatch([16.425 26.54 19.54 9.425 16.425 ],[26.77 26.77 33.77 33" ".77 26.77 ],[0.931 0.946 0.973 ]);\npatch([9.425 19.54 26.54 16.425 9.425 ],[19.77 19.77 26.77 26.77 19.77 ],[1 1 " "1 ]);\npatch([16.425 40.54 33.54 26.54 19.54 9.425 16.425 ],[12.77 12.77 19.77 12.77 19.77 19.77 12.77 ],[0.931 0." "946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');" "port_label('input',1,'b');\ncolor('black');port_label('input',2,'en');\ncolor('black');port_label('output',1,'\\bf" "+=b','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "AddSub1" SID "125" Ports [2, 1] Position [360, 117, 410, 168] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/AddSub" SourceType "Xilinx Adder/Subtracter Block" mode "Subtraction" use_carryin off use_carryout off en off latency "1" precision "Full" arith_type "Signed (2's comp)" n_bits "36" bin_pt "28" quantization "Truncate" overflow "Saturate" dbl_ovrd off use_behavioral_HDL on hw_selection "Fabric" pipelined off xl_use_area off xl_area "[9 18 0 17 0 0 0]" use_rpm "off" has_advanced_control "0" sggui_pos "20,20,348,344" block_type "addsub" block_version "VER_STRING_GOES_HERE" sg_icon_stat "50,51,2,1,white,blue,0,8a00a986,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 50 50 0 0 ],[0 0 51 51 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 50 50 0 0 ],[0 0 51 51 0 ]);\npatch([9.425 19.54 26.54 33.54 40.54 26.54 16.425 9.425 ],[32.77 32.7" "7 39.77 32.77 39.77 39.77 39.77 32.77 ],[1 1 1 ]);\npatch([16.425 26.54 19.54 9.425 16.425 ],[25.77 25.77 32.77 32" ".77 25.77 ],[0.931 0.946 0.973 ]);\npatch([9.425 19.54 26.54 16.425 9.425 ],[18.77 18.77 25.77 25.77 18.77 ],[1 1 " "1 ]);\npatch([16.425 40.54 33.54 26.54 19.54 9.425 16.425 ],[11.77 11.77 18.77 11.77 18.77 18.77 11.77 ],[0.931 0." "946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');" "port_label('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('output',1,'\\bf{" "a - b}','texmode','on');\ncolor('black');disp('z^{-1}\\newline ','texmode','on');\ncolor('black');disp(' \\newline" "\\bf{}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Delay" SID "126" Ports [1, 1] Position [375, 178, 400, 202] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flop." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en off latency "1" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[7 14 0 14 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" block_version "VER_STRING_GOES_HERE" sg_icon_stat "25,24,1,1,white,blue,0,07b98262,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 24 24 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 25 25 0 0 ],[0 0 24 24 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[15.33 15.33 " "18.33 15.33 18.33 18.33 18.33 15.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[12.33 12.33 15.33 15.33 1" "2.33 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[9.33 9.33 12.33 12.33 9.33 ],[1 1 1 ]);\npat" "ch([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[6.33 6.33 9.33 6.33 9.33 9.33 6.33 ],[0.931 0.946 0.973 ]);\nfprin" "tf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');disp('z^{-1}','t" "exmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Delay1" SID "127" Ports [1, 1] Position [495, 198, 520, 222] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flop." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en off latency "1" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[7 14 0 14 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" block_version "VER_STRING_GOES_HERE" sg_icon_stat "25,24,1,1,white,blue,0,07b98262,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 24 24 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 25 25 0 0 ],[0 0 24 24 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[15.33 15.33 " "18.33 15.33 18.33 18.33 18.33 15.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[12.33 12.33 15.33 15.33 1" "2.33 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[9.33 9.33 12.33 12.33 9.33 ],[1 1 1 ]);\npat" "ch([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[6.33 6.33 9.33 6.33 9.33 9.33 6.33 ],[0.931 0.946 0.973 ]);\nfprin" "tf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');disp('z^{-1}','t" "exmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Delay2" SID "128" Ports [1, 1] Position [605, 198, 630, 222] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flop." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en off latency "1" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[7 14 0 14 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" block_version "VER_STRING_GOES_HERE" sg_icon_stat "25,24,1,1,white,blue,0,07b98262,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 24 24 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 25 25 0 0 ],[0 0 24 24 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[15.33 15.33 " "18.33 15.33 18.33 18.33 18.33 15.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[12.33 12.33 15.33 15.33 1" "2.33 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[9.33 9.33 12.33 12.33 9.33 ],[1 1 1 ]);\npat" "ch([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[6.33 6.33 9.33 6.33 9.33 9.33 6.33 ],[0.931 0.946 0.973 ]);\nfprin" "tf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');disp('z^{-1}','t" "exmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Delay6" SID "129" Ports [2, 1] Position [265, 143, 300, 167] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flop." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en on latency "64" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[9 17 0 17 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,24,2,1,white,blue,0,bf433b8b,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 24 24 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 35 35 0 0 ],[0 0 24 24 0 ]);\npatch([10.325 14.66 17.66 20.66 23.66 17.66 13.325 10.325 ],[15.33 15" ".33 18.33 15.33 18.33 18.33 18.33 15.33 ],[1 1 1 ]);\npatch([13.325 17.66 14.66 10.325 13.325 ],[12.33 12.33 15.33" " 15.33 12.33 ],[0.931 0.946 0.973 ]);\npatch([10.325 14.66 17.66 13.325 10.325 ],[9.33 9.33 12.33 12.33 9.33 ],[1 " "1 1 ]);\npatch([13.325 23.66 20.66 17.66 14.66 10.325 13.325 ],[6.33 6.33 9.33 6.33 9.33 9.33 6.33 ],[0.931 0.946 " "0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');po" "rt_label('input',2,'en');\n\ncolor('black');disp('z^{-64}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register" SID "130" Ports [1, 1] Position [600, 142, 635, 178] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "35,36,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 36 36 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 35 35 0 0 ],[0 0 36 36 0 ]);\npatch([5.875 13.1 18.1 23.1 28.1 18.1 10.875 5.875 ],[23.55 23.55 28." "55 23.55 28.55 28.55 28.55 23.55 ],[1 1 1 ]);\npatch([10.875 18.1 13.1 5.875 10.875 ],[18.55 18.55 23.55 23.55 18." "55 ],[0.931 0.946 0.973 ]);\npatch([5.875 13.1 18.1 10.875 5.875 ],[13.55 13.55 18.55 18.55 13.55 ],[1 1 1 ]);\npa" "tch([10.875 28.1 23.1 18.1 13.1 5.875 10.875 ],[8.55 8.55 13.55 8.55 13.55 13.55 8.55 ],[0.931 0.946 0.973 ]);\nfp" "rintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input" "',1,'d');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','" "COMMENT: end icon text');" } Block { BlockType Outport Name "Valid" SID "131" Position [710, 203, 740, 217] IconDisplay "Port number" } Block { BlockType Outport Name "Sum" SID "132" Position [710, 153, 740, 167] Port "2" IconDisplay "Port number" } Line { SrcBlock "Delay6" SrcPort 1 DstBlock "AddSub1" DstPort 2 } Line { SrcBlock "AddSub1" SrcPort 1 DstBlock "Accum1" DstPort 1 } Line { SrcBlock "D" SrcPort 1 Points [0, 0; 15, 0] Branch { DstBlock "AddSub1" DstPort 1 } Branch { Points [0, 20] DstBlock "Delay6" DstPort 1 } } Line { SrcBlock "Accum1" SrcPort 1 DstBlock "Register" DstPort 1 } Line { SrcBlock "Register" SrcPort 1 DstBlock "Sum" DstPort 1 } Line { SrcBlock "En" SrcPort 1 Points [10, 0] Branch { Points [0, -30] DstBlock "Delay6" DstPort 2 } Branch { DstBlock "Delay" DstPort 1 } } Line { SrcBlock "Delay" SrcPort 1 Points [50, 0] Branch { Points [0, -20] DstBlock "Accum1" DstPort 2 } Branch { Points [0, 20] DstBlock "Delay1" DstPort 1 } } Line { SrcBlock "Delay1" SrcPort 1 DstBlock "Delay2" DstPort 1 } Line { SrcBlock "Delay2" SrcPort 1 DstBlock "Valid" DstPort 1 } } } Block { BlockType SubSystem Name "Running Sum1" SID "133" Ports [2, 2] Position [610, 298, 675, 322] NamePlacement "alternate" MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "Running Sum1" Location [442, 320, 2429, 1372] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "En" SID "134" Position [195, 183, 225, 197] IconDisplay "Port number" } Block { BlockType Inport Name "D" SID "135" Position [195, 123, 225, 137] Port "2" IconDisplay "Port number" } Block { BlockType Reference Name "Accum1" SID "136" Ports [2, 1] Position [485, 131, 535, 184] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Accumulator" SourceType "Xilinx Accumulator Block" infoedit "Adder or subtracter-based accumulator. Output type and binary point position match the input.
Hardware notes: When \"Reinitialize with input 'b' on reset\" is selected, the accumulator is forced to run at t" "he system rate even if the input 'b' is running at a slower rate." operation "Add" n_bits "25" overflow "Flag as error" scale "1" rst off infoeditControl "reset for floating point data type must be asserted for a minimum of 2 cycles" hasbypass off en on latency "0" dbl_ovrd off msb_inp "100" msb "100" lsb "-100" use_behavioral_HDL on implementation "Fabric" xl_use_area off xl_area "[12 23 0 22 0 0 0]" has_advanced_control "0" sggui_pos "20,20,367,457" block_type "accum" block_version "VER_STRING_GOES_HERE" sg_icon_stat "50,53,2,1,white,blue,0,debef366,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 50 50 0 0 ],[0 0 53 53 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 50 50 0 0 ],[0 0 53 53 0 ]);\npatch([9.425 19.54 26.54 33.54 40.54 26.54 16.425 9.425 ],[33.77 33.7" "7 40.77 33.77 40.77 40.77 40.77 33.77 ],[1 1 1 ]);\npatch([16.425 26.54 19.54 9.425 16.425 ],[26.77 26.77 33.77 33" ".77 26.77 ],[0.931 0.946 0.973 ]);\npatch([9.425 19.54 26.54 16.425 9.425 ],[19.77 19.77 26.77 26.77 19.77 ],[1 1 " "1 ]);\npatch([16.425 40.54 33.54 26.54 19.54 9.425 16.425 ],[12.77 12.77 19.77 12.77 19.77 19.77 12.77 ],[0.931 0." "946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');" "port_label('input',1,'b');\ncolor('black');port_label('input',2,'en');\ncolor('black');port_label('output',1,'\\bf" "+=b','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "AddSub1" SID "137" Ports [2, 1] Position [360, 117, 410, 168] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/AddSub" SourceType "Xilinx Adder/Subtracter Block" mode "Subtraction" use_carryin off use_carryout off en off latency "1" precision "Full" arith_type "Signed (2's comp)" n_bits "36" bin_pt "28" quantization "Truncate" overflow "Saturate" dbl_ovrd off use_behavioral_HDL on hw_selection "Fabric" pipelined off xl_use_area off xl_area "[9 18 0 17 0 0 0]" use_rpm "off" has_advanced_control "0" sggui_pos "20,20,348,344" block_type "addsub" block_version "VER_STRING_GOES_HERE" sg_icon_stat "50,51,2,1,white,blue,0,8a00a986,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 50 50 0 0 ],[0 0 51 51 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 50 50 0 0 ],[0 0 51 51 0 ]);\npatch([9.425 19.54 26.54 33.54 40.54 26.54 16.425 9.425 ],[32.77 32.7" "7 39.77 32.77 39.77 39.77 39.77 32.77 ],[1 1 1 ]);\npatch([16.425 26.54 19.54 9.425 16.425 ],[25.77 25.77 32.77 32" ".77 25.77 ],[0.931 0.946 0.973 ]);\npatch([9.425 19.54 26.54 16.425 9.425 ],[18.77 18.77 25.77 25.77 18.77 ],[1 1 " "1 ]);\npatch([16.425 40.54 33.54 26.54 19.54 9.425 16.425 ],[11.77 11.77 18.77 11.77 18.77 18.77 11.77 ],[0.931 0." "946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');" "port_label('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('output',1,'\\bf{" "a - b}','texmode','on');\ncolor('black');disp('z^{-1}\\newline ','texmode','on');\ncolor('black');disp(' \\newline" "\\bf{}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Delay" SID "138" Ports [1, 1] Position [375, 178, 400, 202] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flop." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en off latency "1" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[7 14 0 14 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" block_version "VER_STRING_GOES_HERE" sg_icon_stat "25,24,1,1,white,blue,0,07b98262,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 24 24 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 25 25 0 0 ],[0 0 24 24 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[15.33 15.33 " "18.33 15.33 18.33 18.33 18.33 15.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[12.33 12.33 15.33 15.33 1" "2.33 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[9.33 9.33 12.33 12.33 9.33 ],[1 1 1 ]);\npat" "ch([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[6.33 6.33 9.33 6.33 9.33 9.33 6.33 ],[0.931 0.946 0.973 ]);\nfprin" "tf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');disp('z^{-1}','t" "exmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Delay1" SID "139" Ports [1, 1] Position [495, 198, 520, 222] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flop." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en off latency "1" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[7 14 0 14 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" block_version "VER_STRING_GOES_HERE" sg_icon_stat "25,24,1,1,white,blue,0,07b98262,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 24 24 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 25 25 0 0 ],[0 0 24 24 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[15.33 15.33 " "18.33 15.33 18.33 18.33 18.33 15.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[12.33 12.33 15.33 15.33 1" "2.33 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[9.33 9.33 12.33 12.33 9.33 ],[1 1 1 ]);\npat" "ch([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[6.33 6.33 9.33 6.33 9.33 9.33 6.33 ],[0.931 0.946 0.973 ]);\nfprin" "tf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');disp('z^{-1}','t" "exmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Delay2" SID "140" Ports [1, 1] Position [605, 198, 630, 222] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flop." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en off latency "1" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[7 14 0 14 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" block_version "VER_STRING_GOES_HERE" sg_icon_stat "25,24,1,1,white,blue,0,07b98262,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 24 24 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 25 25 0 0 ],[0 0 24 24 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[15.33 15.33 " "18.33 15.33 18.33 18.33 18.33 15.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[12.33 12.33 15.33 15.33 1" "2.33 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[9.33 9.33 12.33 12.33 9.33 ],[1 1 1 ]);\npat" "ch([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[6.33 6.33 9.33 6.33 9.33 9.33 6.33 ],[0.931 0.946 0.973 ]);\nfprin" "tf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');disp('z^{-1}','t" "exmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Delay6" SID "141" Ports [2, 1] Position [265, 143, 300, 167] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flop." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en on latency "64" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[9 17 0 17 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,24,2,1,white,blue,0,bf433b8b,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 24 24 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 35 35 0 0 ],[0 0 24 24 0 ]);\npatch([10.325 14.66 17.66 20.66 23.66 17.66 13.325 10.325 ],[15.33 15" ".33 18.33 15.33 18.33 18.33 18.33 15.33 ],[1 1 1 ]);\npatch([13.325 17.66 14.66 10.325 13.325 ],[12.33 12.33 15.33" " 15.33 12.33 ],[0.931 0.946 0.973 ]);\npatch([10.325 14.66 17.66 13.325 10.325 ],[9.33 9.33 12.33 12.33 9.33 ],[1 " "1 1 ]);\npatch([13.325 23.66 20.66 17.66 14.66 10.325 13.325 ],[6.33 6.33 9.33 6.33 9.33 9.33 6.33 ],[0.931 0.946 " "0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');po" "rt_label('input',2,'en');\n\ncolor('black');disp('z^{-64}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register" SID "142" Ports [1, 1] Position [600, 142, 635, 178] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "35,36,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 36 36 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 35 35 0 0 ],[0 0 36 36 0 ]);\npatch([5.875 13.1 18.1 23.1 28.1 18.1 10.875 5.875 ],[23.55 23.55 28." "55 23.55 28.55 28.55 28.55 23.55 ],[1 1 1 ]);\npatch([10.875 18.1 13.1 5.875 10.875 ],[18.55 18.55 23.55 23.55 18." "55 ],[0.931 0.946 0.973 ]);\npatch([5.875 13.1 18.1 10.875 5.875 ],[13.55 13.55 18.55 18.55 13.55 ],[1 1 1 ]);\npa" "tch([10.875 28.1 23.1 18.1 13.1 5.875 10.875 ],[8.55 8.55 13.55 8.55 13.55 13.55 8.55 ],[0.931 0.946 0.973 ]);\nfp" "rintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input" "',1,'d');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','" "COMMENT: end icon text');" } Block { BlockType Outport Name "Valid" SID "143" Position [710, 203, 740, 217] IconDisplay "Port number" } Block { BlockType Outport Name "Sum" SID "144" Position [710, 153, 740, 167] Port "2" IconDisplay "Port number" } Line { SrcBlock "Delay2" SrcPort 1 DstBlock "Valid" DstPort 1 } Line { SrcBlock "Delay1" SrcPort 1 DstBlock "Delay2" DstPort 1 } Line { SrcBlock "Delay" SrcPort 1 Points [50, 0] Branch { Points [0, 20] DstBlock "Delay1" DstPort 1 } Branch { Points [0, -20] DstBlock "Accum1" DstPort 2 } } Line { SrcBlock "En" SrcPort 1 Points [10, 0] Branch { DstBlock "Delay" DstPort 1 } Branch { Points [0, -30] DstBlock "Delay6" DstPort 2 } } Line { SrcBlock "Register" SrcPort 1 DstBlock "Sum" DstPort 1 } Line { SrcBlock "Accum1" SrcPort 1 DstBlock "Register" DstPort 1 } Line { SrcBlock "D" SrcPort 1 Points [0, 0; 15, 0] Branch { Points [0, 20] DstBlock "Delay6" DstPort 1 } Branch { DstBlock "AddSub1" DstPort 1 } } Line { SrcBlock "AddSub1" SrcPort 1 DstBlock "Accum1" DstPort 1 } Line { SrcBlock "Delay6" SrcPort 1 DstBlock "AddSub1" DstPort 2 } } } Block { BlockType SubSystem Name "S-R Latch2" SID "14891" Ports [2, 1] Position [640, 533, 675, 562] NamePlacement "alternate" MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "S-R Latch2" Location [351, 366, 2001, 1172] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "S" SID "14892" Position [140, 103, 170, 117] IconDisplay "Port number" } Block { BlockType Inport Name "R" SID "14893" Position [140, 88, 170, 102] NamePlacement "alternate" Port "2" IconDisplay "Port number" } Block { BlockType Reference Name "Constant1" SID "14894" Ports [0, 1] Position [195, 71, 210, 89] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "1" gui_display_data_type "Fixed-point" arith_type "Boolean" n_bits "1" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" block_version "VER_STRING_GOES_HERE" sg_icon_stat "15,18,0,1,white,blue,0,1c72b5be,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 15 15 0 0 ],[0 0 18 18 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 15 15 0 0 ],[0 0 18 18 0 ]);\npatch([2.55 5.44 7.44 9.44 11.44 7.44 4.55 2.55 ],[11.22 11.22 13.22 " "11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([4.55 7.44 5.44 2.55 4.55 ],[9.22 9.22 11.22 11.22 9.22 ],[0.931" " 0.946 0.973 ]);\npatch([2.55 5.44 7.44 4.55 2.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);\npatch([4.55 11.44 9.44" " 7.44 5.44 2.55 4.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon" " graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'1');\nfprintf('','COM" "MENT: end icon text');" } Block { BlockType Reference Name "Convert1" SID "14895" Ports [1, 1] Position [230, 86, 255, 104] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do not." gui_display_data_type "Boolean" arith_type "Boolean" n_bits "1" bin_pt "0" float_type "Single" exp_bits "8" fraction_bits "24" quantization "Truncate" overflow "Wrap" en off latency "0" dbl_ovrd off pipeline off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "convert" sg_icon_stat "25,18,1,1,white,blue,0,edca21da,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 18 18 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 25 25 0 0 ],[0 0 18 18 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[11.22 11.22 13" ".22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[9.22 9.22 11.22 11.22 9.22 ]," "[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);\npatch([9.55 16" ".44 14.44 12.44 10.44 7.55 9.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMEN" "T: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('output',1,'cast');\n" "fprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Convert2" SID "14896" Ports [1, 1] Position [230, 101, 255, 119] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do not." gui_display_data_type "Boolean" arith_type "Boolean" n_bits "1" bin_pt "0" float_type "Single" exp_bits "8" fraction_bits "24" quantization "Truncate" overflow "Wrap" en off latency "0" dbl_ovrd off pipeline off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "convert" sg_icon_stat "25,18,1,1,white,blue,0,edca21da,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 18 18 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 25 25 0 0 ],[0 0 18 18 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[11.22 11.22 13" ".22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[9.22 9.22 11.22 11.22 9.22 ]," "[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);\npatch([9.55 16" ".44 14.44 12.44 10.44 7.55 9.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMEN" "T: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('output',1,'cast');\n" "fprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register2" SID "14897" Ports [3, 1] Position [300, 71, 345, 119] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst on en on dbl_ovrd off xl_use_area off xl_area "[1 1 0 0 0 0 0]" has_advanced_control "0" sggui_pos "20,20,348,193" block_type "register" block_version "VER_STRING_GOES_HERE" sg_icon_stat "45,48,3,1,white,blue,0,30546de1,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 48 48 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 45 45 0 0 ],[0 0 48 48 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[30.66 30.66 3" "6.66 30.66 36.66 36.66 36.66 30.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[24.66 24.66 30.66 30.66 24" ".66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[18.66 18.66 24.66 24.66 18.66 ],[1 1 1 ]);\npa" "tch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[12.66 12.66 18.66 12.66 18.66 18.66 12.66 ],[0.931 0.946 0.973 ])" ";\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('" "input',1,'d');\ncolor('black');port_label('input',2,'rst');\ncolor('black');port_label('input',3,'en');\ncolor('bl" "ack');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon te" "xt');" } Block { BlockType Outport Name "Q" SID "14898" Position [370, 88, 400, 102] IconDisplay "Port number" } Line { SrcBlock "Convert2" SrcPort 1 DstBlock "Register2" DstPort 3 } Line { SrcBlock "Convert1" SrcPort 1 DstBlock "Register2" DstPort 2 } Line { SrcBlock "S" SrcPort 1 DstBlock "Convert2" DstPort 1 } Line { SrcBlock "Register2" SrcPort 1 DstBlock "Q" DstPort 1 } Line { SrcBlock "R" SrcPort 1 DstBlock "Convert1" DstPort 1 } Line { SrcBlock "Constant1" SrcPort 1 DstBlock "Register2" DstPort 1 } } } Block { BlockType Reference Name "Scale" SID "153" Ports [1, 1] Position [1345, 543, 1380, 567] NamePlacement "alternate" LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Scale" SourceType "Xilinx Input Scaler Block" infoedit "Scales input by a power of two by adjusting the binary point position.

Hardware notes: " "In hardware this block costs nothing." scale_factor "-7" dbl_ovrd off has_advanced_control "0" sggui_pos "20,20,336,191" block_type "scale" block_version "10.1.2" sg_icon_stat "35,24,1,1,white,blue,0,6cf58983,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 24 24 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 24 24 0 ]);\npatch([10.325 14.66 17.66 20.66 23.66 17.66 13.325 10.325 ]" ",[15.33 15.33 18.33 15.33 18.33 18.33 18.33 15.33 ],[1 1 1 ]);\npatch([13.325 17.66 14.66 10.325 13.325 ],[12.3" "3 12.33 15.33 15.33 12.33 ],[0.931 0.946 0.973 ]);\npatch([10.325 14.66 17.66 13.325 10.325 ],[9.33 9.33 12.33 " "12.33 9.33 ],[1 1 1 ]);\npatch([13.325 23.66 20.66 17.66 14.66 10.325 13.325 ],[6.33 6.33 9.33 6.33 9.33 9.33 6" ".33 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text')" ";\n\n\ncolor('black');disp('\\bf{2^{-7}}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Scale1" SID "15036" Ports [1, 1] Position [1345, 438, 1380, 462] NamePlacement "alternate" LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Scale" SourceType "Xilinx Input Scaler Block" infoedit "Scales input by a power of two by adjusting the binary point position.

Hardware notes: " "In hardware this block costs nothing." scale_factor "-7" dbl_ovrd off has_advanced_control "0" sggui_pos "20,20,336,191" block_type "scale" block_version "10.1.2" sg_icon_stat "35,24,1,1,white,blue,0,6cf58983,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 24 24 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 24 24 0 ]);\npatch([10.325 14.66 17.66 20.66 23.66 17.66 13.325 10.325 ]" ",[15.33 15.33 18.33 15.33 18.33 18.33 18.33 15.33 ],[1 1 1 ]);\npatch([13.325 17.66 14.66 10.325 13.325 ],[12.3" "3 12.33 15.33 15.33 12.33 ],[0.931 0.946 0.973 ]);\npatch([10.325 14.66 17.66 13.325 10.325 ],[9.33 9.33 12.33 " "12.33 9.33 ],[1 1 1 ]);\npatch([13.325 23.66 20.66 17.66 14.66 10.325 13.325 ],[6.33 6.33 9.33 6.33 9.33 9.33 6" ".33 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text')" ";\n\n\ncolor('black');disp('\\bf{2^{-7}}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Outport Name "CFO" SID "154" Position [1495, 548, 1525, 562] IconDisplay "Port number" } Line { Name "Sum Q" Labels [0, 0] SrcBlock "Gateway Out5" SrcPort 1 DstBlock "CFO Est" DstPort 6 } Line { Name "Sum I" Labels [0, 0] SrcBlock "Gateway Out4" SrcPort 1 DstBlock "CFO Est" DstPort 5 } Line { Name "Conj Prod Q" Labels [0, 0] SrcBlock "Gateway Out3" SrcPort 1 DstBlock "CFO Est" DstPort 4 } Line { Name "Conj Prod I" Labels [0, 0] SrcBlock "Gateway Out2" SrcPort 1 DstBlock "CFO Est" DstPort 3 } Line { Name "ADC Q" Labels [0, 0] SrcBlock "Gateway Out1" SrcPort 1 DstBlock "CFO Est" DstPort 2 } Line { Name "ADC I" Labels [0, 0] SrcBlock "Gateway Out" SrcPort 1 DstBlock "CFO Est" DstPort 1 } Line { SrcBlock "rx_valid" SrcPort 1 Points [105, 0] Branch { Points [75, 0] Branch { DstBlock "Conj Mult" DstPort 1 } Branch { Points [0, 95] Branch { DstBlock "Delay2" DstPort 2 } Branch { Points [0, 30] DstBlock "Delay1" DstPort 2 } } } Branch { Points [0, 370] DstBlock "Delay" DstPort 2 } } Line { SrcBlock "rx_I" SrcPort 1 Points [115, 0] Branch { Points [75, 0] Branch { DstBlock "Conj Mult" DstPort 2 } Branch { Points [0, 55] DstBlock "Delay2" DstPort 1 } } Branch { Points [0, -170] DstBlock "Gateway Out" DstPort 1 } } Line { SrcBlock "rx_Q" SrcPort 1 Points [120, 0] Branch { Points [65, 0] Branch { DstBlock "Conj Mult" DstPort 3 } Branch { Points [0, 55] DstBlock "Delay1" DstPort 1 } } Branch { Points [0, -180] DstBlock "Gateway Out1" DstPort 1 } } Line { SrcBlock "Delay2" SrcPort 1 DstBlock "Conj Mult" DstPort 4 } Line { SrcBlock "Delay1" SrcPort 1 DstBlock "Conj Mult" DstPort 5 } Line { SrcBlock "Conj Mult" SrcPort 2 Points [35, 0] Branch { DstBlock "Running Sum" DstPort 2 } Branch { Points [0, -160] DstBlock "Gateway Out2" DstPort 1 } } Line { SrcBlock "Conj Mult" SrcPort 1 Points [25, 0; 0, 45] Branch { DstBlock "Running Sum" DstPort 1 } Branch { Points [0, 55] DstBlock "Running Sum1" DstPort 1 } } Line { SrcBlock "Conj Mult" SrcPort 3 Points [40, 0] Branch { DstBlock "Running Sum1" DstPort 2 } Branch { Points [0, -195] DstBlock "Gateway Out3" DstPort 1 } } Line { SrcBlock "Running Sum" SrcPort 1 Points [15, 0; 0, -10] DstBlock "Phase" DstPort 1 } Line { SrcBlock "Phase" SrcPort 2 Points [150, 0] Branch { Points [0, -95] DstBlock "Gateway Out6" DstPort 1 } Branch { Points [0, 155] Branch { Points [0, 100] DstBlock "Register" DstPort 1 } Branch { DstBlock "Register1" DstPort 1 } } } Line { Name "Phase(Sum)" Labels [0, 0] SrcBlock "Gateway Out6" SrcPort 1 DstBlock "CFO Est" DstPort 7 } Line { SrcBlock "Register" SrcPort 1 DstBlock "Convert2" DstPort 1 } Line { SrcBlock "Convert2" SrcPort 1 DstBlock "Scale" DstPort 1 } Line { SrcBlock "Scale" SrcPort 1 Points [20, 0] Branch { Points [0, -235; -275, 0; 0, -100] DstBlock "Gateway Out8" DstPort 1 } Branch { DstBlock "CFO" DstPort 1 } } Line { Name "LTS Sync" Labels [0, 0] SrcBlock "Gateway Out7" SrcPort 1 DstBlock "CFO Est" DstPort 8 } Line { Name "CFO Est Out" Labels [0, 0] SrcBlock "Gateway Out8" SrcPort 1 DstBlock "CFO Est" DstPort 9 } Line { Points [1230, 240] DstBlock "CFO Est" DstPort 10 } Line { SrcBlock "Delay" SrcPort 1 DstBlock "Posedge3" DstPort 1 } Line { SrcBlock "Posedge3" SrcPort 1 Points [50, 0] Branch { Points [0, -50; -370, 0; 0, 45] DstBlock "S-R Latch2" DstPort 2 } Branch { Points [140, 0] Branch { Points [0, 20] DstBlock "Register" DstPort 3 } Branch { Points [0, -90] Branch { Points [0, -270] DstBlock "Gateway Out7" DstPort 1 } Branch { DstBlock "Register1" DstPort 2 } } } } Line { SrcBlock "Running Sum" SrcPort 2 Points [50, 0] Branch { DstBlock "Phase" DstPort 2 } Branch { Points [0, -120] DstBlock "Gateway Out4" DstPort 1 } } Line { SrcBlock "Running Sum1" SrcPort 2 Points [60, 0; 0, -35] Branch { DstBlock "Phase" DstPort 3 } Branch { Points [0, -120] DstBlock "Gateway Out5" DstPort 1 } } Line { SrcBlock "LTS_Sync" SrcPort 1 DstBlock "S-R Latch2" DstPort 1 } Line { SrcBlock "S-R Latch2" SrcPort 1 DstBlock "Delay" DstPort 1 } Line { SrcBlock "From2" SrcPort 1 DstBlock "Logical" DstPort 2 } Line { SrcBlock "Reset" SrcPort 1 DstBlock "Logical" DstPort 1 } Line { SrcBlock "Logical" SrcPort 1 Points [30, 0; 0, -65] DstBlock "Register" DstPort 2 } Line { SrcBlock "Register1" SrcPort 1 DstBlock "Convert1" DstPort 1 } Line { SrcBlock "Convert1" SrcPort 1 DstBlock "Scale1" DstPort 1 } Line { SrcBlock "Scale1" SrcPort 1 DstBlock "Goto" DstPort 1 } Annotation { Name "(1/2) for normalization of phase\n(1/64) for number of summed elements" Position [1368, 584] } Annotation { Name "Delay LTS sync to capture phase sum output from end\nof LTF, maximizing multipath tolerance in the" " CFO est\n\nLatch captures 1-cycle pulse" Position [654, 649] } } } Block { BlockType Scope Name "FFT in FIFO Ctrl" SID "155" Ports [7] Position [1465, 218, 1500, 312] ZOrder -3 Floating off Location [6, 40, 1838, 1194] Open off NumInputPorts "7" ZoomMode "xonly" List { ListType AxesTitles axes1 "%" axes2 "%" axes3 "%" axes4 "%" axes5 "%" axes6 "%" axes7 "%" } List { ListType ScopeGraphics FigureColor "[0.5 0.5 0.5]" AxesColor "[0 0 0]" AxesTickColor "[1 1 1]" LineColors "[1 1 0;1 0 1;0 1 1;1 0 0;0 1 0;0 0 1]" LineStyles "-|-|-|-|-|-" LineWidths "[0.5 0.5 0.5 0.5 0.5 0.5]" MarkerStyles "none|none|none|none|none|none" } TimeRange "30000" YMin "0~0~0~-0.1~0~-0.1~-0.1" YMax "300~300~1~1.1~4000~1.1~1.1" DataFormat "StructureWithTime" LimitDataPoints off SampleTime "0" } Block { BlockType SubSystem Name "FIFO" SID "156" Ports [5, 5] Position [1135, 334, 1245, 596] NamePlacement "alternate" MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "FIFO" Location [88, 301, 2330, 1301] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "data tvalid" SID "157" Position [525, 333, 555, 347] IconDisplay "Port number" } Block { BlockType Inport Name "I" SID "158" Position [325, 353, 355, 367] NamePlacement "alternate" Port "2" IconDisplay "Port number" } Block { BlockType Inport Name "Q" SID "159" Position [325, 378, 355, 392] Port "3" IconDisplay "Port number" } Block { BlockType Inport Name "data tlast" SID "160" Position [525, 403, 555, 417] Port "4" IconDisplay "Port number" } Block { BlockType Inport Name "FFT tready" SID "161" Position [525, 298, 555, 312] Port "5" IconDisplay "Port number" } Block { BlockType Reference Name "AXI FIFO" SID "162" Ports [4, 5] Position [625, 283, 825, 427] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/AXI FIFO" SourceType "Xilinx AXI FIFO Block Block" input_depth_axis "128" actual_fifo_depth_label "130" enable_tdata on enable_tdest off enable_tstrb off enable_tready on enable_tid off enable_tuser off enable_tkeep off enable_tlast on has_aresetn off enable_data_counts_axis on fifo_implementation_type_axis "Common Clock Block RAM" trim_axipin_name on programmable_full_type_axis "Full" full_threshold_assert_value_axis "0" programmable_empty_type_axis "Empty" empty_threshold_assert_value_axis "1022" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "axi_fifo" sg_icon_stat "200,144,4,5,white,blue,0,c7b89414,right,,[2 3 3 3 ],[2 2 2 3 1 ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 0 4 4 ],[134 110 110 134 ],[5.4666" "67e-001 5.800000e-001 6.400000e-001 ]);\npatch([0 0 4 4 ],[99 5 5 99 ],[3.233333e-001 3.400000e-001 3.700000e-0" "01 ]);\npatch([196 196 200 200 ],[143 61 61 143 ],[5.466667e-001 5.800000e-001 6.400000e-001 ]);\npatch([196 19" "6 200 200 ],[53 31 31 53 ],[3.233333e-001 3.400000e-001 3.700000e-001 ]);\npatch([196 196 200 200 ],[23 1 1 23 " "],[7.700000e-001 8.200000e-001 9.100000e-001 ]);\npatch([4 195 195 4 4 ],[0 0 144 144 0 ],[7.700000e-001 8.2000" "00e-001 9.100000e-001 ]);\nplot([4 195 195 4 4 ],[0 0 144 144 0 ]);\n\n\npatch([55.5 84.4 104.4 124.4 144.4 104" ".4 75.5 55.5 ],[94.2 94.2 114.2 94.2 114.2 114.2 114.2 94.2 ],[1 1 1 ]);\npatch([75.5 104.4 84.4 55.5 75.5 ],[7" "4.2 74.2 94.2 94.2 74.2 ],[0.931 0.946 0.973 ]);\npatch([55.5 84.4 104.4 75.5 55.5 ],[54.2 54.2 74.2 74.2 54.2 " "],[1 1 1 ]);\npatch([75.5 144.4 124.4 104.4 84.4 55.5 75.5 ],[34.2 34.2 54.2 34.2 54.2 54.2 34.2 ],[0.931 0.946" " 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');" "port_label('input',1,' tready ');\ncolor('black');port_label('input',2,' tvalid ');\ncolor('black');port_la" "bel('input',3,' tdata ');\ncolor('black');port_label('input',4,' tlast ');\ncolor('black');port_label('outp" "ut',1,' tvalid ');\ncolor('black');port_label('output',2,' tdata ');\ncolor('black');port_label('output',3," "' tlast ');\ncolor('black');port_label('output',4,' tready ');\ncolor('black');port_label('output',5,' dat" "a_count ');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Scope Name "FIFO" SID "163" Ports [9] Position [1535, 181, 1570, 319] ZOrder -3 Floating off Location [246, 238, 2456, 1582] Open off NumInputPorts "9" ZoomMode "xonly" List { ListType AxesTitles axes1 "%" axes2 "%" axes3 "%" axes4 "%" axes5 "%" axes6 "%" axes7 "%" axes8 "%" axes9 "%" } List { ListType ScopeGraphics FigureColor "[0.5 0.5 0.5]" AxesColor "[0 0 0]" AxesTickColor "[1 1 1]" LineColors "[1 1 0;1 0 1;0 1 1;1 0 0;0 1 0;0 0 1]" LineStyles "-|-|-|-|-|-" LineWidths "[0.5 0.5 0.5 0.5 0.5 0.5]" MarkerStyles "none|none|none|none|none|none" } TimeRange "14580 " YMin "0.95~-1~-1~-1~0.95~-1~-1~-1~-1" YMax "1.05~1~1~1~1.05~1~1~1~1" SaveName "ScopeData20" DataFormat "StructureWithTime" LimitDataPoints off SampleTime "0" } Block { BlockType Reference Name "Gateway Out1" SID "164" Ports [1, 1] Position [1375, 199, 1410, 211] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of t" "ype Simulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become t" "op level output ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0" ".88 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ]" ",[7.11 7.11 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7." "11 7.11 6.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1" " 1 1 ]);\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0." "964 0.964 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black" "');port_label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nf" "printf('','COMMENT: end icon text');" Port { PortNumber 1 Name "FIFO out valid" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out2" SID "165" Ports [1, 1] Position [1375, 214, 1410, 226] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of t" "ype Simulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become t" "op level output ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0" ".88 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ]" ",[7.11 7.11 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7." "11 7.11 6.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1" " 1 1 ]);\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0." "964 0.964 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black" "');port_label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nf" "printf('','COMMENT: end icon text');" Port { PortNumber 1 Name "Q out" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out3" SID "166" Ports [1, 1] Position [1375, 229, 1410, 241] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of t" "ype Simulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become t" "op level output ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0" ".88 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ]" ",[7.11 7.11 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7." "11 7.11 6.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1" " 1 1 ]);\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0." "964 0.964 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black" "');port_label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nf" "printf('','COMMENT: end icon text');" Port { PortNumber 1 Name "tlast out" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out4" SID "167" Ports [1, 1] Position [1375, 244, 1410, 256] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of t" "ype Simulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become t" "op level output ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0" ".88 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ]" ",[7.11 7.11 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7." "11 7.11 6.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1" " 1 1 ]);\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0." "964 0.964 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black" "');port_label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nf" "printf('','COMMENT: end icon text');" Port { PortNumber 1 Name "FIFO ready" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out5" SID "168" Ports [1, 1] Position [1375, 259, 1410, 271] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of t" "ype Simulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become t" "op level output ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0" ".88 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ]" ",[7.11 7.11 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7." "11 7.11 6.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1" " 1 1 ]);\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0." "964 0.964 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black" "');port_label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nf" "printf('','COMMENT: end icon text');" Port { PortNumber 1 Name "valid in" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out6" SID "169" Ports [1, 1] Position [1375, 274, 1410, 286] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of t" "ype Simulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become t" "op level output ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0" ".88 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ]" ",[7.11 7.11 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7." "11 7.11 6.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1" " 1 1 ]);\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0." "964 0.964 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black" "');port_label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nf" "printf('','COMMENT: end icon text');" Port { PortNumber 1 Name "tlast in" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out8" SID "170" Ports [1, 1] Position [1375, 184, 1410, 196] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of t" "ype Simulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become t" "op level output ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0" ".88 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ]" ",[7.11 7.11 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7." "11 7.11 6.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1" " 1 1 ]);\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0." "964 0.964 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black" "');port_label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nf" "printf('','COMMENT: end icon text');" Port { PortNumber 1 Name "FFT ready" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out9" SID "171" Ports [1, 1] Position [1375, 304, 1410, 316] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of t" "ype Simulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become t" "op level output ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0" ".88 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ]" ",[7.11 7.11 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7." "11 7.11 6.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1" " 1 1 ]);\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0." "964 0.964 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black" "');port_label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nf" "printf('','COMMENT: end icon text');" Port { PortNumber 1 Name "FIFO Occ" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType SubSystem Name "I/Q Concat" SID "172" Ports [2, 1] Position [420, 347, 460, 398] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "I/Q Concat" Location [522, 447, 879, 615] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "I" SID "173" Position [105, 123, 135, 137] IconDisplay "Port number" } Block { BlockType Inport Name "Q" SID "174" Position [105, 158, 135, 172] Port "2" IconDisplay "Port number" } Block { BlockType Reference Name "Concat" SID "175" Ports [2, 1] Position [315, 110, 350, 185] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Concat" SourceType "Xilinx Bus Concatenator Block" infoedit "Concatenates two or more inputs. Output will be cast to an unsigned value with the binary point at z" "ero." num_inputs "2" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "concat" sg_icon_stat "35,75,2,1,white,blue,0,16398980,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 75 75 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 35 35 0 0 ],[0 0 75 75 0 ]);\npatch([5.875 13.1 18.1 23.1 28.1 18.1 10.875 5.875 ],[42.55 42.55 47." "55 42.55 47.55 47.55 47.55 42.55 ],[1 1 1 ]);\npatch([10.875 18.1 13.1 5.875 10.875 ],[37.55 37.55 42.55 42.55 37." "55 ],[0.931 0.946 0.973 ]);\npatch([5.875 13.1 18.1 10.875 5.875 ],[32.55 32.55 37.55 37.55 32.55 ],[1 1 1 ]);\npa" "tch([10.875 28.1 23.1 18.1 13.1 5.875 10.875 ],[27.55 27.55 32.55 27.55 32.55 32.55 27.55 ],[0.931 0.946 0.973 ]);" "\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('i" "nput',1,'hi');\ncolor('black');port_label('input',2,'lo');\n\ncolor('black');disp('\\fontsize{20}\\}','texmode','o" "n');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Reinterpret" SID "176" Ports [1, 1] Position [205, 119, 245, 141] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Reinterpret" SourceType "Xilinx Type Reinterpreter Block" infoedit "Changes signal type without altering the binary representation. You can change the signal between s" "igned and unsigned, and relocate the binary point.

Hardware notes: In hardware this block costs nothing.
Example: Suppose the input is 6 bits wide, signed, with 2 fractional bits, and the output is forced to unsig" "ned with 0 fractional bits. Then an input of -2.0 (1110.00 in binary 2's complement) becomes an output of 56 (111" "000 in binary)." force_arith_type on arith_type "Unsigned" force_bin_pt on bin_pt "0" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "reinterpret" sg_icon_stat "40,22,1,1,white,blue,0,6b04d0b0,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 22 22 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 40 40 0 0 ],[0 0 22 22 0 ]);\npatch([13.325 17.66 20.66 23.66 26.66 20.66 16.325 13.325 ],[14.33 14" ".33 17.33 14.33 17.33 17.33 17.33 14.33 ],[1 1 1 ]);\npatch([16.325 20.66 17.66 13.325 16.325 ],[11.33 11.33 14.33" " 14.33 11.33 ],[0.931 0.946 0.973 ]);\npatch([13.325 17.66 20.66 16.325 13.325 ],[8.33 8.33 11.33 11.33 8.33 ],[1 " "1 1 ]);\npatch([16.325 26.66 23.66 20.66 17.66 13.325 16.325 ],[5.33 5.33 8.33 5.33 8.33 8.33 5.33 ],[0.931 0.946 " "0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');" "disp('reinterpret');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Reinterpret1" SID "177" Ports [1, 1] Position [205, 154, 245, 176] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Reinterpret" SourceType "Xilinx Type Reinterpreter Block" infoedit "Changes signal type without altering the binary representation. You can change the signal between s" "igned and unsigned, and relocate the binary point.

Hardware notes: In hardware this block costs nothing.
Example: Suppose the input is 6 bits wide, signed, with 2 fractional bits, and the output is forced to unsig" "ned with 0 fractional bits. Then an input of -2.0 (1110.00 in binary 2's complement) becomes an output of 56 (111" "000 in binary)." force_arith_type on arith_type "Unsigned" force_bin_pt on bin_pt "0" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "reinterpret" sg_icon_stat "40,22,1,1,white,blue,0,6b04d0b0,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 22 22 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 40 40 0 0 ],[0 0 22 22 0 ]);\npatch([13.325 17.66 20.66 23.66 26.66 20.66 16.325 13.325 ],[14.33 14" ".33 17.33 14.33 17.33 17.33 17.33 14.33 ],[1 1 1 ]);\npatch([16.325 20.66 17.66 13.325 16.325 ],[11.33 11.33 14.33" " 14.33 11.33 ],[0.931 0.946 0.973 ]);\npatch([13.325 17.66 20.66 16.325 13.325 ],[8.33 8.33 11.33 11.33 8.33 ],[1 " "1 1 ]);\npatch([16.325 26.66 23.66 20.66 17.66 13.325 16.325 ],[5.33 5.33 8.33 5.33 8.33 8.33 5.33 ],[0.931 0.946 " "0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');" "disp('reinterpret');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Outport Name "IQ" SID "178" Position [420, 143, 450, 157] IconDisplay "Port number" } Line { SrcBlock "Reinterpret" SrcPort 1 DstBlock "Concat" DstPort 1 } Line { SrcBlock "Reinterpret1" SrcPort 1 DstBlock "Concat" DstPort 2 } Line { SrcBlock "I" SrcPort 1 DstBlock "Reinterpret" DstPort 1 } Line { SrcBlock "Concat" SrcPort 1 DstBlock "IQ" DstPort 1 } Line { SrcBlock "Q" SrcPort 1 DstBlock "Reinterpret1" DstPort 1 } } } Block { BlockType SubSystem Name "I/Q Slice" SID "179" Ports [1, 2] Position [955, 305, 1005, 340] NamePlacement "alternate" MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "I/Q Slice" Location [1155, 565, 1558, 696] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "IQ" SID "180" Position [190, 123, 220, 137] IconDisplay "Port number" } Block { BlockType Reference Name "Reinterpret2" SID "181" Ports [1, 1] Position [350, 119, 390, 141] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Reinterpret" SourceType "Xilinx Type Reinterpreter Block" infoedit "Changes signal type without altering the binary representation. You can change the signal between s" "igned and unsigned, and relocate the binary point.

Hardware notes: In hardware this block costs nothing.
Example: Suppose the input is 6 bits wide, signed, with 2 fractional bits, and the output is forced to unsig" "ned with 0 fractional bits. Then an input of -2.0 (1110.00 in binary 2's complement) becomes an output of 56 (111" "000 in binary)." force_arith_type on arith_type "Signed (2's comp)" force_bin_pt on bin_pt "15" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "reinterpret" sg_icon_stat "40,22,1,1,white,blue,0,6b04d0b0,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 22 22 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 40 40 0 0 ],[0 0 22 22 0 ]);\npatch([13.325 17.66 20.66 23.66 26.66 20.66 16.325 13.325 ],[14.33 14" ".33 17.33 14.33 17.33 17.33 17.33 14.33 ],[1 1 1 ]);\npatch([16.325 20.66 17.66 13.325 16.325 ],[11.33 11.33 14.33" " 14.33 11.33 ],[0.931 0.946 0.973 ]);\npatch([13.325 17.66 20.66 16.325 13.325 ],[8.33 8.33 11.33 11.33 8.33 ],[1 " "1 1 ]);\npatch([16.325 26.66 23.66 20.66 17.66 13.325 16.325 ],[5.33 5.33 8.33 5.33 8.33 8.33 5.33 ],[0.931 0.946 " "0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');" "disp('reinterpret');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Reinterpret3" SID "182" Ports [1, 1] Position [350, 144, 390, 166] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Reinterpret" SourceType "Xilinx Type Reinterpreter Block" infoedit "Changes signal type without altering the binary representation. You can change the signal between s" "igned and unsigned, and relocate the binary point.

Hardware notes: In hardware this block costs nothing.
Example: Suppose the input is 6 bits wide, signed, with 2 fractional bits, and the output is forced to unsig" "ned with 0 fractional bits. Then an input of -2.0 (1110.00 in binary 2's complement) becomes an output of 56 (111" "000 in binary)." force_arith_type on arith_type "Signed (2's comp)" force_bin_pt on bin_pt "15" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "reinterpret" sg_icon_stat "40,22,1,1,white,blue,0,6b04d0b0,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 22 22 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 40 40 0 0 ],[0 0 22 22 0 ]);\npatch([13.325 17.66 20.66 23.66 26.66 20.66 16.325 13.325 ],[14.33 14" ".33 17.33 14.33 17.33 17.33 17.33 14.33 ],[1 1 1 ]);\npatch([16.325 20.66 17.66 13.325 16.325 ],[11.33 11.33 14.33" " 14.33 11.33 ],[0.931 0.946 0.973 ]);\npatch([13.325 17.66 20.66 16.325 13.325 ],[8.33 8.33 11.33 11.33 8.33 ],[1 " "1 1 ]);\npatch([16.325 26.66 23.66 20.66 17.66 13.325 16.325 ],[5.33 5.33 8.33 5.33 8.33 8.33 5.33 ],[0.931 0.946 " "0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');" "disp('reinterpret');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Slice" SID "183" Ports [1, 1] Position [265, 119, 300, 141] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The output type" " is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.

Hardw" "are notes: In hardware this block costs nothing." nbits "16" boolean_output off mode "Upper Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "0" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "slice" sg_icon_stat "35,22,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 22 22 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 35 35 0 0 ],[0 0 22 22 0 ]);\npatch([10.325 14.66 17.66 20.66 23.66 17.66 13.325 10.325 ],[14.33 14" ".33 17.33 14.33 17.33 17.33 17.33 14.33 ],[1 1 1 ]);\npatch([13.325 17.66 14.66 10.325 13.325 ],[11.33 11.33 14.33" " 14.33 11.33 ],[0.931 0.946 0.973 ]);\npatch([10.325 14.66 17.66 13.325 10.325 ],[8.33 8.33 11.33 11.33 8.33 ],[1 " "1 1 ]);\npatch([13.325 23.66 20.66 17.66 14.66 10.325 13.325 ],[5.33 5.33 8.33 5.33 8.33 8.33 5.33 ],[0.931 0.946 " "0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');po" "rt_label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Slice1" SID "184" Ports [1, 1] Position [265, 144, 300, 166] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The output type" " is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.

Hardw" "are notes: In hardware this block costs nothing." nbits "16" boolean_output off mode "Lower Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "0" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "slice" sg_icon_stat "35,22,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 22 22 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 35 35 0 0 ],[0 0 22 22 0 ]);\npatch([10.325 14.66 17.66 20.66 23.66 17.66 13.325 10.325 ],[14.33 14" ".33 17.33 14.33 17.33 17.33 17.33 14.33 ],[1 1 1 ]);\npatch([13.325 17.66 14.66 10.325 13.325 ],[11.33 11.33 14.33" " 14.33 11.33 ],[0.931 0.946 0.973 ]);\npatch([10.325 14.66 17.66 13.325 10.325 ],[8.33 8.33 11.33 11.33 8.33 ],[1 " "1 1 ]);\npatch([13.325 23.66 20.66 17.66 14.66 10.325 13.325 ],[5.33 5.33 8.33 5.33 8.33 8.33 5.33 ],[0.931 0.946 " "0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');po" "rt_label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Outport Name "I" SID "185" Position [450, 123, 480, 137] NamePlacement "alternate" IconDisplay "Port number" } Block { BlockType Outport Name "Q" SID "186" Position [450, 148, 480, 162] Port "2" IconDisplay "Port number" } Line { SrcBlock "Reinterpret3" SrcPort 1 DstBlock "Q" DstPort 1 } Line { SrcBlock "Reinterpret2" SrcPort 1 DstBlock "I" DstPort 1 } Line { SrcBlock "IQ" SrcPort 1 Points [15, 0] Branch { DstBlock "Slice" DstPort 1 } Branch { Points [0, 25] DstBlock "Slice1" DstPort 1 } } Line { SrcBlock "Slice1" SrcPort 1 DstBlock "Reinterpret3" DstPort 1 } Line { SrcBlock "Slice" SrcPort 1 DstBlock "Reinterpret2" DstPort 1 } } } Block { BlockType Reference Name "Logical2" SID "187" Ports [2, 1] Position [900, 334, 930, 361] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "AND" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" sg_icon_stat "30,27,2,1,white,blue,0,83a4b621,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 27 27 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 27 27 0 ]);\npatch([8.325 12.66 15.66 18.66 21.66 15.66 11.325 8.325 ],[" "16.33 16.33 19.33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([11.325 15.66 12.66 8.325 11.325 ],[13.33 1" "3.33 16.33 16.33 13.33 ],[0.931 0.946 0.973 ]);\npatch([8.325 12.66 15.66 11.325 8.325 ],[10.33 10.33 13.33 13." "33 10.33 ],[1 1 1 ]);\npatch([11.325 21.66 18.66 15.66 12.66 8.325 11.325 ],[7.33 7.33 10.33 7.33 10.33 10.33 7" ".33 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text')" ";\n\n\n\ncolor('black');disp('and');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Outport Name "FFT tvalid" SID "188" Position [900, 288, 930, 302] NamePlacement "alternate" IconDisplay "Port number" } Block { BlockType Outport Name "FFT tdata_re" SID "189" Position [1075, 308, 1105, 322] NamePlacement "alternate" Port "2" IconDisplay "Port number" } Block { BlockType Outport Name "FFT tdata_im" SID "190" Position [1075, 323, 1105, 337] Port "3" IconDisplay "Port number" } Block { BlockType Outport Name "FFT tlast" SID "191" Position [1325, 343, 1355, 357] Port "4" IconDisplay "Port number" } Block { BlockType Outport Name "FIFO tready" SID "192" Position [900, 378, 930, 392] Port "5" IconDisplay "Port number" } Line { SrcBlock "AXI FIFO" SrcPort 2 DstBlock "I/Q Slice" DstPort 1 } Line { SrcBlock "AXI FIFO" SrcPort 1 Points [30, 0] Branch { DstBlock "FFT tvalid" DstPort 1 } Branch { Points [0, -90] DstBlock "Gateway Out1" DstPort 1 } Branch { Points [0, 45] DstBlock "Logical2" DstPort 1 } } Line { SrcBlock "AXI FIFO" SrcPort 3 DstBlock "Logical2" DstPort 2 } Line { Name "FFT ready" Labels [0, 0] SrcBlock "Gateway Out8" SrcPort 1 DstBlock "FIFO" DstPort 1 } Line { SrcBlock "I/Q Slice" SrcPort 1 DstBlock "FFT tdata_re" DstPort 1 } Line { SrcBlock "I/Q Slice" SrcPort 2 Points [10, 0] Branch { DstBlock "FFT tdata_im" DstPort 1 } Branch { Points [0, -110] DstBlock "Gateway Out2" DstPort 1 } } Line { SrcBlock "FFT tready" SrcPort 1 Points [30, 0] Branch { Points [0, -115] DstBlock "Gateway Out8" DstPort 1 } Branch { DstBlock "AXI FIFO" DstPort 1 } } Line { SrcBlock "data tvalid" SrcPort 1 Points [40, 0] Branch { Points [0, 165; 550, 0; 0, -240] DstBlock "Gateway Out5" DstPort 1 } Branch { DstBlock "AXI FIFO" DstPort 2 } } Line { SrcBlock "data tlast" SrcPort 1 Points [30, 0] Branch { Points [0, 80; 575, 0; 0, -210] DstBlock "Gateway Out6" DstPort 1 } Branch { DstBlock "AXI FIFO" DstPort 4 } } Line { SrcBlock "AXI FIFO" SrcPort 4 Points [25, 0] Branch { DstBlock "FIFO tready" DstPort 1 } Branch { Points [0, 55; 285, 0; 0, -190] DstBlock "Gateway Out4" DstPort 1 } } Line { Name "FIFO out valid" Labels [0, 0] SrcBlock "Gateway Out1" SrcPort 1 DstBlock "FIFO" DstPort 2 } Line { Name "Q out" Labels [0, 0] SrcBlock "Gateway Out2" SrcPort 1 DstBlock "FIFO" DstPort 3 } Line { Name "tlast out" Labels [0, 0] SrcBlock "Gateway Out3" SrcPort 1 DstBlock "FIFO" DstPort 4 } Line { Name "FIFO ready" Labels [0, 0] SrcBlock "Gateway Out4" SrcPort 1 DstBlock "FIFO" DstPort 5 } Line { Name "valid in" Labels [0, 0] SrcBlock "Gateway Out5" SrcPort 1 DstBlock "FIFO" DstPort 6 } Line { Name "tlast in" Labels [0, 0] SrcBlock "Gateway Out6" SrcPort 1 DstBlock "FIFO" DstPort 7 } Line { SrcBlock "Logical2" SrcPort 1 Points [360, 0] Branch { DstBlock "FFT tlast" DstPort 1 } Branch { Points [0, -115] DstBlock "Gateway Out3" DstPort 1 } } Line { SrcBlock "I" SrcPort 1 DstBlock "I/Q Concat" DstPort 1 } Line { SrcBlock "Q" SrcPort 1 DstBlock "I/Q Concat" DstPort 2 } Line { SrcBlock "I/Q Concat" SrcPort 1 DstBlock "AXI FIFO" DstPort 3 } Line { Name "Reset" Labels [0, 0] Points [1415, 295] DstBlock "FIFO" DstPort 8 } Line { Name "FIFO Occ" Labels [0, 0] SrcBlock "Gateway Out9" SrcPort 1 DstBlock "FIFO" DstPort 9 } Line { SrcBlock "AXI FIFO" SrcPort 5 Points [530, 0] DstBlock "Gateway Out9" DstPort 1 } Annotation { Name "AND not strictly necessary, since FFT\nonly honors tlast when tvalid is asserted.\nExplicit AND he" "re makes scopes\nmuch easier to understand." Position [959, 576] } Annotation { Name "This FIFO aids in synchronizing sample generation\nand feeding the FFT. It would be possible to de" "sign\nthe sample buffer control logic not to require\nthis FIFO, but then the logic would need tweaking\nif the" " FFT timing or sample processing timing\never change. This FIFO isolates those blocks,\nat the cost of a little" " memory and 1 clock cyle latency\n(assuming the FFT consumes samples faster than\nthey're received)" Position [723, 91] } } } Block { BlockType Reference Name "Gateway Out1" SID "193" Ports [1, 1] Position [1315, 244, 1350, 256] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type Simu" "link integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top level out" "put ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0.88 0.88" " ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[7.11 7.11 " "8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7.11 7.11 6.11 ],[" "0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]);\npatch([15." "775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.964 ]);\nfprintf('" "','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,' ')" ";\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf('','COMMENT: end icon tex" "t');" Port { PortNumber 1 Name "FIFO Out: valid" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out10" SID "194" Ports [1, 1] Position [725, 229, 760, 241] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type Simu" "link integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top level out" "put ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0.88 0.88" " ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[7.11 7.11 " "8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7.11 7.11 6.11 ],[" "0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]);\npatch([15." "775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.964 ]);\nfprintf('" "','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,' ')" ";\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf('','COMMENT: end icon tex" "t');" Port { PortNumber 1 Name "Pkt Det" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out17" SID "195" Ports [1, 1] Position [725, 184, 760, 196] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type Simu" "link integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top level out" "put ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0.88 0.88" " ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[7.11 7.11 " "8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7.11 7.11 6.11 ],[" "0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]);\npatch([15." "775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.964 ]);\nfprintf('" "','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,' ')" ";\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf('','COMMENT: end icon tex" "t');" Port { PortNumber 1 Name "ADC I" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out2" SID "196" Ports [1, 1] Position [1315, 259, 1350, 271] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type Simu" "link integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top level out" "put ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0.88 0.88" " ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[7.11 7.11 " "8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7.11 7.11 6.11 ],[" "0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]);\npatch([15." "775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.964 ]);\nfprintf('" "','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,' ')" ";\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf('','COMMENT: end icon tex" "t');" Port { PortNumber 1 Name "FIFO Out: tlast" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out3" SID "197" Ports [1, 1] Position [1315, 214, 1350, 226] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type Simu" "link integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top level out" "put ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0.88 0.88" " ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[7.11 7.11 " "8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7.11 7.11 6.11 ],[" "0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]);\npatch([15." "775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.964 ]);\nfprintf('" "','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,' ')" ";\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf('','COMMENT: end icon tex" "t');" Port { PortNumber 1 Name "FIFO IN: tlast" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out4" SID "198" Ports [1, 1] Position [1315, 229, 1350, 241] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type Simu" "link integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top level out" "put ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0.88 0.88" " ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[7.11 7.11 " "8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7.11 7.11 6.11 ],[" "0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]);\npatch([15." "775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.964 ]);\nfprintf('" "','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,' ')" ";\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf('','COMMENT: end icon tex" "t');" Port { PortNumber 1 Name "FIFO IN: valid" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out5" SID "199" Ports [1, 1] Position [725, 214, 760, 226] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type Simu" "link integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top level out" "put ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0.88 0.88" " ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[7.11 7.11 " "8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7.11 7.11 6.11 ],[" "0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]);\npatch([15." "775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.964 ]);\nfprintf('" "','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,' ')" ";\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf('','COMMENT: end icon tex" "t');" Port { PortNumber 1 Name "ADC Valid" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out6" SID "200" Ports [1, 1] Position [1320, 304, 1355, 316] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type Simu" "link integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top level out" "put ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0.88 0.88" " ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[7.11 7.11 " "8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7.11 7.11 6.11 ],[" "0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]);\npatch([15." "775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.964 ]);\nfprintf('" "','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,' ')" ";\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf('','COMMENT: end icon tex" "t');" Port { PortNumber 1 Name "Reset" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out7" SID "201" Ports [1, 1] Position [725, 199, 760, 211] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type Simu" "link integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top level out" "put ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0.88 0.88" " ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[7.11 7.11 " "8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7.11 7.11 6.11 ],[" "0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]);\npatch([15." "775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.964 ]);\nfprintf('" "','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,' ')" ";\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf('','COMMENT: end icon tex" "t');" Port { PortNumber 1 Name "ADC Q" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out9" SID "202" Ports [1, 1] Position [1315, 274, 1350, 286] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type Simu" "link integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top level out" "put ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0.88 0.88" " ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[7.11 7.11 " "8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7.11 7.11 6.11 ],[" "0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]);\npatch([15." "775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.964 ]);\nfprintf('" "','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,' ')" ";\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf('','COMMENT: end icon tex" "t');" Port { PortNumber 1 Name "FFT in: tready" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType SubSystem Name "Samp Buffer" SID "203" Ports [7, 5] Position [695, 349, 780, 491] NamePlacement "alternate" MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "Samp Buffer" Location [589, 321, 2367, 1501] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "108" Block { BlockType Inport Name "Pkt Det" SID "204" Position [15, 238, 45, 252] IconDisplay "Port number" } Block { BlockType Inport Name "Pkt Done" SID "205" Position [190, 268, 220, 282] Port "2" IconDisplay "Port number" } Block { BlockType Inport Name "rx I" SID "206" Position [450, 333, 480, 347] NamePlacement "alternate" Port "3" IconDisplay "Port number" } Block { BlockType Inport Name "rx Q" SID "207" Position [450, 348, 480, 362] Port "4" IconDisplay "Port number" } Block { BlockType Inport Name "IQ valid" SID "208" Position [15, 363, 45, 377] Port "5" IconDisplay "Port number" } Block { BlockType Inport Name "LTS Sync 2" SID "209" Position [190, 628, 220, 642] NamePlacement "alternate" Port "6" IconDisplay "Port number" } Block { BlockType Inport Name "FIFO tready" SID "210" Position [300, 488, 330, 502] NamePlacement "alternate" Port "7" IconDisplay "Port number" } Block { BlockType Reference Name "Circular Sample\nBuffer" SID "211" Ports [6, 2] Position [715, 317, 805, 443] NamePlacement "alternate" LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Dual Port RAM" SourceType "Xilinx Dual Port Random Access Memory Block" depth "preFFT_sampBuff_numSamps" initVector "1 * repmat([0:63], 1, 4)" distributed_mem "Block RAM" init_a "0" init_b "0" rst_a off rst_b off en_a off en_b off latency "1" write_mode_A "Read After Write" write_mode_B "Read After Write" dbl_ovrd off optimize "Area" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "dpram" sg_icon_stat "90,126,6,2,white,blue,0,28af736d,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 90 90 0 0 ],[0 0 126 126 0 ],[0.77" " 0.82 0.91 ]);\nplot([0 90 90 0 0 ],[0 0 126 126 0 ]);\npatch([18.3 35.64 47.64 59.64 71.64 47.64 30.3 18.3 ],[" "76.32 76.32 88.32 76.32 88.32 88.32 88.32 76.32 ],[1 1 1 ]);\npatch([30.3 47.64 35.64 18.3 30.3 ],[64.32 64.32 " "76.32 76.32 64.32 ],[0.931 0.946 0.973 ]);\npatch([18.3 35.64 47.64 30.3 18.3 ],[52.32 52.32 64.32 64.32 52.32 " "],[1 1 1 ]);\npatch([30.3 71.64 59.64 47.64 35.64 18.3 30.3 ],[40.32 40.32 52.32 40.32 52.32 52.32 40.32 ],[0.9" "31 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('" "black');port_label('input',1,'addra');\ncolor('black');port_label('input',2,'dina');\ncolor('black');port_label" "('input',3,'wea');\ncolor('black');port_label('input',4,'addrb');\ncolor('black');port_label('input',5,'dinb');" "\ncolor('black');port_label('input',6,'web');\ncolor('black');port_label('output',1,'A');\ncolor('black');port_" "label('output',2,'B');\nfprintf('','COMMENT: end icon text');" } Block { BlockType SubSystem Name "Concat" SID "212" Ports [2, 1] Position [535, 330, 585, 365] NamePlacement "alternate" MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "Concat" Location [522, 447, 879, 615] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "I" SID "213" Position [105, 123, 135, 137] IconDisplay "Port number" } Block { BlockType Inport Name "Q" SID "214" Position [105, 158, 135, 172] Port "2" IconDisplay "Port number" } Block { BlockType Reference Name "Concat" SID "215" Ports [2, 1] Position [315, 110, 350, 185] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Concat" SourceType "Xilinx Bus Concatenator Block" infoedit "Concatenates two or more inputs. Output will be cast to an unsigned value with the binary point at z" "ero." num_inputs "2" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "concat" sg_icon_stat "35,75,2,1,white,blue,0,16398980,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 75 75 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 35 35 0 0 ],[0 0 75 75 0 ]);\npatch([5.875 13.1 18.1 23.1 28.1 18.1 10.875 5.875 ],[42.55 42.55 47." "55 42.55 47.55 47.55 47.55 42.55 ],[1 1 1 ]);\npatch([10.875 18.1 13.1 5.875 10.875 ],[37.55 37.55 42.55 42.55 37." "55 ],[0.931 0.946 0.973 ]);\npatch([5.875 13.1 18.1 10.875 5.875 ],[32.55 32.55 37.55 37.55 32.55 ],[1 1 1 ]);\npa" "tch([10.875 28.1 23.1 18.1 13.1 5.875 10.875 ],[27.55 27.55 32.55 27.55 32.55 32.55 27.55 ],[0.931 0.946 0.973 ]);" "\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('i" "nput',1,'hi');\ncolor('black');port_label('input',2,'lo');\n\ncolor('black');disp('\\fontsize{20}\\}','texmode','o" "n');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Reinterpret" SID "216" Ports [1, 1] Position [205, 119, 245, 141] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Reinterpret" SourceType "Xilinx Type Reinterpreter Block" infoedit "Changes signal type without altering the binary representation. You can change the signal between s" "igned and unsigned, and relocate the binary point.

Hardware notes: In hardware this block costs nothing.
Example: Suppose the input is 6 bits wide, signed, with 2 fractional bits, and the output is forced to unsig" "ned with 0 fractional bits. Then an input of -2.0 (1110.00 in binary 2's complement) becomes an output of 56 (111" "000 in binary)." force_arith_type on arith_type "Unsigned" force_bin_pt on bin_pt "0" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "reinterpret" sg_icon_stat "40,22,1,1,white,blue,0,6b04d0b0,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 22 22 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 40 40 0 0 ],[0 0 22 22 0 ]);\npatch([13.325 17.66 20.66 23.66 26.66 20.66 16.325 13.325 ],[14.33 14" ".33 17.33 14.33 17.33 17.33 17.33 14.33 ],[1 1 1 ]);\npatch([16.325 20.66 17.66 13.325 16.325 ],[11.33 11.33 14.33" " 14.33 11.33 ],[0.931 0.946 0.973 ]);\npatch([13.325 17.66 20.66 16.325 13.325 ],[8.33 8.33 11.33 11.33 8.33 ],[1 " "1 1 ]);\npatch([16.325 26.66 23.66 20.66 17.66 13.325 16.325 ],[5.33 5.33 8.33 5.33 8.33 8.33 5.33 ],[0.931 0.946 " "0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');" "disp('reinterpret');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Reinterpret1" SID "217" Ports [1, 1] Position [205, 154, 245, 176] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Reinterpret" SourceType "Xilinx Type Reinterpreter Block" infoedit "Changes signal type without altering the binary representation. You can change the signal between s" "igned and unsigned, and relocate the binary point.

Hardware notes: In hardware this block costs nothing.
Example: Suppose the input is 6 bits wide, signed, with 2 fractional bits, and the output is forced to unsig" "ned with 0 fractional bits. Then an input of -2.0 (1110.00 in binary 2's complement) becomes an output of 56 (111" "000 in binary)." force_arith_type on arith_type "Unsigned" force_bin_pt on bin_pt "0" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "reinterpret" sg_icon_stat "40,22,1,1,white,blue,0,6b04d0b0,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 22 22 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 40 40 0 0 ],[0 0 22 22 0 ]);\npatch([13.325 17.66 20.66 23.66 26.66 20.66 16.325 13.325 ],[14.33 14" ".33 17.33 14.33 17.33 17.33 17.33 14.33 ],[1 1 1 ]);\npatch([16.325 20.66 17.66 13.325 16.325 ],[11.33 11.33 14.33" " 14.33 11.33 ],[0.931 0.946 0.973 ]);\npatch([13.325 17.66 20.66 16.325 13.325 ],[8.33 8.33 11.33 11.33 8.33 ],[1 " "1 1 ]);\npatch([16.325 26.66 23.66 20.66 17.66 13.325 16.325 ],[5.33 5.33 8.33 5.33 8.33 8.33 5.33 ],[0.931 0.946 " "0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');" "disp('reinterpret');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Outport Name "IQ" SID "218" Position [495, 143, 525, 157] IconDisplay "Port number" } Line { SrcBlock "Reinterpret" SrcPort 1 DstBlock "Concat" DstPort 1 } Line { SrcBlock "Reinterpret1" SrcPort 1 DstBlock "Concat" DstPort 2 } Line { SrcBlock "I" SrcPort 1 DstBlock "Reinterpret" DstPort 1 } Line { SrcBlock "Concat" SrcPort 1 DstBlock "IQ" DstPort 1 } Line { SrcBlock "Q" SrcPort 1 DstBlock "Reinterpret1" DstPort 1 } } } Block { BlockType Reference Name "Constant3" SID "219" Ports [0, 1] Position [655, 401, 680, 419] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "0" gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "32" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "8" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" sg_icon_stat "25,18,0,1,white,blue,0,bf4ddd8b,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 18 18 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 18 18 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[11.2" "2 11.22 13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[9.22 9.22 11.22 " "11.22 9.22 ],[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);" "\npatch([9.55 16.44 14.44 12.44 10.44 7.55 9.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\n" "fprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('" "output',1,'0');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Constant4" SID "220" Ports [0, 1] Position [655, 421, 680, 439] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "0" gui_display_data_type "Boolean" arith_type "Boolean" n_bits "6" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "8" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" sg_icon_stat "25,18,0,1,white,blue,0,bf4ddd8b,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 18 18 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 18 18 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[11.2" "2 11.22 13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[9.22 9.22 11.22 " "11.22 9.22 ],[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);" "\npatch([9.55 16.44 14.44 12.44 10.44 7.55 9.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\n" "fprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('" "output',1,'0');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Counter" SID "221" Ports [1, 1] Position [320, 279, 385, 311] NamePlacement "alternate" LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Counter" SourceType "Xilinx Counter Block" infoedit "Hardware notes: Free running counters are the least expensive in hardware. A count limited co" "unter is implemented by combining a counter with a comparator." cnt_type "Free Running" cnt_to "Inf" operation "Up" start_count "0" cnt_by_val "1" arith_type "Unsigned" n_bits "ceil(log2(preFFT_sampBuff_numSamps))" bin_pt "0" load_pin off rst off en on explicit_period "off" period "8" dbl_ovrd off use_behavioral_HDL off implementation "Fabric" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "counter" sg_icon_stat "65,32,1,1,white,blue,0,b089e9c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 65 65 0 0 ],[0 0 32 32 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 65 65 0 0 ],[0 0 32 32 0 ]);\npatch([23.1 28.88 32.88 36.88 40.88 32.88 27.1 23.1 ],[20.4" "4 20.44 24.44 20.44 24.44 24.44 24.44 20.44 ],[1 1 1 ]);\npatch([27.1 32.88 28.88 23.1 27.1 ],[16.44 16.44 20.4" "4 20.44 16.44 ],[0.931 0.946 0.973 ]);\npatch([23.1 28.88 32.88 27.1 23.1 ],[12.44 12.44 16.44 16.44 12.44 ],[1" " 1 1 ]);\npatch([27.1 40.88 36.88 32.88 28.88 23.1 27.1 ],[8.44 8.44 12.44 8.44 12.44 12.44 8.44 ],[0.931 0.946" " 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');" "port_label('input',1,'en');\n\ncolor('black');disp('{\\fontsize{14}\\bf++}','texmode','on');\nfprintf('','COMME" "NT: end icon text');" } Block { BlockType Reference Name "Delay" SID "222" Ports [1, 1] Position [715, 510, 745, 530] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flo" "p." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en off latency "1" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" sg_icon_stat "30,20,1,1,white,blue,0,07b98262,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 20 20 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 20 20 0 ]);\npatch([10.55 13.44 15.44 17.44 19.44 15.44 12.55 10.55 ],[1" "2.22 12.22 14.22 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([12.55 15.44 13.44 10.55 12.55 ],[10.22 10.2" "2 12.22 12.22 10.22 ],[0.931 0.946 0.973 ]);\npatch([10.55 13.44 15.44 12.55 10.55 ],[8.22 8.22 10.22 10.22 8.2" "2 ],[1 1 1 ]);\npatch([12.55 19.44 17.44 15.44 13.44 10.55 12.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.931" " 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor" "('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Delay2" SID "223" Ports [1, 1] Position [715, 490, 745, 510] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flo" "p." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en off latency "1" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" sg_icon_stat "30,20,1,1,white,blue,0,07b98262,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 20 20 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 20 20 0 ]);\npatch([10.55 13.44 15.44 17.44 19.44 15.44 12.55 10.55 ],[1" "2.22 12.22 14.22 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([12.55 15.44 13.44 10.55 12.55 ],[10.22 10.2" "2 12.22 12.22 10.22 ],[0.931 0.946 0.973 ]);\npatch([10.55 13.44 15.44 12.55 10.55 ],[8.22 8.22 10.22 10.22 8.2" "2 ],[1 1 1 ]);\npatch([12.55 19.44 17.44 15.44 13.44 10.55 12.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.931" " 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor" "('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType SubSystem Name "FFT Load Ctrl" SID "224" Ports [6, 5] Position [515, 470, 630, 565] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "FFT Load Ctrl" Location [88, 301, 2330, 1301] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "139" Block { BlockType Inport Name "Wr Addr" SID "225" Position [490, 288, 520, 302] NamePlacement "alternate" IconDisplay "Port number" } Block { BlockType Inport Name "data tready" SID "226" Position [170, 503, 200, 517] NamePlacement "alternate" Port "2" IconDisplay "Port number" } Block { BlockType Inport Name "LTS Sync" SID "227" Position [490, 318, 520, 332] Port "3" IconDisplay "Port number" } Block { BlockType Inport Name "Skip Sel" SID "228" Position [765, 403, 795, 417] NamePlacement "alternate" Port "4" IconDisplay "Port number" } Block { BlockType Inport Name "FFT LTS Load" SID "229" Position [170, 593, 200, 607] Port "5" IconDisplay "Port number" } Block { BlockType Inport Name "FFT Load" SID "230" Position [170, 538, 200, 552] Port "6" IconDisplay "Port number" } Block { BlockType Reference Name "AddSub4" SID "231" Ports [2, 1] Position [1085, 390, 1135, 425] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/AddSub" SourceType "Xilinx Adder/Subtracter Block" mode "Addition" use_carryin off use_carryout off en off latency "0" precision "User Defined" arith_type "Unsigned" n_bits "ceil(log2(preFFT_sampBuff_numSamps))" bin_pt "0" quantization "Truncate" overflow "Wrap" dbl_ovrd off use_behavioral_HDL off hw_selection "Fabric" pipelined off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "addsub" sg_icon_stat "50,35,2,1,white,blue,0,e139daf6,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 50 50 0 0 ],[0 0 35 35 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 50 50 0 0 ],[0 0 35 35 0 ]);\npatch([13.875 21.1 26.1 31.1 36.1 26.1 18.875 13.875 ],[22.55 22.55 2" "7.55 22.55 27.55 27.55 27.55 22.55 ],[1 1 1 ]);\npatch([18.875 26.1 21.1 13.875 18.875 ],[17.55 17.55 22.55 22.55 " "17.55 ],[0.931 0.946 0.973 ]);\npatch([13.875 21.1 26.1 18.875 13.875 ],[12.55 12.55 17.55 17.55 12.55 ],[1 1 1 ])" ";\npatch([18.875 36.1 31.1 26.1 21.1 13.875 18.875 ],[7.55 7.55 12.55 7.55 12.55 12.55 7.55 ],[0.931 0.946 0.973 ]" ");\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label(" "'input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('output',1,'\\bf{a + b}','te" "xmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Convert2" SID "232" Ports [1, 1] Position [265, 501, 290, 519] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do not." gui_display_data_type "Boolean" arith_type "Boolean" n_bits "1" bin_pt "0" float_type "Single" exp_bits "8" fraction_bits "24" quantization "Truncate" overflow "Wrap" en off latency "0" dbl_ovrd off pipeline off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "convert" sg_icon_stat "25,18,1,1,white,blue,0,edca21da,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 18 18 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 25 25 0 0 ],[0 0 18 18 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[11.22 11.22 13" ".22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[9.22 9.22 11.22 11.22 9.22 ]," "[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);\npatch([9.55 16" ".44 14.44 12.44 10.44 7.55 9.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMEN" "T: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('output',1,'cast');\n" "fprintf('','COMMENT: end icon text');" } Block { BlockType SubSystem Name "Count-To Calc" SID "233" Ports [1, 2] Position [915, 391, 975, 429] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "Count-To Calc" Location [904, 1040, 1324, 1205] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "Skip Sel" SID "234" Position [245, 253, 275, 267] NamePlacement "alternate" IconDisplay "Port number" } Block { BlockType Reference Name "AddSub1" SID "235" Ports [2, 1] Position [480, 280, 530, 315] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/AddSub" SourceType "Xilinx Adder/Subtracter Block" mode "Addition" use_carryin off use_carryout off en off latency "0" precision "User Defined" arith_type "Unsigned" n_bits "ceil(log2(preFFT_sampBuff_numSamps))" bin_pt "0" quantization "Truncate" overflow "Wrap" dbl_ovrd off use_behavioral_HDL off hw_selection "Fabric" pipelined off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "addsub" sg_icon_stat "50,35,2,1,white,blue,0,e139daf6,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 50 50 0 0 ],[0 0 35 35 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 50 50 0 0 ],[0 0 35 35 0 ]);\npatch([13.875 21.1 26.1 31.1 36.1 26.1 18.875 13.875 ],[22.55 2" "2.55 27.55 22.55 27.55 27.55 27.55 22.55 ],[1 1 1 ]);\npatch([18.875 26.1 21.1 13.875 18.875 ],[17.55 17.55 22.5" "5 22.55 17.55 ],[0.931 0.946 0.973 ]);\npatch([13.875 21.1 26.1 18.875 13.875 ],[12.55 12.55 17.55 17.55 12.55 ]" ",[1 1 1 ]);\npatch([18.875 36.1 31.1 26.1 21.1 13.875 18.875 ],[7.55 7.55 12.55 7.55 12.55 12.55 7.55 ],[0.931 0" ".946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black" "');port_label('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('output',1,'" "\\bf{a + b}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Constant4" SID "236" Ports [0, 1] Position [305, 281, 330, 299] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "0" gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "1" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "8" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" sg_icon_stat "25,18,0,1,white,blue,0,bf4ddd8b,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 18 18 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 18 18 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[11.22 11" ".22 13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[9.22 9.22 11.22 11.22" " 9.22 ],[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);\npatc" "h([9.55 16.44 14.44 12.44 10.44 7.55 9.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\nfprint" "f('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output'" ",1,'0');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Display Name "Display" SID "237" Ports [1] Position [530, 410, 620, 440] ZOrder -1 ShowName off Decimation "1" Lockdown off } Block { BlockType Display Name "Display1" SID "238" Ports [1] Position [530, 445, 620, 475] ZOrder -1 ShowName off Decimation "1" Lockdown off } Block { BlockType From Name "From2" SID "239" Position [210, 313, 340, 327] ShowName off CloseFcn "tagdialog Close" GotoTag "regRx_CP_LEN" TagVisibility "global" } Block { BlockType From Name "From3" SID "240" Position [210, 343, 340, 357] ShowName off CloseFcn "tagdialog Close" GotoTag "regRx_NUM_SC" TagVisibility "global" } Block { BlockType Reference Name "Gateway Out" SID "241" Ports [1, 1] Position [425, 418, 465, 432] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type" " Simulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top l" "evel output ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "40,14,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 14 14 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 40 40 0 0 ],[0 0 14 14 0 ]);\npatch([15.55 18.44 20.44 22.44 24.44 20.44 17.55 15.55 ],[9.22 " "9.22 11.22 9.22 11.22 11.22 11.22 9.22 ],[1 1 1 ]);\npatch([17.55 20.44 18.44 15.55 17.55 ],[7.22 7.22 9.22 9.22" " 7.22 ],[0.964 0.964 0.964 ]);\npatch([15.55 18.44 20.44 17.55 15.55 ],[5.22 5.22 7.22 7.22 5.22 ],[1 1 1 ]);\np" "atch([17.55 24.44 22.44 20.44 18.44 15.55 17.55 ],[3.22 3.22 5.22 3.22 5.22 5.22 3.22 ],[0.964 0.964 0.964 ]);\n" "fprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('i" "nput',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf('','COMMEN" "T: end icon text');" } Block { BlockType Reference Name "Gateway Out1" SID "242" Ports [1, 1] Position [425, 453, 465, 467] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type" " Simulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top l" "evel output ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "40,14,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 14 14 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 40 40 0 0 ],[0 0 14 14 0 ]);\npatch([15.55 18.44 20.44 22.44 24.44 20.44 17.55 15.55 ],[9.22 " "9.22 11.22 9.22 11.22 11.22 11.22 9.22 ],[1 1 1 ]);\npatch([17.55 20.44 18.44 15.55 17.55 ],[7.22 7.22 9.22 9.22" " 7.22 ],[0.964 0.964 0.964 ]);\npatch([15.55 18.44 20.44 17.55 15.55 ],[5.22 5.22 7.22 7.22 5.22 ],[1 1 1 ]);\np" "atch([17.55 24.44 22.44 20.44 18.44 15.55 17.55 ],[3.22 3.22 5.22 3.22 5.22 5.22 3.22 ],[0.964 0.964 0.964 ]);\n" "fprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('i" "nput',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf('','COMMEN" "T: end icon text');" } Block { BlockType Reference Name "Mux" SID "243" Ports [3, 1] Position [390, 244, 420, 336] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Mux" SourceType "Xilinx Bus Multiplexer Block" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "14" quantization "Truncate" overflow "Wrap" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "mux" sg_icon_stat "30,92,3,1,white,blue,3,eb98d690,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 13.1429 78.8571 92 0 ]" ",[0.77 0.82 0.91 ]);\nplot([0 30 30 0 0 ],[0 13.1429 78.8571 92 0 ]);\npatch([6.1 11.88 15.88 19.88 23.88 15.88 " "10.1 6.1 ],[50.44 50.44 54.44 50.44 54.44 54.44 54.44 50.44 ],[1 1 1 ]);\npatch([10.1 15.88 11.88 6.1 10.1 ],[46" ".44 46.44 50.44 50.44 46.44 ],[0.931 0.946 0.973 ]);\npatch([6.1 11.88 15.88 10.1 6.1 ],[42.44 42.44 46.44 46.44" " 42.44 ],[1 1 1 ]);\npatch([10.1 23.88 19.88 15.88 11.88 6.1 10.1 ],[38.44 38.44 42.44 38.44 42.44 42.44 38.44 ]" ",[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncol" "or('black');port_label('input',1,'sel');\ncolor('black');port_label('input',2,'d0');\ncolor('black');port_label(" "'input',3,'d1');\n\ncolor('black');disp('\\bf{}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Outport Name "Samp+Skip" SID "244" Position [605, 293, 635, 307] IconDisplay "Port number" } Block { BlockType Outport Name "Samp" SID "245" Position [605, 353, 635, 367] Port "2" IconDisplay "Port number" } Line { SrcBlock "From2" SrcPort 1 Points [15, 0] Branch { DstBlock "Mux" DstPort 3 } Branch { Points [0, 105] DstBlock "Gateway Out" DstPort 1 } } Line { SrcBlock "Skip Sel" SrcPort 1 DstBlock "Mux" DstPort 1 } Line { SrcBlock "Constant4" SrcPort 1 DstBlock "Mux" DstPort 2 } Line { SrcBlock "Mux" SrcPort 1 DstBlock "AddSub1" DstPort 1 } Line { SrcBlock "AddSub1" SrcPort 1 DstBlock "Samp+Skip" DstPort 1 } Line { SrcBlock "From3" SrcPort 1 Points [10, 0] Branch { Points [85, 0] Branch { Points [0, -45] DstBlock "AddSub1" DstPort 2 } Branch { Points [0, 10] DstBlock "Samp" DstPort 1 } } Branch { Points [0, 110] DstBlock "Gateway Out1" DstPort 1 } } Line { SrcBlock "Gateway Out" SrcPort 1 DstBlock "Display" DstPort 1 } Line { SrcBlock "Gateway Out1" SrcPort 1 DstBlock "Display1" DstPort 1 } } } Block { BlockType Scope Name "Ctrl" SID "246" Ports [7] Position [1540, 143, 1575, 237] ZOrder -3 Floating off Location [1389, 159, 2380, 1503] Open off NumInputPorts "7" ZoomMode "xonly" List { ListType AxesTitles axes1 "%" axes2 "%" axes3 "%" axes4 "%" axes5 "%" axes6 "%" axes7 "%" } List { ListType ScopeGraphics FigureColor "[0.5 0.5 0.5]" AxesColor "[0 0 0]" AxesTickColor "[1 1 1]" LineColors "[1 1 0;1 0 1;0 1 1;1 0 0;0 1 0;0 0 1]" LineStyles "-|-|-|-|-|-" LineWidths "[0.5 0.5 0.5 0.5 0.5 0.5]" MarkerStyles "none|none|none|none|none|none" } TimeRange "1322.580645161291" YMin "-1~70~59.85~166.25~-1~-1~166.25" YMax "1~135~66.15~183.75~1~1~183.75" SaveName "ScopeData5" DataFormat "StructureWithTime" LimitDataPoints off SampleTime "0" } Block { BlockType Reference Name "Delay" SID "247" Ports [1, 1] Position [655, 455, 685, 485] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flop." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en off latency "1" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" sg_icon_stat "30,30,1,1,white,blue,0,07b98262,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 30 30 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 30 30 0 0 ],[0 0 30 30 0 ]);\npatch([6.1 11.88 15.88 19.88 23.88 15.88 10.1 6.1 ],[19.44 19.44 23.4" "4 19.44 23.44 23.44 23.44 19.44 ],[1 1 1 ]);\npatch([10.1 15.88 11.88 6.1 10.1 ],[15.44 15.44 19.44 19.44 15.44 ]," "[0.931 0.946 0.973 ]);\npatch([6.1 11.88 15.88 10.1 6.1 ],[11.44 11.44 15.44 15.44 11.44 ],[1 1 1 ]);\npatch([10.1" " 23.88 19.88 15.88 11.88 6.1 10.1 ],[7.44 7.44 11.44 7.44 11.44 11.44 7.44 ],[0.931 0.946 0.973 ]);\nfprintf('','C" "OMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');disp('z^{-1}','texmode'," "'on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType SubSystem Name "First Samp\nCalc" SID "248" Ports [2, 1] Position [635, 280, 710, 340] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "First Samp\nCalc" Location [677, 751, 1183, 937] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "Wr Addr" SID "249" Position [220, 193, 250, 207] NamePlacement "alternate" IconDisplay "Port number" } Block { BlockType Inport Name "LTS Sync" SID "250" Position [220, 213, 250, 227] Port "2" IconDisplay "Port number" } Block { BlockType Reference Name "AddSub2" SID "251" Ports [2, 1] Position [585, 179, 620, 306] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/AddSub" SourceType "Xilinx Adder/Subtracter Block" mode "Subtraction" use_carryin off use_carryout off en off latency "0" precision "User Defined" arith_type "Unsigned" n_bits "ceil(log2(preFFT_sampBuff_numSamps))" bin_pt "0" quantization "Truncate" overflow "Wrap" dbl_ovrd off use_behavioral_HDL off hw_selection "Fabric" pipelined off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "addsub" sg_icon_stat "35,127,2,1,white,blue,0,32e1f85f,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 127 127 0 ],[0.77 0." "82 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 127 127 0 ]);\npatch([5.875 13.1 18.1 23.1 28.1 18.1 10.875 5.875 ],[68.55" " 68.55 73.55 68.55 73.55 73.55 73.55 68.55 ],[1 1 1 ]);\npatch([10.875 18.1 13.1 5.875 10.875 ],[63.55 63.55 68." "55 68.55 63.55 ],[0.931 0.946 0.973 ]);\npatch([5.875 13.1 18.1 10.875 5.875 ],[58.55 58.55 63.55 63.55 58.55 ]," "[1 1 1 ]);\npatch([10.875 28.1 23.1 18.1 13.1 5.875 10.875 ],[53.55 53.55 58.55 53.55 58.55 58.55 53.55 ],[0.931" " 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('bla" "ck');port_label('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('output',1" ",'\\bf{a - b}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "AddSub3" SID "252" Ports [2, 1] Position [440, 247, 485, 303] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/AddSub" SourceType "Xilinx Adder/Subtracter Block" mode "Addition" use_carryin off use_carryout off en off latency "0" precision "User Defined" arith_type "Unsigned" n_bits "ceil(log2(preFFT_sampBuff_numSamps))" bin_pt "0" quantization "Truncate" overflow "Wrap" dbl_ovrd off use_behavioral_HDL off hw_selection "Fabric" pipelined off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "addsub" sg_icon_stat "45,56,2,1,white,blue,0,e139daf6,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 56 56 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 45 45 0 0 ],[0 0 56 56 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[34.66 3" "4.66 40.66 34.66 40.66 40.66 40.66 34.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[28.66 28.66 34.66 " "34.66 28.66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[22.66 22.66 28.66 28.66 22.66 ],[1 1" " 1 ]);\npatch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[16.66 16.66 22.66 16.66 22.66 22.66 16.66 ],[0.931 0." "946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black'" ");port_label('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('output',1,'\\" "bf{a + b}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType From Name "From1" SID "253" Position [170, 253, 300, 267] ShowName off CloseFcn "tagdialog Close" GotoTag "regRx_NUM_SC" TagVisibility "global" } Block { BlockType From Name "From2" SID "254" Position [170, 283, 300, 297] ShowName off CloseFcn "tagdialog Close" GotoTag "regRx_FFT_OFFSET" TagVisibility "global" } Block { BlockType Reference Name "Register" SID "255" Ports [2, 1] Position [405, 192, 445, 228] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "40,36,2,1,white,blue,0,6bd0930c,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 36 36 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 36 36 0 ]);\npatch([8.875 16.1 21.1 26.1 31.1 21.1 13.875 8.875 ],[23.55 23." "55 28.55 23.55 28.55 28.55 28.55 23.55 ],[1 1 1 ]);\npatch([13.875 21.1 16.1 8.875 13.875 ],[18.55 18.55 23.55 2" "3.55 18.55 ],[0.931 0.946 0.973 ]);\npatch([8.875 16.1 21.1 13.875 8.875 ],[13.55 13.55 18.55 18.55 13.55 ],[1 1" " 1 ]);\npatch([13.875 31.1 26.1 21.1 16.1 8.875 13.875 ],[8.55 8.55 13.55 8.55 13.55 13.55 8.55 ],[0.931 0.946 0" ".973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');por" "t_label('input',1,'d');\ncolor('black');port_label('input',2,'en');\ncolor('black');port_label('output',1,'q');\n" "color('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Shift" SID "256" Ports [1, 1] Position [355, 246, 405, 274] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Shift" SourceType "Xilinx Binary Shift Operator Block" infoedit "Hardware notes: In hardware this block costs nothing if full output precision is used." shift_dir "Left" shift_bits "1" en off latency "0" precision "Full" arith_type "Signed (2's comp)" n_bits "16" bin_pt "14" quantization "Truncate" overflow "Wrap" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "shift" sg_icon_stat "50,28,1,1,white,blue,0,6c6aa2df,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 50 50 0 0 ],[0 0 28 28 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 50 50 0 0 ],[0 0 28 28 0 ]);\npatch([16.1 21.88 25.88 29.88 33.88 25.88 20.1 16.1 ],[18.44 18" ".44 22.44 18.44 22.44 22.44 22.44 18.44 ],[1 1 1 ]);\npatch([20.1 25.88 21.88 16.1 20.1 ],[14.44 14.44 18.44 18." "44 14.44 ],[0.931 0.946 0.973 ]);\npatch([16.1 21.88 25.88 20.1 16.1 ],[10.44 10.44 14.44 14.44 10.44 ],[1 1 1 ]" ");\npatch([20.1 33.88 29.88 25.88 21.88 16.1 20.1 ],[6.44 6.44 10.44 6.44 10.44 10.44 6.44 ],[0.931 0.946 0.973 " "]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');disp" "('\\bf{X << 1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Outport Name "Samp Addr" SID "257" Position [695, 238, 725, 252] IconDisplay "Port number" } Line { SrcBlock "From1" SrcPort 1 DstBlock "Shift" DstPort 1 } Line { SrcBlock "Shift" SrcPort 1 DstBlock "AddSub3" DstPort 1 } Line { SrcBlock "AddSub3" SrcPort 1 DstBlock "AddSub2" DstPort 2 } Line { SrcBlock "Register" SrcPort 1 DstBlock "AddSub2" DstPort 1 } Line { SrcBlock "Wr Addr" SrcPort 1 DstBlock "Register" DstPort 1 } Line { SrcBlock "AddSub2" SrcPort 1 DstBlock "Samp Addr" DstPort 1 } Line { SrcBlock "LTS Sync" SrcPort 1 DstBlock "Register" DstPort 2 } Line { SrcBlock "From2" SrcPort 1 DstBlock "AddSub3" DstPort 2 } Annotation { Name "NUM_SC = length(LTS), so 2*NUM_SC points to first sample of first LTS\nFFT_OFFSET adjusts this pointe" "r into the 32-sample cyclic prefix\nin front of the first LTS." Position [236, 382] HorizontalAlignment "left" } } } Block { BlockType Reference Name "Gateway Out1" SID "258" Ports [1, 1] Position [1395, 139, 1430, 151] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type Sim" "ulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top level o" "utput ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0.88 0.8" "8 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[7.11 7.1" "1 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7.11 7.11 6.11 " "],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]);\npatch(" "[15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.964 ]);\nfpri" "ntf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input'," "1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf('','COMMENT: end i" "con text');" Port { PortNumber 1 Name "LTS Sync" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out2" SID "259" Ports [1, 1] Position [1395, 154, 1430, 166] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type Sim" "ulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top level o" "utput ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0.88 0.8" "8 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[7.11 7.1" "1 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7.11 7.11 6.11 " "],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]);\npatch(" "[15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.964 ]);\nfpri" "ntf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input'," "1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf('','COMMENT: end i" "con text');" Port { PortNumber 1 Name "Rx Samp Ind" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out3" SID "260" Ports [1, 1] Position [1395, 169, 1430, 181] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type Sim" "ulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top level o" "utput ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0.88 0.8" "8 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[7.11 7.1" "1 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7.11 7.11 6.11 " "],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]);\npatch(" "[15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.964 ]);\nfpri" "ntf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input'," "1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf('','COMMENT: end i" "con text');" Port { PortNumber 1 Name "Init Samp Addr" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out4" SID "261" Ports [1, 1] Position [1395, 184, 1430, 196] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type Sim" "ulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top level o" "utput ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0.88 0.8" "8 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[7.11 7.1" "1 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7.11 7.11 6.11 " "],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]);\npatch(" "[15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.964 ]);\nfpri" "ntf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input'," "1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf('','COMMENT: end i" "con text');" Port { PortNumber 1 Name "Rd Counter" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out5" SID "262" Ports [1, 1] Position [1395, 214, 1430, 226] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type Sim" "ulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top level o" "utput ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0.88 0.8" "8 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[7.11 7.1" "1 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7.11 7.11 6.11 " "],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]);\npatch(" "[15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.964 ]);\nfpri" "ntf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input'," "1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf('','COMMENT: end i" "con text');" Port { PortNumber 1 Name "FFT tvalid" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out6" SID "263" Ports [1, 1] Position [1395, 229, 1430, 241] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type Sim" "ulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top level o" "utput ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0.88 0.8" "8 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[7.11 7.1" "1 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7.11 7.11 6.11 " "],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]);\npatch(" "[15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.964 ]);\nfpri" "ntf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input'," "1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf('','COMMENT: end i" "con text');" Port { PortNumber 1 Name "Rd Addr" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out7" SID "264" Ports [1, 1] Position [1395, 199, 1430, 211] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type Sim" "ulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top level o" "utput ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0.88 0.8" "8 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[7.11 7.1" "1 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7.11 7.11 6.11 " "],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]);\npatch(" "[15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.964 ]);\nfpri" "ntf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input'," "1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf('','COMMENT: end i" "con text');" Port { PortNumber 1 Name "Samp Counter" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Inverter" SID "265" Ports [1, 1] Position [600, 606, 625, 624] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Inverter" SourceType "Xilinx Inverter Block" infoedit "Bitwise logical negation (one's complement) operator." en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "inv" block_version "VER_STRING_GOES_HERE" sg_icon_stat "25,18,1,1,white,blue,0,267846e5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 18 18 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 25 25 0 0 ],[0 0 18 18 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[11.22 11.22 13" ".22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[9.22 9.22 11.22 11.22 9.22 ]," "[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);\npatch([9.55 16" ".44 14.44 12.44 10.44 7.55 9.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMEN" "T: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');disp('not');\nfprintf('','COM" "MENT: end icon text');" } Block { BlockType Reference Name "Logical" SID "266" Ports [2, 1] Position [285, 534, 325, 576] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "AND" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" sg_icon_stat "40,42,2,1,white,blue,0,83a4b621,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 42 42 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 40 40 0 0 ],[0 0 42 42 0 ]);\npatch([8.875 16.1 21.1 26.1 31.1 21.1 13.875 8.875 ],[26.55 26.55 31." "55 26.55 31.55 31.55 31.55 26.55 ],[1 1 1 ]);\npatch([13.875 21.1 16.1 8.875 13.875 ],[21.55 21.55 26.55 26.55 21." "55 ],[0.931 0.946 0.973 ]);\npatch([8.875 16.1 21.1 13.875 8.875 ],[16.55 16.55 21.55 21.55 16.55 ],[1 1 1 ]);\npa" "tch([13.875 31.1 26.1 21.1 16.1 8.875 13.875 ],[11.55 11.55 16.55 11.55 16.55 16.55 11.55 ],[0.931 0.946 0.973 ]);" "\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\ncolor('black');disp('a" "nd');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical1" SID "267" Ports [2, 1] Position [845, 494, 875, 521] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "OR" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" sg_icon_stat "30,27,2,1,white,blue,0,7ede7d88,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 27 27 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 30 30 0 0 ],[0 0 27 27 0 ]);\npatch([8.325 12.66 15.66 18.66 21.66 15.66 11.325 8.325 ],[16.33 16.3" "3 19.33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([11.325 15.66 12.66 8.325 11.325 ],[13.33 13.33 16.33 16" ".33 13.33 ],[0.931 0.946 0.973 ]);\npatch([8.325 12.66 15.66 11.325 8.325 ],[10.33 10.33 13.33 13.33 10.33 ],[1 1 " "1 ]);\npatch([11.325 21.66 18.66 15.66 12.66 8.325 11.325 ],[7.33 7.33 10.33 7.33 10.33 10.33 7.33 ],[0.931 0.946 " "0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\ncolor('black'" ");disp('or');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical2" SID "268" Ports [2, 1] Position [1205, 569, 1245, 611] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "AND" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" sg_icon_stat "40,42,2,1,white,blue,0,83a4b621,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 42 42 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 40 40 0 0 ],[0 0 42 42 0 ]);\npatch([8.875 16.1 21.1 26.1 31.1 21.1 13.875 8.875 ],[26.55 26.55 31." "55 26.55 31.55 31.55 31.55 26.55 ],[1 1 1 ]);\npatch([13.875 21.1 16.1 8.875 13.875 ],[21.55 21.55 26.55 26.55 21." "55 ],[0.931 0.946 0.973 ]);\npatch([8.875 16.1 21.1 13.875 8.875 ],[16.55 16.55 21.55 21.55 16.55 ],[1 1 1 ]);\npa" "tch([13.875 31.1 26.1 21.1 16.1 8.875 13.875 ],[11.55 11.55 16.55 11.55 16.55 16.55 11.55 ],[0.931 0.946 0.973 ]);" "\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\ncolor('black');disp('a" "nd');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical3" SID "269" Ports [2, 1] Position [355, 544, 395, 586] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "OR" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" sg_icon_stat "40,42,2,1,white,blue,0,7ede7d88,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 42 42 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 40 40 0 0 ],[0 0 42 42 0 ]);\npatch([8.875 16.1 21.1 26.1 31.1 21.1 13.875 8.875 ],[26.55 26.55 31." "55 26.55 31.55 31.55 31.55 26.55 ],[1 1 1 ]);\npatch([13.875 21.1 16.1 8.875 13.875 ],[21.55 21.55 26.55 26.55 21." "55 ],[0.931 0.946 0.973 ]);\npatch([8.875 16.1 21.1 13.875 8.875 ],[16.55 16.55 21.55 21.55 16.55 ],[1 1 1 ]);\npa" "tch([13.875 31.1 26.1 21.1 16.1 8.875 13.875 ],[11.55 11.55 16.55 11.55 16.55 16.55 11.55 ],[0.931 0.946 0.973 ]);" "\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\ncolor('black');disp('o" "r');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical4" SID "270" Ports [3, 1] Position [665, 504, 705, 546] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "AND" inputs "3" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" sg_icon_stat "40,42,3,1,white,blue,0,98d76266,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 42 42 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 40 40 0 0 ],[0 0 42 42 0 ]);\npatch([8.875 16.1 21.1 26.1 31.1 21.1 13.875 8.875 ],[26.55 26.55 31." "55 26.55 31.55 31.55 31.55 26.55 ],[1 1 1 ]);\npatch([13.875 21.1 16.1 8.875 13.875 ],[21.55 21.55 26.55 26.55 21." "55 ],[0.931 0.946 0.973 ]);\npatch([8.875 16.1 21.1 13.875 8.875 ],[16.55 16.55 21.55 21.55 16.55 ],[1 1 1 ]);\npa" "tch([13.875 31.1 26.1 21.1 16.1 8.875 13.875 ],[11.55 11.55 16.55 11.55 16.55 16.55 11.55 ],[0.931 0.946 0.973 ]);" "\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\n\ncolor('black');disp(" "'and');\nfprintf('','COMMENT: end icon text');" } Block { BlockType SubSystem Name "Posedge" SID "271" Ports [1, 1] Position [1265, 733, 1320, 757] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "Posedge" Location [384, 656, 940, 879] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "D" SID "272" Position [200, 253, 230, 267] IconDisplay "Port number" } Block { BlockType Reference Name "Delay" SID "273" Ports [1, 1] Position [425, 153, 460, 177] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flop. " "If register retiming is enabled, the delay line is a chain of flip-flops." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en off latency "1" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[1 1 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,24,1,1,white,blue,0,07b98262,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 24 24 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 24 24 0 ]);\npatch([10.325 14.66 17.66 20.66 23.66 17.66 13.325 10.325 ],[15" ".33 15.33 18.33 15.33 18.33 18.33 18.33 15.33 ],[1 1 1 ]);\npatch([13.325 17.66 14.66 10.325 13.325 ],[12.33 12." "33 15.33 15.33 12.33 ],[0.931 0.946 0.973 ]);\npatch([10.325 14.66 17.66 13.325 10.325 ],[9.33 9.33 12.33 12.33 " "9.33 ],[1 1 1 ]);\npatch([13.325 23.66 20.66 17.66 14.66 10.325 13.325 ],[6.33 6.33 9.33 6.33 9.33 9.33 6.33 ],[" "0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\nc" "olor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Inverter" SID "274" Ports [1, 1] Position [490, 156, 515, 174] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Inverter" SourceType "Xilinx Inverter Block" infoedit "Bitwise logical negation (one's complement) operator." en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "inv" block_version "VER_STRING_GOES_HERE" sg_icon_stat "25,18,1,1,white,blue,0,267846e5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 18 18 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 18 18 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[11.22 11" ".22 13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[9.22 9.22 11.22 11.22" " 9.22 ],[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);\npatc" "h([9.55 16.44 14.44 12.44 10.44 7.55 9.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\nfprint" "f('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');disp('not');\nf" "printf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical1" SID "275" Ports [2, 1] Position [540, 151, 585, 204] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "AND" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "8" bin_pt "2" align_bp on dbl_ovrd off xl_use_area off xl_area "[1 0 0 1 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" block_version "VER_STRING_GOES_HERE" sg_icon_stat "45,53,2,1,white,blue,0,83a4b621,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 53 53 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 45 45 0 0 ],[0 0 53 53 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[32.66 3" "2.66 38.66 32.66 38.66 38.66 38.66 32.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[26.66 26.66 32.66 " "32.66 26.66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[20.66 20.66 26.66 26.66 20.66 ],[1 1" " 1 ]);\npatch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[14.66 14.66 20.66 14.66 20.66 20.66 14.66 ],[0.931 0." "946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\ncolor('" "black');disp('and');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Outport Name "Q" SID "276" Position [610, 173, 640, 187] IconDisplay "Port number" } Line { SrcBlock "D" SrcPort 1 Points [150, 0; 0, -70] Branch { DstBlock "Logical1" DstPort 2 } Branch { Points [0, -25] DstBlock "Delay" DstPort 1 } } Line { SrcBlock "Logical1" SrcPort 1 DstBlock "Q" DstPort 1 } Line { SrcBlock "Inverter" SrcPort 1 DstBlock "Logical1" DstPort 1 } Line { SrcBlock "Delay" SrcPort 1 DstBlock "Inverter" DstPort 1 } Annotation { Name "Rising Edge Detection" Position [500, 112] } } } Block { BlockType Reference Name "Rd Counter" SID "277" Ports [3, 1] Position [915, 463, 975, 517] NamePlacement "alternate" LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Counter" SourceType "Xilinx Counter Block" infoedit "Hardware notes: Free running counters are the least expensive in hardware. A count limited counter i" "s implemented by combining a counter with a comparator." cnt_type "Free Running" cnt_to "Inf" operation "Up" start_count "0" cnt_by_val "1" arith_type "Unsigned" n_bits "ceil(log2(preFFT_sampBuff_numSamps))" bin_pt "0" load_pin on rst off en on explicit_period "off" period "8" dbl_ovrd off use_behavioral_HDL off implementation "Fabric" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "counter" sg_icon_stat "60,54,3,1,white,blue,0,4f561634,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 0 ],[0 0 54 54 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 60 60 0 0 ],[0 0 54 54 0 ]);\npatch([14.425 24.54 31.54 38.54 45.54 31.54 21.425 14.425 ],[34.77 34" ".77 41.77 34.77 41.77 41.77 41.77 34.77 ],[1 1 1 ]);\npatch([21.425 31.54 24.54 14.425 21.425 ],[27.77 27.77 34.77" " 34.77 27.77 ],[0.931 0.946 0.973 ]);\npatch([14.425 24.54 31.54 21.425 14.425 ],[20.77 20.77 27.77 27.77 20.77 ]," "[1 1 1 ]);\npatch([21.425 45.54 38.54 31.54 24.54 14.425 21.425 ],[13.77 13.77 20.77 13.77 20.77 20.77 13.77 ],[0." "931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('bl" "ack');port_label('input',1,'load');\ncolor('black');port_label('input',2,'din');\ncolor('black');port_label('input" "',3,'en');\n\ncolor('black');disp('{\\fontsize{14}\\bf++}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Relational1" SID "278" Ports [2, 1] Position [1225, 379, 1270, 421] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Relational" SourceType "Xilinx Arithmetic Relational Operator Block" mode "a=b" en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "relational" sg_icon_stat "45,42,2,1,white,blue,0,2a81ff49,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 42 42 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 45 45 0 0 ],[0 0 42 42 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[27.66 27.66 3" "3.66 27.66 33.66 33.66 33.66 27.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[21.66 21.66 27.66 27.66 21" ".66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[15.66 15.66 21.66 21.66 15.66 ],[1 1 1 ]);\npa" "tch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[9.66 9.66 15.66 9.66 15.66 15.66 9.66 ],[0.931 0.946 0.973 ]);\nf" "printf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('inpu" "t',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('output',1,'\\bfa = b','texmode'," "'on');\ncolor('black');disp(' ');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Relational2" SID "279" Ports [2, 1] Position [1045, 624, 1090, 666] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Relational" SourceType "Xilinx Arithmetic Relational Operator Block" mode "a=b" en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "relational" sg_icon_stat "45,42,2,1,white,blue,0,2a81ff49,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 42 42 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 45 45 0 0 ],[0 0 42 42 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[27.66 27.66 3" "3.66 27.66 33.66 33.66 33.66 27.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[21.66 21.66 27.66 27.66 21" ".66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[15.66 15.66 21.66 21.66 15.66 ],[1 1 1 ]);\npa" "tch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[9.66 9.66 15.66 9.66 15.66 15.66 9.66 ],[0.931 0.946 0.973 ]);\nf" "printf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('inpu" "t',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('output',1,'\\bfa = b','texmode'," "'on');\ncolor('black');disp(' ');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Relational3" SID "280" Ports [2, 1] Position [1045, 534, 1090, 576] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Relational" SourceType "Xilinx Arithmetic Relational Operator Block" mode "a<=b" en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "relational" sg_icon_stat "45,42,2,1,white,blue,0,52e4b236,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 42 42 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 45 45 0 0 ],[0 0 42 42 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[27.66 27.66 3" "3.66 27.66 33.66 33.66 33.66 27.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[21.66 21.66 27.66 27.66 21" ".66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[15.66 15.66 21.66 21.66 15.66 ],[1 1 1 ]);\npa" "tch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[9.66 9.66 15.66 9.66 15.66 15.66 9.66 ],[0.931 0.946 0.973 ]);\nf" "printf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('inpu" "t',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('output',1,'\\bfa \\leq b','texmo" "de','on');\ncolor('black');disp(' ');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Relational4" SID "281" Ports [2, 1] Position [1045, 579, 1090, 621] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Relational" SourceType "Xilinx Arithmetic Relational Operator Block" mode "a>b" en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "relational" sg_icon_stat "45,42,2,1,white,blue,0,b5131c97,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 42 42 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 45 45 0 0 ],[0 0 42 42 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[27.66 27.66 3" "3.66 27.66 33.66 33.66 33.66 27.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[21.66 21.66 27.66 27.66 21" ".66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[15.66 15.66 21.66 21.66 15.66 ],[1 1 1 ]);\npa" "tch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[9.66 9.66 15.66 9.66 15.66 15.66 9.66 ],[0.931 0.946 0.973 ]);\nf" "printf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('inpu" "t',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('output',1,'\\bfa > b','texmode'," "'on');\ncolor('black');disp(' ');\nfprintf('','COMMENT: end icon text');" } Block { BlockType SubSystem Name "S-R Latch1" SID "282" Ports [2, 1] Position [570, 558, 605, 587] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "S-R Latch1" Location [351, 366, 2001, 1172] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "S" SID "283" Position [140, 103, 170, 117] IconDisplay "Port number" } Block { BlockType Inport Name "R" SID "284" Position [140, 88, 170, 102] NamePlacement "alternate" Port "2" IconDisplay "Port number" } Block { BlockType Reference Name "Constant1" SID "285" Ports [0, 1] Position [195, 71, 210, 89] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "1" gui_display_data_type "Fixed-point" arith_type "Boolean" n_bits "1" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" block_version "VER_STRING_GOES_HERE" sg_icon_stat "15,18,0,1,white,blue,0,1c72b5be,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 15 15 0 0 ],[0 0 18 18 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 15 15 0 0 ],[0 0 18 18 0 ]);\npatch([2.55 5.44 7.44 9.44 11.44 7.44 4.55 2.55 ],[11.22 11.22 " "13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([4.55 7.44 5.44 2.55 4.55 ],[9.22 9.22 11.22 11.22 9.22 " "],[0.931 0.946 0.973 ]);\npatch([2.55 5.44 7.44 4.55 2.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);\npatch([4.55 " "11.44 9.44 7.44 5.44 2.55 4.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\nfprintf('','COMME" "NT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'1');\nf" "printf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Convert1" SID "286" Ports [1, 1] Position [210, 86, 235, 104] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do no" "t." gui_display_data_type "Boolean" arith_type "Boolean" n_bits "1" bin_pt "0" float_type "Single" exp_bits "8" fraction_bits "24" quantization "Truncate" overflow "Wrap" en off latency "0" dbl_ovrd off pipeline off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "convert" sg_icon_stat "25,18,1,1,white,blue,0,edca21da,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 18 18 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 18 18 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[11.22 11" ".22 13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[9.22 9.22 11.22 11.22" " 9.22 ],[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);\npatc" "h([9.55 16.44 14.44 12.44 10.44 7.55 9.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\nfprint" "f('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('outpu" "t',1,'cast');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Convert2" SID "287" Ports [1, 1] Position [210, 101, 235, 119] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do no" "t." gui_display_data_type "Boolean" arith_type "Boolean" n_bits "1" bin_pt "0" float_type "Single" exp_bits "8" fraction_bits "24" quantization "Truncate" overflow "Wrap" en off latency "0" dbl_ovrd off pipeline off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "convert" sg_icon_stat "25,18,1,1,white,blue,0,edca21da,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 18 18 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 18 18 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[11.22 11" ".22 13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[9.22 9.22 11.22 11.22" " 9.22 ],[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);\npatc" "h([9.55 16.44 14.44 12.44 10.44 7.55 9.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\nfprint" "f('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('outpu" "t',1,'cast');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register2" SID "288" Ports [3, 1] Position [255, 71, 300, 119] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst on en on dbl_ovrd off xl_use_area off xl_area "[1 1 0 0 0 0 0]" has_advanced_control "0" sggui_pos "20,20,348,193" block_type "register" block_version "VER_STRING_GOES_HERE" sg_icon_stat "45,48,3,1,white,blue,0,30546de1,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 48 48 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 45 45 0 0 ],[0 0 48 48 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[30.66 3" "0.66 36.66 30.66 36.66 36.66 36.66 30.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[24.66 24.66 30.66 " "30.66 24.66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[18.66 18.66 24.66 24.66 18.66 ],[1 1" " 1 ]);\npatch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[12.66 12.66 18.66 12.66 18.66 18.66 12.66 ],[0.931 0." "946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black'" ");port_label('input',1,'d');\ncolor('black');port_label('input',2,'rst');\ncolor('black');port_label('input',3,'" "en');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','CO" "MMENT: end icon text');" } Block { BlockType Outport Name "Q" SID "289" Position [325, 88, 355, 102] IconDisplay "Port number" } Line { SrcBlock "S" SrcPort 1 DstBlock "Convert2" DstPort 1 } Line { SrcBlock "Register2" SrcPort 1 DstBlock "Q" DstPort 1 } Line { SrcBlock "R" SrcPort 1 DstBlock "Convert1" DstPort 1 } Line { SrcBlock "Constant1" SrcPort 1 DstBlock "Register2" DstPort 1 } Line { SrcBlock "Convert1" SrcPort 1 DstBlock "Register2" DstPort 2 } Line { SrcBlock "Convert2" SrcPort 1 DstBlock "Register2" DstPort 3 } } } Block { BlockType Reference Name "Samp Counter" SID "290" Ports [2, 1] Position [915, 537, 975, 588] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Counter" SourceType "Xilinx Counter Block" infoedit "Hardware notes: Free running counters are the least expensive in hardware. A count limited counter i" "s implemented by combining a counter with a comparator." cnt_type "Free Running" cnt_to "Inf" operation "Up" start_count "0" cnt_by_val "1" arith_type "Unsigned" n_bits "ceil(log2(MAX_NUM_SC+MAX_CP_LEN))" bin_pt "0" load_pin off rst on en on explicit_period "off" period "8" dbl_ovrd off use_behavioral_HDL off implementation "Fabric" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "counter" sg_icon_stat "60,51,2,1,white,blue,0,ae3608d6,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 0 ],[0 0 51 51 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 60 60 0 0 ],[0 0 51 51 0 ]);\npatch([14.425 24.54 31.54 38.54 45.54 31.54 21.425 14.425 ],[32.77 32" ".77 39.77 32.77 39.77 39.77 39.77 32.77 ],[1 1 1 ]);\npatch([21.425 31.54 24.54 14.425 21.425 ],[25.77 25.77 32.77" " 32.77 25.77 ],[0.931 0.946 0.973 ]);\npatch([14.425 24.54 31.54 21.425 14.425 ],[18.77 18.77 25.77 25.77 18.77 ]," "[1 1 1 ]);\npatch([21.425 45.54 38.54 31.54 24.54 14.425 21.425 ],[11.77 11.77 18.77 11.77 18.77 18.77 11.77 ],[0." "931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('bl" "ack');port_label('input',1,'rst');\ncolor('black');port_label('input',2,'en');\n\ncolor('black');disp('{\\fontsize" "{14}\\bf++}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Outport Name "Rd Addr" SID "291" Position [1265, 483, 1295, 497] IconDisplay "Port number" } Block { BlockType Outport Name "Reading" SID "292" Position [1195, 773, 1225, 787] Port "2" IconDisplay "Port number" } Block { BlockType Outport Name "FFT tvalid" SID "293" Position [1420, 583, 1450, 597] Port "3" IconDisplay "Port number" } Block { BlockType Outport Name "FFT tlast" SID "294" Position [1420, 638, 1450, 652] Port "4" IconDisplay "Port number" } Block { BlockType Outport Name "FFT Load Done" SID "295" Position [1420, 738, 1450, 752] Port "5" IconDisplay "Port number" } Line { SrcBlock "Posedge" SrcPort 1 DstBlock "FFT Load Done" DstPort 1 } Line { SrcBlock "data tready" SrcPort 1 DstBlock "Convert2" DstPort 1 } Line { SrcBlock "Wr Addr" SrcPort 1 Points [60, 0] Branch { Labels [0, 0] DstBlock "First Samp\nCalc" DstPort 1 } Branch { Points [0, -30] Branch { Points [565, 0; 0, 125] DstBlock "Relational1" DstPort 1 } Branch { Points [0, -105] DstBlock "Gateway Out2" DstPort 1 } } } Line { SrcBlock "First Samp\nCalc" SrcPort 1 Points [115, 0] Branch { Points [0, 180] DstBlock "Rd Counter" DstPort 2 } Branch { Points [0, -135] DstBlock "Gateway Out3" DstPort 1 } } Line { SrcBlock "Rd Counter" SrcPort 1 Points [15, 0] Branch { Points [65, 0] Branch { Points [0, -75] DstBlock "AddSub4" DstPort 2 } Branch { Points [140, 0] Branch { DstBlock "Rd Addr" DstPort 1 } Branch { Points [0, -255] DstBlock "Gateway Out6" DstPort 1 } } } Branch { Points [0, -300] DstBlock "Gateway Out4" DstPort 1 } } Line { SrcBlock "Skip Sel" SrcPort 1 DstBlock "Count-To Calc" DstPort 1 } Line { SrcBlock "Count-To Calc" SrcPort 1 Points [40, 0] Branch { DstBlock "AddSub4" DstPort 1 } Branch { Points [0, 145] DstBlock "Relational3" DstPort 1 } } Line { SrcBlock "AddSub4" SrcPort 1 DstBlock "Relational1" DstPort 2 } Line { SrcBlock "Logical4" SrcPort 1 Points [75, 0] Branch { Points [0, 50] DstBlock "Samp Counter" DstPort 2 } Branch { Points [0, -10] DstBlock "Logical1" DstPort 2 } } Line { SrcBlock "Convert2" SrcPort 1 DstBlock "Logical4" DstPort 1 } Line { SrcBlock "FFT Load" SrcPort 1 DstBlock "Logical" DstPort 1 } Line { SrcBlock "S-R Latch1" SrcPort 1 Points [20, 0; 0, -10] Branch { Points [0, -40] DstBlock "Logical4" DstPort 2 } Branch { Points [205, 0; 0, -40; 355, 0] DstBlock "Logical2" DstPort 1 } } Line { SrcBlock "Relational1" SrcPort 1 Points [20, 0; 0, 300; -1060, 0; 0, -135] DstBlock "Logical" DstPort 2 } Line { SrcBlock "Samp Counter" SrcPort 1 Points [20, 0] Branch { DstBlock "Relational3" DstPort 2 } Branch { Points [0, 45] Branch { DstBlock "Relational4" DstPort 2 } Branch { Points [0, 45] DstBlock "Relational2" DstPort 2 } } Branch { Points [0, -360] DstBlock "Gateway Out7" DstPort 1 } } Line { SrcBlock "Relational3" SrcPort 1 Points [30, 0; 0, 135; -245, 0] Branch { Points [0, -140] DstBlock "Samp Counter" DstPort 1 } Branch { Points [0, 55] DstBlock "Posedge" DstPort 1 } Branch { Points [-430, 0; 0, -75] Branch { DstBlock "Inverter" DstPort 1 } Branch { Points [0, -35] DstBlock "S-R Latch1" DstPort 2 } } } Line { SrcBlock "Count-To Calc" SrcPort 2 Points [35, 0; 0, 170] Branch { DstBlock "Relational4" DstPort 1 } Branch { Points [0, 45] DstBlock "Relational2" DstPort 1 } } Line { SrcBlock "Relational4" SrcPort 1 DstBlock "Logical2" DstPort 2 } Line { SrcBlock "Logical2" SrcPort 1 Points [80, 0] Branch { DstBlock "FFT tvalid" DstPort 1 } Branch { Points [0, -370] DstBlock "Gateway Out5" DstPort 1 } } Line { Name "FFT tvalid" Labels [0, 0] SrcBlock "Gateway Out5" SrcPort 1 DstBlock "Ctrl" DstPort 6 } Line { Name "Rd Addr" Labels [0, 0] SrcBlock "Gateway Out6" SrcPort 1 DstBlock "Ctrl" DstPort 7 } Line { Name "LTS Sync" Labels [0, 0] SrcBlock "Gateway Out1" SrcPort 1 DstBlock "Ctrl" DstPort 1 } Line { Name "Rx Samp Ind" Labels [0, 0] SrcBlock "Gateway Out2" SrcPort 1 DstBlock "Ctrl" DstPort 2 } Line { Name "Init Samp Addr" Labels [0, 0] SrcBlock "Gateway Out3" SrcPort 1 DstBlock "Ctrl" DstPort 3 } Line { Name "Rd Counter" Labels [0, 0] SrcBlock "Gateway Out4" SrcPort 1 DstBlock "Ctrl" DstPort 4 } Line { Name "Samp Counter" Labels [0, 0] SrcBlock "Gateway Out7" SrcPort 1 DstBlock "Ctrl" DstPort 5 } Line { SrcBlock "Logical1" SrcPort 1 Points [15, 0] Branch { DstBlock "Rd Counter" DstPort 3 } Branch { Points [0, 270] DstBlock "Reading" DstPort 1 } } Line { SrcBlock "Delay" SrcPort 1 Points [95, 0] Branch { DstBlock "Rd Counter" DstPort 1 } Branch { Points [0, 30] DstBlock "Logical1" DstPort 1 } } Line { SrcBlock "Inverter" SrcPort 1 Points [10, 0; 0, -75] DstBlock "Logical4" DstPort 3 } Line { SrcBlock "LTS Sync" SrcPort 1 Points [30, 0] Branch { DstBlock "First Samp\nCalc" DstPort 2 } Branch { Points [0, 145] DstBlock "Delay" DstPort 1 } Branch { Points [0, -180] DstBlock "Gateway Out1" DstPort 1 } } Line { SrcBlock "Relational2" SrcPort 1 DstBlock "FFT tlast" DstPort 1 } Line { SrcBlock "Logical" SrcPort 1 DstBlock "Logical3" DstPort 1 } Line { SrcBlock "Logical3" SrcPort 1 DstBlock "S-R Latch1" DstPort 1 } Line { SrcBlock "FFT LTS Load" SrcPort 1 Points [135, 0] DstBlock "Logical3" DstPort 2 } } } Block { BlockType SubSystem Name "FSM" SID "296" Ports [3, 3] Position [490, 632, 610, 668] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "FSM" Location [311, 989, 1176, 1189] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "FFT Load Done" SID "297" Position [155, 238, 185, 252] IconDisplay "Port number" } Block { BlockType Inport Name "LTS" SID "298" Position [155, 213, 185, 227] NamePlacement "alternate" Port "2" IconDisplay "Port number" } Block { BlockType Inport Name "Pkt Done" SID "299" Position [155, 268, 185, 282] Port "3" IconDisplay "Port number" } Block { BlockType Reference Name "Convert" SID "300" Ports [1, 1] Position [275, 236, 300, 254] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do not." gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "1" bin_pt "0" float_type "Single" exp_bits "8" fraction_bits "24" quantization "Truncate" overflow "Wrap" en off latency "0" dbl_ovrd off pipeline off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "convert" sg_icon_stat "25,18,1,1,white,blue,0,edca21da,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 18 18 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 25 25 0 0 ],[0 0 18 18 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[11.22 11.22 13" ".22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[9.22 9.22 11.22 11.22 9.22 ]," "[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);\npatch([9.55 16" ".44 14.44 12.44 10.44 7.55 9.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMEN" "T: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('output',1,'cast');\n" "fprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Convert1" SID "301" Ports [1, 1] Position [275, 211, 300, 229] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do not." gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "1" bin_pt "0" float_type "Single" exp_bits "8" fraction_bits "24" quantization "Truncate" overflow "Wrap" en off latency "0" dbl_ovrd off pipeline off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "convert" sg_icon_stat "25,18,1,1,white,blue,0,edca21da,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 18 18 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 25 25 0 0 ],[0 0 18 18 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[11.22 11.22 13" ".22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[9.22 9.22 11.22 11.22 9.22 ]," "[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);\npatch([9.55 16" ".44 14.44 12.44 10.44 7.55 9.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMEN" "T: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('output',1,'cast');\n" "fprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Convert2" SID "302" Ports [1, 1] Position [275, 266, 300, 284] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do not." gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "1" bin_pt "0" float_type "Single" exp_bits "8" fraction_bits "24" quantization "Truncate" overflow "Wrap" en off latency "0" dbl_ovrd off pipeline off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "convert" sg_icon_stat "25,18,1,1,white,blue,0,edca21da,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 18 18 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 25 25 0 0 ],[0 0 18 18 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[11.22 11.22 13" ".22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[9.22 9.22 11.22 11.22 9.22 ]," "[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);\npatch([9.55 16" ".44 14.44 12.44 10.44 7.55 9.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMEN" "T: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('output',1,'cast');\n" "fprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Convert3" SID "303" Ports [1, 1] Position [675, 211, 700, 229] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do not." gui_display_data_type "Boolean" arith_type "Boolean" n_bits "1" bin_pt "0" float_type "Single" exp_bits "8" fraction_bits "24" quantization "Truncate" overflow "Wrap" en off latency "0" dbl_ovrd off pipeline off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "convert" sg_icon_stat "25,18,1,1,white,blue,0,edca21da,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 18 18 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 25 25 0 0 ],[0 0 18 18 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[11.22 11.22 13" ".22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[9.22 9.22 11.22 11.22 9.22 ]," "[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);\npatch([9.55 16" ".44 14.44 12.44 10.44 7.55 9.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMEN" "T: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('output',1,'cast');\n" "fprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Convert4" SID "304" Ports [1, 1] Position [675, 236, 700, 254] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do not." gui_display_data_type "Boolean" arith_type "Boolean" n_bits "1" bin_pt "0" float_type "Single" exp_bits "8" fraction_bits "24" quantization "Truncate" overflow "Wrap" en off latency "0" dbl_ovrd off pipeline off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "convert" sg_icon_stat "25,18,1,1,white,blue,0,edca21da,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 18 18 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 25 25 0 0 ],[0 0 18 18 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[11.22 11.22 13" ".22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[9.22 9.22 11.22 11.22 9.22 ]," "[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);\npatch([9.55 16" ".44 14.44 12.44 10.44 7.55 9.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMEN" "T: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('output',1,'cast');\n" "fprintf('','COMMENT: end icon text');" } Block { BlockType Scope Name "FFT Load FSM" SID "305" Ports [9] Position [1000, 381, 1035, 529] ZOrder -3 Floating off Location [797, 508, 2334, 1506] Open off NumInputPorts "9" ZoomMode "xonly" List { ListType AxesTitles axes1 "%" axes2 "%" axes3 "%" axes4 "%" axes5 "%" axes6 "%" axes7 "%" axes8 "%" axes9 "%" } List { ListType ScopeGraphics FigureColor "[0.5 0.5 0.5]" AxesColor "[0 0 0]" AxesTickColor "[1 1 1]" LineColors "[1 1 0;1 0 1;0 1 1;1 0 0;0 1 0;0 0 1]" LineStyles "-|-|-|-|-|-" LineWidths "[0.5 0.5 0.5 0.5 0.5 0.5]" MarkerStyles "none|none|none|none|none|none" } TimeRange "10000" YMin "-0.25~-0.25~0~0~0~-0.1~-0.1~-5~-5" YMax "0.2~0.2~300~300~4000~1.1~1.1~5~5" SaveName "ScopeData48" DataFormat "StructureWithTime" LimitDataPoints off SampleTime "0" } Block { BlockType Reference Name "Gateway Out1" SID "306" Ports [1, 1] Position [875, 419, 910, 431] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type Sim" "ulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top level o" "utput ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0.88 0.8" "8 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[7.11 7.1" "1 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7.11 7.11 6.11 " "],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]);\npatch(" "[15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.964 ]);\nfpri" "ntf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input'," "1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf('','COMMENT: end i" "con text');" Port { PortNumber 1 Name "Pkt Done" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out2" SID "307" Ports [1, 1] Position [875, 449, 910, 461] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type Sim" "ulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top level o" "utput ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0.88 0.8" "8 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[7.11 7.1" "1 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7.11 7.11 6.11 " "],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]);\npatch(" "[15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.964 ]);\nfpri" "ntf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input'," "1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf('','COMMENT: end i" "con text');" Port { PortNumber 1 Name "FFT Data Load" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out3" SID "308" Ports [1, 1] Position [875, 464, 910, 476] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type Sim" "ulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top level o" "utput ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0.88 0.8" "8 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[7.11 7.1" "1 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7.11 7.11 6.11 " "],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]);\npatch(" "[15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.964 ]);\nfpri" "ntf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input'," "1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf('','COMMENT: end i" "con text');" Port { PortNumber 1 Name "FFT LTS Load" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out4" SID "309" Ports [1, 1] Position [875, 479, 910, 491] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type Sim" "ulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top level o" "utput ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0.88 0.8" "8 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[7.11 7.1" "1 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7.11 7.11 6.11 " "],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]);\npatch(" "[15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.964 ]);\nfpri" "ntf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input'," "1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf('','COMMENT: end i" "con text');" Port { PortNumber 1 Name "FFT skip sel" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out5" SID "310" Ports [1, 1] Position [875, 404, 910, 416] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type Sim" "ulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top level o" "utput ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0.88 0.8" "8 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[7.11 7.1" "1 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7.11 7.11 6.11 " "],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]);\npatch(" "[15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.964 ]);\nfpri" "ntf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input'," "1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf('','COMMENT: end i" "con text');" Port { PortNumber 1 Name "FFT Load Done" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out6" SID "311" Ports [1, 1] Position [875, 389, 910, 401] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type Sim" "ulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top level o" "utput ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0.88 0.8" "8 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[7.11 7.1" "1 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7.11 7.11 6.11 " "],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]);\npatch(" "[15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.964 ]);\nfpri" "ntf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input'," "1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf('','COMMENT: end i" "con text');" Port { PortNumber 1 Name "LTS Sync" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "MCode" SID "312" Ports [3, 3] Position [415, 205, 635, 285] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/MCode" SourceType "Xilinx MCode Block Block" infoedit "Pass input values to a MATLAB function for evaluation in Xilinx fixed-point type. The input ports of " "the block are input arguments of the function. The output ports of the block are output arguments of the function." mfname "rx_fft_ctrl_fsm" explicit_period on period "1" inputsTable "{'boundInpExpr'=>['','',''],'inputs'=>['lts_sync','fft_load_done','pkt_done']}" outputsTable "{'outputs'=>['fft_load','samp_skip_mode'],'suppressOut'=>['off','off']}" dbl_ovrd off enable_stdout off enable_debug off xl_use_area off xl_area "[0,0,0,0,0,0,0]" suppress_output "on" defparams "{}" hide_port_list "{}" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "mcode" sg_icon_stat "220,80,3,3,white,blue,0,c9d27118,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 220 220 0 0 ],[0 0 80 80 0 ],[0.77 0.82 0" ".91 ]);\nplot([0 220 220 0 0 ],[0 0 80 80 0 ]);\npatch([85.525 101.42 112.42 123.42 134.42 112.42 96.525 85.525 ]," "[52.21 52.21 63.21 52.21 63.21 63.21 63.21 52.21 ],[1 1 1 ]);\npatch([96.525 112.42 101.42 85.525 96.525 ],[41.21 " "41.21 52.21 52.21 41.21 ],[0.931 0.946 0.973 ]);\npatch([85.525 101.42 112.42 96.525 85.525 ],[30.21 30.21 41.21 4" "1.21 30.21 ],[1 1 1 ]);\npatch([96.525 134.42 123.42 112.42 101.42 85.525 96.525 ],[19.21 19.21 30.21 19.21 30.21 " "30.21 19.21 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon t" "ext');\ncolor('black');port_label('input',1,'lts_sync');\ncolor('black');port_label('input',2,'fft_load_done');\nc" "olor('black');port_label('input',3,'pkt_done');\ncolor('black');port_label('output',1,'fft_load');\ncolor('black')" ";port_label('output',2,'fft_lts_load');\ncolor('black');port_label('output',3,'samp_skip_mode');\ncolor('black');d" "isp('\\bf{rx\\_fft\\_ctrl\\_fsm}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Outport Name "FFT skip sel" SID "313" Position [775, 263, 805, 277] IconDisplay "Port number" } Block { BlockType Outport Name "FFT LTS load" SID "314" Position [900, 238, 930, 252] Port "2" IconDisplay "Port number" } Block { BlockType Outport Name "FFT Data load" SID "315" Position [765, 213, 795, 227] Port "3" IconDisplay "Port number" } Line { SrcBlock "Pkt Done" SrcPort 1 DstBlock "Convert2" DstPort 1 } Line { SrcBlock "Convert1" SrcPort 1 Points [85, 0] Branch { DstBlock "MCode" DstPort 1 } Branch { Points [0, 175] DstBlock "Gateway Out6" DstPort 1 } } Line { SrcBlock "MCode" SrcPort 1 DstBlock "Convert3" DstPort 1 } Line { SrcBlock "MCode" SrcPort 2 DstBlock "Convert4" DstPort 1 } Line { SrcBlock "Convert" SrcPort 1 Points [80, 0] Branch { DstBlock "MCode" DstPort 2 } Branch { Points [0, 165] DstBlock "Gateway Out5" DstPort 1 } } Line { SrcBlock "LTS" SrcPort 1 DstBlock "Convert1" DstPort 1 } Line { SrcBlock "FFT Load Done" SrcPort 1 DstBlock "Convert" DstPort 1 } Line { SrcBlock "Convert2" SrcPort 1 Points [0, -5; 75, 0] Branch { DstBlock "MCode" DstPort 3 } Branch { Points [0, 155] DstBlock "Gateway Out1" DstPort 1 } } Line { SrcBlock "MCode" SrcPort 3 Points [85, 0] Branch { DstBlock "FFT skip sel" DstPort 1 } Branch { Points [0, 215] DstBlock "Gateway Out4" DstPort 1 } } Line { SrcBlock "Convert3" SrcPort 1 Points [30, 0] Branch { DstBlock "FFT Data load" DstPort 1 } Branch { Points [0, 235] DstBlock "Gateway Out2" DstPort 1 } } Line { SrcBlock "Convert4" SrcPort 1 Points [25, 0] Branch { DstBlock "FFT LTS load" DstPort 1 } Branch { Points [0, 225] DstBlock "Gateway Out3" DstPort 1 } } Line { Name "FFT Load Done" Labels [0, 0] SrcBlock "Gateway Out5" SrcPort 1 DstBlock "FFT Load FSM" DstPort 2 } Line { Name "LTS Sync" Labels [0, 0] SrcBlock "Gateway Out6" SrcPort 1 DstBlock "FFT Load FSM" DstPort 1 } Line { Name "Pkt Done" Labels [0, 0] SrcBlock "Gateway Out1" SrcPort 1 DstBlock "FFT Load FSM" DstPort 3 } Line { Name "FFT Data Load" Labels [0, 0] SrcBlock "Gateway Out2" SrcPort 1 DstBlock "FFT Load FSM" DstPort 5 } Line { Name "FFT LTS Load" Labels [0, 0] SrcBlock "Gateway Out3" SrcPort 1 DstBlock "FFT Load FSM" DstPort 6 } Line { Points [955, 440] DstBlock "FFT Load FSM" DstPort 4 } Line { Name "FFT skip sel" Labels [0, 0] SrcBlock "Gateway Out4" SrcPort 1 DstBlock "FFT Load FSM" DstPort 7 } } } Block { BlockType Reference Name "Gateway Out1" SID "316" Ports [1, 1] Position [1040, 219, 1075, 231] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of t" "ype Simulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become t" "op level output ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0" ".88 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ]" ",[7.11 7.11 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7." "11 7.11 6.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1" " 1 1 ]);\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0." "964 0.964 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black" "');port_label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nf" "printf('','COMMENT: end icon text');" Port { PortNumber 1 Name "Rd Addr" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out2" SID "317" Ports [1, 1] Position [1040, 234, 1075, 246] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of t" "ype Simulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become t" "op level output ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0" ".88 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ]" ",[7.11 7.11 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7." "11 7.11 6.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1" " 1 1 ]);\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0." "964 0.964 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black" "');port_label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nf" "printf('','COMMENT: end icon text');" Port { PortNumber 1 Name "Wr Addr" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out3" SID "318" Ports [1, 1] Position [1040, 249, 1075, 261] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of t" "ype Simulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become t" "op level output ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0" ".88 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ]" ",[7.11 7.11 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7." "11 7.11 6.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1" " 1 1 ]);\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0." "964 0.964 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black" "');port_label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nf" "printf('','COMMENT: end icon text');" Port { PortNumber 1 Name "Pkt Det" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out4" SID "319" Ports [1, 1] Position [1040, 264, 1075, 276] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of t" "ype Simulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become t" "op level output ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0" ".88 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ]" ",[7.11 7.11 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7." "11 7.11 6.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1" " 1 1 ]);\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0." "964 0.964 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black" "');port_label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nf" "printf('','COMMENT: end icon text');" Port { PortNumber 1 Name "Pkt Done" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out5" SID "320" Ports [1, 1] Position [1040, 204, 1075, 216] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of t" "ype Simulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become t" "op level output ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0" ".88 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ]" ",[7.11 7.11 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7." "11 7.11 6.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1" " 1 1 ]);\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0." "964 0.964 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black" "');port_label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nf" "printf('','COMMENT: end icon text');" Port { PortNumber 1 Name "FFT In I" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out6" SID "321" Ports [1, 1] Position [1040, 189, 1075, 201] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of t" "ype Simulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become t" "op level output ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0" ".88 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ]" ",[7.11 7.11 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7." "11 7.11 6.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1" " 1 1 ]);\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0." "964 0.964 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black" "');port_label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nf" "printf('','COMMENT: end icon text');" Port { PortNumber 1 Name "ADC I" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out7" SID "322" Ports [1, 1] Position [1040, 279, 1075, 291] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of t" "ype Simulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become t" "op level output ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0" ".88 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ]" ",[7.11 7.11 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7." "11 7.11 6.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1" " 1 1 ]);\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0." "964 0.964 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black" "');port_label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nf" "printf('','COMMENT: end icon text');" Port { PortNumber 1 Name "FFT Load Done" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out8" SID "323" Ports [1, 1] Position [1040, 294, 1075, 306] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of t" "ype Simulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become t" "op level output ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0" ".88 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ]" ",[7.11 7.11 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7." "11 7.11 6.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1" " 1 1 ]);\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0." "964 0.964 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black" "');port_label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nf" "printf('','COMMENT: end icon text');" Port { PortNumber 1 Name "FFT In tvalid" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out9" SID "11306" Ports [1, 1] Position [1040, 309, 1075, 321] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of t" "ype Simulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become t" "op level output ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0" ".88 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ]" ",[7.11 7.11 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7." "11 7.11 6.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1" " 1 1 ]);\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0." "964 0.964 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black" "');port_label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nf" "printf('','COMMENT: end icon text');" Port { PortNumber 1 Name "DEBUG Payload" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Goto Name "Goto" SID "324" Position [1065, 786, 1290, 804] ZOrder -10 ShowName off GotoTag "OFDM_RX_RUNNING_DSSS_BLOCK" TagVisibility "global" } Block { BlockType Reference Name "Logical2" SID "325" Ports [2, 1] Position [285, 620, 320, 675] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "AND" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" sg_icon_stat "35,55,2,1,white,blue,0,83a4b621,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 55 55 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 55 55 0 ]);\npatch([5.875 13.1 18.1 23.1 28.1 18.1 10.875 5.875 ],[32.55" " 32.55 37.55 32.55 37.55 37.55 37.55 32.55 ],[1 1 1 ]);\npatch([10.875 18.1 13.1 5.875 10.875 ],[27.55 27.55 32" ".55 32.55 27.55 ],[0.931 0.946 0.973 ]);\npatch([5.875 13.1 18.1 10.875 5.875 ],[22.55 22.55 27.55 27.55 22.55 " "],[1 1 1 ]);\npatch([10.875 28.1 23.1 18.1 13.1 5.875 10.875 ],[17.55 17.55 22.55 17.55 22.55 22.55 17.55 ],[0." "931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\n" "color('black');disp('and');\nfprintf('','COMMENT: end icon text');" } Block { BlockType SubSystem Name "Posedge" SID "326" Ports [1, 1] Position [360, 638, 415, 662] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "Posedge" Location [384, 656, 940, 879] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "D" SID "327" Position [200, 253, 230, 267] IconDisplay "Port number" } Block { BlockType Reference Name "Delay" SID "328" Ports [1, 1] Position [425, 153, 460, 177] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flop. If r" "egister retiming is enabled, the delay line is a chain of flip-flops." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en off latency "1" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[1 1 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,24,1,1,white,blue,0,07b98262,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 24 24 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 35 35 0 0 ],[0 0 24 24 0 ]);\npatch([10.325 14.66 17.66 20.66 23.66 17.66 13.325 10.325 ],[15.33 15" ".33 18.33 15.33 18.33 18.33 18.33 15.33 ],[1 1 1 ]);\npatch([13.325 17.66 14.66 10.325 13.325 ],[12.33 12.33 15.33" " 15.33 12.33 ],[0.931 0.946 0.973 ]);\npatch([10.325 14.66 17.66 13.325 10.325 ],[9.33 9.33 12.33 12.33 9.33 ],[1 " "1 1 ]);\npatch([13.325 23.66 20.66 17.66 14.66 10.325 13.325 ],[6.33 6.33 9.33 6.33 9.33 9.33 6.33 ],[0.931 0.946 " "0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');" "disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Inverter" SID "329" Ports [1, 1] Position [490, 156, 515, 174] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Inverter" SourceType "Xilinx Inverter Block" infoedit "Bitwise logical negation (one's complement) operator." en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "inv" block_version "VER_STRING_GOES_HERE" sg_icon_stat "25,18,1,1,white,blue,0,267846e5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 18 18 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 25 25 0 0 ],[0 0 18 18 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[11.22 11.22 13" ".22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[9.22 9.22 11.22 11.22 9.22 ]," "[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);\npatch([9.55 16" ".44 14.44 12.44 10.44 7.55 9.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMEN" "T: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');disp('not');\nfprintf('','COM" "MENT: end icon text');" } Block { BlockType Reference Name "Logical1" SID "330" Ports [2, 1] Position [540, 151, 585, 204] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "AND" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "8" bin_pt "2" align_bp on dbl_ovrd off xl_use_area off xl_area "[1 0 0 1 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" block_version "VER_STRING_GOES_HERE" sg_icon_stat "45,53,2,1,white,blue,0,83a4b621,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 53 53 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 45 45 0 0 ],[0 0 53 53 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[32.66 32.66 3" "8.66 32.66 38.66 38.66 38.66 32.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[26.66 26.66 32.66 32.66 26" ".66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[20.66 20.66 26.66 26.66 20.66 ],[1 1 1 ]);\npa" "tch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[14.66 14.66 20.66 14.66 20.66 20.66 14.66 ],[0.931 0.946 0.973 ])" ";\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\ncolor('black');disp('" "and');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Outport Name "Q" SID "331" Position [610, 173, 640, 187] IconDisplay "Port number" } Line { SrcBlock "D" SrcPort 1 Points [150, 0; 0, -70] Branch { DstBlock "Logical1" DstPort 2 } Branch { Points [0, -25] DstBlock "Delay" DstPort 1 } } Line { SrcBlock "Logical1" SrcPort 1 DstBlock "Q" DstPort 1 } Line { SrcBlock "Inverter" SrcPort 1 DstBlock "Logical1" DstPort 1 } Line { SrcBlock "Delay" SrcPort 1 DstBlock "Inverter" DstPort 1 } Annotation { Name "Rising Edge Detection" Position [500, 112] } } } Block { BlockType SubSystem Name "Posedge3" SID "332" Ports [1, 1] Position [725, 648, 780, 672] NamePlacement "alternate" MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "Posedge3" Location [88, 301, 2330, 1301] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "D" SID "333" Position [200, 253, 230, 267] IconDisplay "Port number" } Block { BlockType Reference Name "Delay" SID "334" Ports [1, 1] Position [425, 153, 460, 177] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flop. If r" "egister retiming is enabled, the delay line is a chain of flip-flops." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en off latency "1" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[1 1 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,24,1,1,white,blue,0,07b98262,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 24 24 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 35 35 0 0 ],[0 0 24 24 0 ]);\npatch([10.325 14.66 17.66 20.66 23.66 17.66 13.325 10.325 ],[15.33 15" ".33 18.33 15.33 18.33 18.33 18.33 15.33 ],[1 1 1 ]);\npatch([13.325 17.66 14.66 10.325 13.325 ],[12.33 12.33 15.33" " 15.33 12.33 ],[0.931 0.946 0.973 ]);\npatch([10.325 14.66 17.66 13.325 10.325 ],[9.33 9.33 12.33 12.33 9.33 ],[1 " "1 1 ]);\npatch([13.325 23.66 20.66 17.66 14.66 10.325 13.325 ],[6.33 6.33 9.33 6.33 9.33 9.33 6.33 ],[0.931 0.946 " "0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');" "disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Inverter" SID "335" Ports [1, 1] Position [490, 156, 515, 174] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Inverter" SourceType "Xilinx Inverter Block" infoedit "Bitwise logical negation (one's complement) operator." en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "inv" block_version "VER_STRING_GOES_HERE" sg_icon_stat "25,18,1,1,white,blue,0,267846e5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 18 18 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 25 25 0 0 ],[0 0 18 18 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[11.22 11.22 13" ".22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[9.22 9.22 11.22 11.22 9.22 ]," "[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);\npatch([9.55 16" ".44 14.44 12.44 10.44 7.55 9.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMEN" "T: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');disp('not');\nfprintf('','COM" "MENT: end icon text');" } Block { BlockType Reference Name "Logical1" SID "336" Ports [2, 1] Position [540, 151, 585, 204] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "AND" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "8" bin_pt "2" align_bp on dbl_ovrd off xl_use_area off xl_area "[1 0 0 1 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" block_version "VER_STRING_GOES_HERE" sg_icon_stat "45,53,2,1,white,blue,0,83a4b621,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 53 53 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 45 45 0 0 ],[0 0 53 53 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[32.66 32.66 3" "8.66 32.66 38.66 38.66 38.66 32.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[26.66 26.66 32.66 32.66 26" ".66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[20.66 20.66 26.66 26.66 20.66 ],[1 1 1 ]);\npa" "tch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[14.66 14.66 20.66 14.66 20.66 20.66 14.66 ],[0.931 0.946 0.973 ])" ";\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\ncolor('black');disp('" "and');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Outport Name "Q" SID "337" Position [610, 173, 640, 187] IconDisplay "Port number" } Line { SrcBlock "D" SrcPort 1 Points [150, 0; 0, -70] Branch { DstBlock "Logical1" DstPort 2 } Branch { Points [0, -25] DstBlock "Delay" DstPort 1 } } Line { SrcBlock "Logical1" SrcPort 1 DstBlock "Q" DstPort 1 } Line { SrcBlock "Inverter" SrcPort 1 DstBlock "Logical1" DstPort 1 } Line { SrcBlock "Delay" SrcPort 1 DstBlock "Inverter" DstPort 1 } Annotation { Name "Rising Edge Detection" Position [500, 112] } } } Block { BlockType Reference Name "Register" SID "338" Ports [1, 1] Position [930, 657, 965, 683] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "35,26,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 26 26 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 26 26 0 ]);\npatch([10.325 14.66 17.66 20.66 23.66 17.66 13.325 10.325 ]" ",[16.33 16.33 19.33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([13.325 17.66 14.66 10.325 13.325 ],[13.3" "3 13.33 16.33 16.33 13.33 ],[0.931 0.946 0.973 ]);\npatch([10.325 14.66 17.66 13.325 10.325 ],[10.33 10.33 13.3" "3 13.33 10.33 ],[1 1 1 ]);\npatch([13.325 23.66 20.66 17.66 14.66 10.325 13.325 ],[7.33 7.33 10.33 7.33 10.33 1" "0.33 7.33 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon " "text');\ncolor('black');port_label('input',1,'d');\ncolor('black');port_label('output',1,'q');\ncolor('black');" "disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register1" SID "339" Ports [1, 1] Position [1000, 657, 1035, 683] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "35,26,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 26 26 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 26 26 0 ]);\npatch([10.325 14.66 17.66 20.66 23.66 17.66 13.325 10.325 ]" ",[16.33 16.33 19.33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([13.325 17.66 14.66 10.325 13.325 ],[13.3" "3 13.33 16.33 16.33 13.33 ],[0.931 0.946 0.973 ]);\npatch([10.325 14.66 17.66 13.325 10.325 ],[10.33 10.33 13.3" "3 13.33 10.33 ],[1 1 1 ]);\npatch([13.325 23.66 20.66 17.66 14.66 10.325 13.325 ],[7.33 7.33 10.33 7.33 10.33 1" "0.33 7.33 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon " "text');\ncolor('black');port_label('input',1,'d');\ncolor('black');port_label('output',1,'q');\ncolor('black');" "disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType SubSystem Name "S-R Latch" SID "340" Ports [2, 1] Position [845, 653, 890, 682] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "S-R Latch" Location [-1278, 70, -2, 1004] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "S" SID "341" Position [140, 103, 170, 117] IconDisplay "Port number" } Block { BlockType Inport Name "R" SID "342" Position [140, 88, 170, 102] NamePlacement "alternate" Port "2" IconDisplay "Port number" } Block { BlockType Reference Name "Constant1" SID "343" Ports [0, 1] Position [195, 71, 210, 89] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "1" gui_display_data_type "Fixed-point" arith_type "Boolean" n_bits "1" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" block_version "VER_STRING_GOES_HERE" sg_icon_stat "15,18,0,1,white,blue,0,1c72b5be,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 15 15 0 0 ],[0 0 18 18 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 15 15 0 0 ],[0 0 18 18 0 ]);\npatch([2.55 5.44 7.44 9.44 11.44 7.44 4.55 2.55 ],[11.22 11.22 13.22 " "11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([4.55 7.44 5.44 2.55 4.55 ],[9.22 9.22 11.22 11.22 9.22 ],[0.931" " 0.946 0.973 ]);\npatch([2.55 5.44 7.44 4.55 2.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);\npatch([4.55 11.44 9.44" " 7.44 5.44 2.55 4.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon" " graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'1');\nfprintf('','COM" "MENT: end icon text');" } Block { BlockType Reference Name "Register2" SID "344" Ports [3, 1] Position [255, 71, 300, 119] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst on en on dbl_ovrd off xl_use_area off xl_area "[1 1 0 0 0 0 0]" has_advanced_control "0" sggui_pos "20,20,348,193" block_type "register" block_version "VER_STRING_GOES_HERE" sg_icon_stat "45,48,3,1,white,blue,0,30546de1,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 48 48 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 45 45 0 0 ],[0 0 48 48 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[30.66 30.66 3" "6.66 30.66 36.66 36.66 36.66 30.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[24.66 24.66 30.66 30.66 24" ".66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[18.66 18.66 24.66 24.66 18.66 ],[1 1 1 ]);\npa" "tch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[12.66 12.66 18.66 12.66 18.66 18.66 12.66 ],[0.931 0.946 0.973 ])" ";\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('" "input',1,'d');\ncolor('black');port_label('input',2,'rst');\ncolor('black');port_label('input',3,'en');\ncolor('bl" "ack');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon te" "xt');" } Block { BlockType Outport Name "Q" SID "345" Position [325, 88, 355, 102] IconDisplay "Port number" } Line { SrcBlock "Constant1" SrcPort 1 DstBlock "Register2" DstPort 1 } Line { SrcBlock "R" SrcPort 1 DstBlock "Register2" DstPort 2 } Line { SrcBlock "Register2" SrcPort 1 DstBlock "Q" DstPort 1 } Line { SrcBlock "S" SrcPort 1 DstBlock "Register2" DstPort 3 } } } Block { BlockType Scope Name "Scope" SID "346" Ports [9] Position [1170, 181, 1205, 329] ZOrder -3 Floating off Location [5, 40, 1925, 1194] Open off NumInputPorts "9" ZoomMode "xonly" List { ListType AxesTitles axes1 "%" axes2 "%" axes3 "%" axes4 "%" axes5 "%" axes6 "%" axes7 "%" axes8 "%" axes9 "%" } List { ListType ScopeGraphics FigureColor "[0.501960784313725 0.501960784313725 0.501960784313725]" AxesColor "[0 0 0]" AxesTickColor "[1 1 1]" LineColors "[1 1 0;1 0 1;0 1 1;1 0 0;0 1 0;0 0 1]" LineStyles "-|-|-|-|-|-" LineWidths "[2 0.5 0.5 0.5 0.5 0.5]" MarkerStyles "none|none|none|none|none|none" } TimeRange "10000" YMin "-0.4~-0.4~0~0~0~-0.1~-0.1~-5~-5" YMax "0.5~0.4~275~275~4000~1.1~1.1~5~5" SaveName "ScopeData25" DataFormat "StructureWithTime" LimitDataPoints off SampleTime "0" } Block { BlockType SubSystem Name "Slice" SID "347" Ports [1, 2] Position [865, 395, 915, 430] NamePlacement "alternate" MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "Slice" Location [1155, 565, 1558, 696] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "IQ" SID "348" Position [190, 123, 220, 137] IconDisplay "Port number" } Block { BlockType Reference Name "Reinterpret2" SID "349" Ports [1, 1] Position [350, 119, 390, 141] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Reinterpret" SourceType "Xilinx Type Reinterpreter Block" infoedit "Changes signal type without altering the binary representation. You can change the signal between s" "igned and unsigned, and relocate the binary point.

Hardware notes: In hardware this block costs nothing.
Example: Suppose the input is 6 bits wide, signed, with 2 fractional bits, and the output is forced to unsig" "ned with 0 fractional bits. Then an input of -2.0 (1110.00 in binary 2's complement) becomes an output of 56 (111" "000 in binary)." force_arith_type on arith_type "Signed (2's comp)" force_bin_pt on bin_pt "15" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "reinterpret" sg_icon_stat "40,22,1,1,white,blue,0,6b04d0b0,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 22 22 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 40 40 0 0 ],[0 0 22 22 0 ]);\npatch([13.325 17.66 20.66 23.66 26.66 20.66 16.325 13.325 ],[14.33 14" ".33 17.33 14.33 17.33 17.33 17.33 14.33 ],[1 1 1 ]);\npatch([16.325 20.66 17.66 13.325 16.325 ],[11.33 11.33 14.33" " 14.33 11.33 ],[0.931 0.946 0.973 ]);\npatch([13.325 17.66 20.66 16.325 13.325 ],[8.33 8.33 11.33 11.33 8.33 ],[1 " "1 1 ]);\npatch([16.325 26.66 23.66 20.66 17.66 13.325 16.325 ],[5.33 5.33 8.33 5.33 8.33 8.33 5.33 ],[0.931 0.946 " "0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');" "disp('reinterpret');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Reinterpret3" SID "350" Ports [1, 1] Position [350, 144, 390, 166] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Reinterpret" SourceType "Xilinx Type Reinterpreter Block" infoedit "Changes signal type without altering the binary representation. You can change the signal between s" "igned and unsigned, and relocate the binary point.

Hardware notes: In hardware this block costs nothing.
Example: Suppose the input is 6 bits wide, signed, with 2 fractional bits, and the output is forced to unsig" "ned with 0 fractional bits. Then an input of -2.0 (1110.00 in binary 2's complement) becomes an output of 56 (111" "000 in binary)." force_arith_type on arith_type "Signed (2's comp)" force_bin_pt on bin_pt "15" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "reinterpret" sg_icon_stat "40,22,1,1,white,blue,0,6b04d0b0,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 22 22 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 40 40 0 0 ],[0 0 22 22 0 ]);\npatch([13.325 17.66 20.66 23.66 26.66 20.66 16.325 13.325 ],[14.33 14" ".33 17.33 14.33 17.33 17.33 17.33 14.33 ],[1 1 1 ]);\npatch([16.325 20.66 17.66 13.325 16.325 ],[11.33 11.33 14.33" " 14.33 11.33 ],[0.931 0.946 0.973 ]);\npatch([13.325 17.66 20.66 16.325 13.325 ],[8.33 8.33 11.33 11.33 8.33 ],[1 " "1 1 ]);\npatch([16.325 26.66 23.66 20.66 17.66 13.325 16.325 ],[5.33 5.33 8.33 5.33 8.33 8.33 5.33 ],[0.931 0.946 " "0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');" "disp('reinterpret');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Slice" SID "351" Ports [1, 1] Position [265, 119, 300, 141] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The output type" " is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.

Hardw" "are notes: In hardware this block costs nothing." nbits "16" boolean_output off mode "Upper Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "0" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "slice" sg_icon_stat "35,22,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 22 22 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 35 35 0 0 ],[0 0 22 22 0 ]);\npatch([10.325 14.66 17.66 20.66 23.66 17.66 13.325 10.325 ],[14.33 14" ".33 17.33 14.33 17.33 17.33 17.33 14.33 ],[1 1 1 ]);\npatch([13.325 17.66 14.66 10.325 13.325 ],[11.33 11.33 14.33" " 14.33 11.33 ],[0.931 0.946 0.973 ]);\npatch([10.325 14.66 17.66 13.325 10.325 ],[8.33 8.33 11.33 11.33 8.33 ],[1 " "1 1 ]);\npatch([13.325 23.66 20.66 17.66 14.66 10.325 13.325 ],[5.33 5.33 8.33 5.33 8.33 8.33 5.33 ],[0.931 0.946 " "0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');po" "rt_label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Slice1" SID "352" Ports [1, 1] Position [265, 144, 300, 166] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The output type" " is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.

Hardw" "are notes: In hardware this block costs nothing." nbits "16" boolean_output off mode "Lower Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "0" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "slice" sg_icon_stat "35,22,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 22 22 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 35 35 0 0 ],[0 0 22 22 0 ]);\npatch([10.325 14.66 17.66 20.66 23.66 17.66 13.325 10.325 ],[14.33 14" ".33 17.33 14.33 17.33 17.33 17.33 14.33 ],[1 1 1 ]);\npatch([13.325 17.66 14.66 10.325 13.325 ],[11.33 11.33 14.33" " 14.33 11.33 ],[0.931 0.946 0.973 ]);\npatch([10.325 14.66 17.66 13.325 10.325 ],[8.33 8.33 11.33 11.33 8.33 ],[1 " "1 1 ]);\npatch([13.325 23.66 20.66 17.66 14.66 10.325 13.325 ],[5.33 5.33 8.33 5.33 8.33 8.33 5.33 ],[0.931 0.946 " "0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');po" "rt_label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Outport Name "I" SID "353" Position [450, 123, 480, 137] NamePlacement "alternate" IconDisplay "Port number" } Block { BlockType Outport Name "Q" SID "354" Position [450, 148, 480, 162] Port "2" IconDisplay "Port number" } Line { SrcBlock "Slice" SrcPort 1 DstBlock "Reinterpret2" DstPort 1 } Line { SrcBlock "Slice1" SrcPort 1 DstBlock "Reinterpret3" DstPort 1 } Line { SrcBlock "IQ" SrcPort 1 Points [15, 0] Branch { Points [0, 25] DstBlock "Slice1" DstPort 1 } Branch { DstBlock "Slice" DstPort 1 } } Line { SrcBlock "Reinterpret2" SrcPort 1 DstBlock "I" DstPort 1 } Line { SrcBlock "Reinterpret3" SrcPort 1 DstBlock "Q" DstPort 1 } } } Block { BlockType Terminator Name "Terminator" SID "355" Position [865, 340, 885, 360] ZOrder -5 ShowName off } Block { BlockType ToWorkspace Name "To Workspace" SID "18120" Ports [1] Position [1170, 657, 1325, 683] ZOrder -7 ShowName off VariableName "rx_sim_phy_active_debug_out" MaxDataPoints "inf" SampleTime "-1" SaveFormat "Array" } Block { BlockType Reference Name "dbg_payload" SID "356" Ports [1, 1] Position [1080, 663, 1120, 677] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of t" "ype Simulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become t" "op level output ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port on timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "40,14,1,1,white,yellow,1,cc31b7ac,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 14 14 0 ],[0.95 0" ".93 0.65 ]);\nplot([0 40 40 0 0 ],[0 0 14 14 0 ]);\npatch([15.55 18.44 20.44 22.44 24.44 20.44 17.55 15.55 ],[9" ".22 9.22 11.22 9.22 11.22 11.22 11.22 9.22 ],[1 1 1 ]);\npatch([17.55 20.44 18.44 15.55 17.55 ],[7.22 7.22 9.22" " 9.22 7.22 ],[0.985 0.979 0.895 ]);\npatch([15.55 18.44 20.44 17.55 15.55 ],[5.22 5.22 7.22 7.22 5.22 ],[1 1 1 " "]);\npatch([17.55 24.44 22.44 20.44 18.44 15.55 17.55 ],[3.22 3.22 5.22 3.22 5.22 5.22 3.22 ],[0.985 0.979 0.89" "5 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt}\\bf Out ','texmode','on');\nfprin" "tf('','COMMENT: end icon text');" } Block { BlockType Outport Name "I" SID "357" Position [1040, 398, 1070, 412] NamePlacement "alternate" IconDisplay "Port number" } Block { BlockType Outport Name "Q" SID "358" Position [1040, 413, 1070, 427] Port "2" IconDisplay "Port number" } Block { BlockType Outport Name "Buff Rd" SID "359" Position [835, 493, 865, 507] NamePlacement "alternate" Port "3" IconDisplay "Port number" } Block { BlockType Outport Name " IQ valid" SID "360" Position [835, 513, 865, 527] Port "4" IconDisplay "Port number" } Block { BlockType Outport Name "tlast" SID "361" Position [835, 553, 865, 567] Port "5" IconDisplay "Port number" } Line { SrcBlock "Concat" SrcPort 1 DstBlock "Circular Sample\nBuffer" DstPort 2 } Line { SrcBlock "Circular Sample\nBuffer" SrcPort 1 DstBlock "Terminator" DstPort 1 } Line { SrcBlock "FFT Load Ctrl" SrcPort 1 Points [15, 0; 0, -90] Branch { DstBlock "Circular Sample\nBuffer" DstPort 4 } Branch { Points [0, -165] DstBlock "Gateway Out1" DstPort 1 } } Line { SrcBlock "Constant3" SrcPort 1 DstBlock "Circular Sample\nBuffer" DstPort 5 } Line { SrcBlock "Constant4" SrcPort 1 DstBlock "Circular Sample\nBuffer" DstPort 6 } Line { SrcBlock "Logical2" SrcPort 1 DstBlock "Posedge" DstPort 1 } Line { SrcBlock "Posedge" SrcPort 1 Points [30, 0] Branch { Points [0, -140] DstBlock "FFT Load Ctrl" DstPort 3 } Branch { Labels [0, 0] DstBlock "FSM" DstPort 2 } } Line { SrcBlock "FFT Load Ctrl" SrcPort 5 Points [20, 0; 0, 45] Branch { Points [-180, 0] DstBlock "FSM" DstPort 1 } Branch { Points [330, 0; 0, -320] DstBlock "Gateway Out7" DstPort 1 } } Line { SrcBlock "FSM" SrcPort 3 Points [30, 0; 0, -75; -150, 0; 0, -30] DstBlock "FFT Load Ctrl" DstPort 6 } Line { Labels [0, 0] SrcBlock "Circular Sample\nBuffer" SrcPort 2 DstBlock "Slice" DstPort 1 } Line { SrcBlock "FSM" SrcPort 1 Points [15, 0; 0, -45; -155, 0; 0, -70] DstBlock "FFT Load Ctrl" DstPort 4 } Line { SrcBlock "FFT Load Ctrl" SrcPort 3 Points [55, 0] Branch { DstBlock "Delay" DstPort 1 } Branch { Points [0, 140] DstBlock "Posedge3" DstPort 1 } } Line { SrcBlock "FFT Load Ctrl" SrcPort 2 DstBlock "Delay2" DstPort 1 } Line { SrcBlock "Pkt Done" SrcPort 1 Points [20, 0] Branch { Points [0, 290; -75, 0; 0, 130; 305, 0] Branch { DstBlock "FSM" DstPort 3 } Branch { Points [345, 0; 0, -20] DstBlock "S-R Latch" DstPort 2 } } Branch { Points [0, -100; 685, 0; 0, 95] DstBlock "Gateway Out4" DstPort 1 } } Line { SrcBlock "rx I" SrcPort 1 Points [25, 0] Branch { DstBlock "Concat" DstPort 1 } Branch { Points [0, -145] DstBlock "Gateway Out6" DstPort 1 } } Line { SrcBlock "rx Q" SrcPort 1 DstBlock "Concat" DstPort 2 } Line { SrcBlock "IQ valid" SrcPort 1 Points [240, 0] Branch { DstBlock "Circular Sample\nBuffer" DstPort 3 } Branch { Points [0, -75] DstBlock "Counter" DstPort 1 } } Line { SrcBlock "Slice" SrcPort 1 Points [55, 0] Branch { DstBlock "I" DstPort 1 } Branch { Points [0, -195] DstBlock "Gateway Out5" DstPort 1 } } Line { SrcBlock "Slice" SrcPort 2 DstBlock "Q" DstPort 1 } Line { SrcBlock "FIFO tready" SrcPort 1 DstBlock "FFT Load Ctrl" DstPort 2 } Line { SrcBlock "Delay2" SrcPort 1 DstBlock "Buff Rd" DstPort 1 } Line { SrcBlock "Delay" SrcPort 1 Points [50, 0] Branch { DstBlock " IQ valid" DstPort 1 } Branch { Points [0, -50; 210, 0; 0, -170] DstBlock "Gateway Out8" DstPort 1 } } Line { SrcBlock "FFT Load Ctrl" SrcPort 4 Points [140, 0; 0, 20] DstBlock "tlast" DstPort 1 } Line { SrcBlock "LTS Sync 2" SrcPort 1 DstBlock "Logical2" DstPort 1 } Line { SrcBlock "Pkt Det" SrcPort 1 Points [40, 0] Branch { Points [0, 415] DstBlock "Logical2" DstPort 2 } Branch { Points [0, -100; 855, 0; 0, 110] DstBlock "Gateway Out3" DstPort 1 } } Line { Name "FFT In I" Labels [0, 0] SrcBlock "Gateway Out5" SrcPort 1 DstBlock "Scope" DstPort 2 } Line { Name "Rd Addr" Labels [0, 0] SrcBlock "Gateway Out1" SrcPort 1 DstBlock "Scope" DstPort 3 } Line { Name "Wr Addr" Labels [0, 0] SrcBlock "Gateway Out2" SrcPort 1 DstBlock "Scope" DstPort 4 } Line { Name "Pkt Det" Labels [0, 0] SrcBlock "Gateway Out3" SrcPort 1 DstBlock "Scope" DstPort 5 } Line { SrcBlock "Posedge3" SrcPort 1 DstBlock "S-R Latch" DstPort 1 } Line { SrcBlock "S-R Latch" SrcPort 1 Points [5, 0] Branch { Points [5, 0] Branch { DstBlock "Register" DstPort 1 } Branch { Points [0, 125] DstBlock "Goto" DstPort 1 } } Branch { Points [0, -35; 115, 0; 0, -320] DstBlock "Gateway Out9" DstPort 1 } } Line { Name "Pkt Done" Labels [0, 0] SrcBlock "Gateway Out4" SrcPort 1 DstBlock "Scope" DstPort 6 } Line { Name "ADC I" Labels [0, 0] SrcBlock "Gateway Out6" SrcPort 1 DstBlock "Scope" DstPort 1 } Line { SrcBlock "Register" SrcPort 1 DstBlock "Register1" DstPort 1 } Line { SrcBlock "Register1" SrcPort 1 DstBlock "dbg_payload" DstPort 1 } Line { Name "FFT Load Done" Labels [0, 0] SrcBlock "Gateway Out7" SrcPort 1 DstBlock "Scope" DstPort 7 } Line { SrcBlock "Counter" SrcPort 1 Points [35, 0] Branch { Points [245, 0; 0, 35] DstBlock "Circular Sample\nBuffer" DstPort 1 } Branch { Points [0, 185] DstBlock "FFT Load Ctrl" DstPort 1 } Branch { Points [0, -55] DstBlock "Gateway Out2" DstPort 1 } } Line { SrcBlock "FSM" SrcPort 2 Points [25, 0; 0, -60; -150, 0; 0, -50] DstBlock "FFT Load Ctrl" DstPort 5 } Line { Name "FFT In tvalid" Labels [0, 0] SrcBlock "Gateway Out8" SrcPort 1 DstBlock "Scope" DstPort 8 } Line { Name "DEBUG Payload" Labels [0, 0] SrcBlock "Gateway Out9" SrcPort 1 DstBlock "Scope" DstPort 9 } Line { SrcBlock "dbg_payload" SrcPort 1 DstBlock "To Workspace" DstPort 1 } Annotation { Name "Circular sample buffer records all incoming I/Q samples post pkt det\nSamples are unloaded from th" "e buffer after LTS sync and fed into\nthe FFT (via CFO correction and a FIFO)\n\nThis buffer is required becaus" "e 802.11 uses the same preamble samples\n(the LTS) for sample-level synchronization and CFO estimation. The \nr" "eceived LTS samples must be saved and CFO-corrected before the\nFFT to avoid degrading the channel estimates." Position [577, 88] HorizontalAlignment "left" } } } Block { BlockType Reference Name "Slice1" SID "362" Ports [1, 1] Position [620, 503, 655, 517] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The output type " "is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.

Hardwar" "e notes: In hardware this block costs nothing." nbits "1" boolean_output on mode "Lower Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "0" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "slice" sg_icon_stat "35,14,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 14 14 0 ],[0.77 0.82 0.91" " ]);\nplot([0 35 35 0 0 ],[0 0 14 14 0 ]);\npatch([12.55 15.44 17.44 19.44 21.44 17.44 14.55 12.55 ],[9.22 9.22 11." "22 9.22 11.22 11.22 11.22 9.22 ],[1 1 1 ]);\npatch([14.55 17.44 15.44 12.55 14.55 ],[7.22 7.22 9.22 9.22 7.22 ],[0." "931 0.946 0.973 ]);\npatch([12.55 15.44 17.44 14.55 12.55 ],[5.22 5.22 7.22 7.22 5.22 ],[1 1 1 ]);\npatch([14.55 21" ".44 19.44 17.44 15.44 12.55 14.55 ],[3.22 3.22 5.22 3.22 5.22 5.22 3.22 ],[0.931 0.946 0.973 ]);\nfprintf('','COMME" "NT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('output',1,'[a:b]');" "\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Slice2" SID "363" Ports [1, 1] Position [620, 453, 655, 467] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The output type " "is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.

Hardwar" "e notes: In hardware this block costs nothing." nbits "1" boolean_output on mode "Upper Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "0" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "slice" sg_icon_stat "35,14,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 14 14 0 ],[0.77 0.82 0.91" " ]);\nplot([0 35 35 0 0 ],[0 0 14 14 0 ]);\npatch([12.55 15.44 17.44 19.44 21.44 17.44 14.55 12.55 ],[9.22 9.22 11." "22 9.22 11.22 11.22 11.22 9.22 ],[1 1 1 ]);\npatch([14.55 17.44 15.44 12.55 14.55 ],[7.22 7.22 9.22 9.22 7.22 ],[0." "931 0.946 0.973 ]);\npatch([12.55 15.44 17.44 14.55 12.55 ],[5.22 5.22 7.22 7.22 5.22 ],[1 1 1 ]);\npatch([14.55 21" ".44 19.44 17.44 15.44 12.55 14.55 ],[3.22 3.22 5.22 3.22 5.22 5.22 3.22 ],[0.931 0.946 0.973 ]);\nfprintf('','COMME" "NT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('output',1,'[a:b]');" "\nfprintf('','COMMENT: end icon text');" } Block { BlockType Outport Name "FFT tdata_im" SID "364" Position [1390, 458, 1420, 472] NamePlacement "alternate" IconDisplay "Port number" } Block { BlockType Outport Name "FFT tdata_re" SID "365" Position [1390, 408, 1420, 422] NamePlacement "alternate" Port "2" IconDisplay "Port number" } Block { BlockType Outport Name "FFT tvalid" SID "366" Position [1390, 358, 1420, 372] NamePlacement "alternate" Port "3" IconDisplay "Port number" } Block { BlockType Outport Name "FFT tlast" SID "367" Position [1390, 508, 1420, 522] NamePlacement "alternate" Port "4" IconDisplay "Port number" } Line { SrcBlock "Rx Q" SrcPort 1 Points [65, 0] Branch { Points [315, 0] Branch { Points [0, 120] DstBlock "CFO Estimation" DstPort 3 } Branch { DstBlock "Samp Buffer" DstPort 4 } } Branch { Points [0, -215] DstBlock "Gateway Out7" DstPort 1 } } Line { SrcBlock "Rx I" SrcPort 1 Points [40, 0] Branch { Points [310, 0] Branch { Labels [0, 0] DstBlock "Samp Buffer" DstPort 3 } Branch { Points [0, 125] DstBlock "CFO Estimation" DstPort 2 } } Branch { Points [0, -210] DstBlock "Gateway Out17" DstPort 1 } } Line { SrcBlock "FFT tready" SrcPort 1 Points [15, 0] Branch { Points [10, 0] DstBlock "FIFO" DstPort 5 } Branch { Points [0, -270] DstBlock "Gateway Out9" DstPort 1 } } Line { SrcBlock "Samp Buffer" SrcPort 1 DstBlock "CFO\nCorrection" DstPort 1 } Line { SrcBlock "Samp Buffer" SrcPort 2 Points [90, 0] DstBlock "CFO\nCorrection" DstPort 2 } Line { SrcBlock "CFO\nCorrection" SrcPort 2 DstBlock "FIFO" DstPort 2 } Line { SrcBlock "CFO\nCorrection" SrcPort 3 Points [160, 0] DstBlock "FIFO" DstPort 3 } Line { SrcBlock "CFO\nCorrection" SrcPort 1 Points [125, 0] Branch { Points [35, 0] DstBlock "FIFO" DstPort 1 } Branch { Points [0, -135] DstBlock "Gateway Out4" DstPort 1 } } Line { SrcBlock "Samp Buffer" SrcPort 5 Points [90, 0] DstBlock "CFO\nCorrection" DstPort 5 } Line { SrcBlock "Samp Buffer" SrcPort 4 Points [90, 0] DstBlock "CFO\nCorrection" DstPort 4 } Line { SrcBlock "FIFO" SrcPort 5 Points [25, 0; 0, 45; -600, 0; 0, -130] DstBlock "Samp Buffer" DstPort 7 } Line { SrcBlock "FIFO" SrcPort 4 Points [40, 0] Branch { DstBlock "FFT tlast" DstPort 1 } Branch { Points [0, -250] DstBlock "Gateway Out2" DstPort 1 } } Line { SrcBlock "FIFO" SrcPort 3 DstBlock "FFT tdata_im" DstPort 1 } Line { SrcBlock "FIFO" SrcPort 1 Points [35, 0] Branch { DstBlock "FFT tvalid" DstPort 1 } Branch { Points [0, -115] DstBlock "Gateway Out1" DstPort 1 } } Line { SrcBlock "FIFO" SrcPort 2 DstBlock "FFT tdata_re" DstPort 1 } Line { Name "FIFO IN: tlast" Labels [0, 0] SrcBlock "Gateway Out3" SrcPort 1 DstBlock "FFT in FIFO Ctrl" DstPort 1 } Line { Name "FIFO IN: valid" Labels [0, 0] SrcBlock "Gateway Out4" SrcPort 1 DstBlock "FFT in FIFO Ctrl" DstPort 2 } Line { SrcBlock "IQ Valid" SrcPort 1 Points [95, 0] Branch { Points [320, 0] Branch { Points [0, 115] DstBlock "CFO Estimation" DstPort 4 } Branch { Labels [0, 0] DstBlock "Samp Buffer" DstPort 5 } } Branch { Points [0, -220] DstBlock "Gateway Out5" DstPort 1 } } Line { SrcBlock "Slice1" SrcPort 1 DstBlock "CFO Estimation" DstPort 1 } Line { SrcBlock "Slice2" SrcPort 1 DstBlock "Samp Buffer" DstPort 6 } Line { Name "ADC I" Labels [0, 0] SrcBlock "Gateway Out17" SrcPort 1 DstBlock "ADC/Corr" DstPort 1 } Line { Name "ADC Q" Labels [0, 0] SrcBlock "Gateway Out7" SrcPort 1 DstBlock "ADC/Corr" DstPort 2 } Line { Name "ADC Valid" Labels [0, 0] SrcBlock "Gateway Out5" SrcPort 1 DstBlock "ADC/Corr" DstPort 3 } Line { SrcBlock "Samp Buffer" SrcPort 3 Points [90, 0] DstBlock "CFO\nCorrection" DstPort 3 } Line { SrcBlock "CFO\nCorrection" SrcPort 4 Points [120, 0] Branch { Points [40, 0] DstBlock "FIFO" DstPort 4 } Branch { Labels [1, 0] Points [0, -285] DstBlock "Gateway Out3" DstPort 1 } } Line { Name "FIFO Out: valid" Labels [0, 0] SrcBlock "Gateway Out1" SrcPort 1 DstBlock "FFT in FIFO Ctrl" DstPort 3 } Line { Name "FIFO Out: tlast" Labels [0, 0] SrcBlock "Gateway Out2" SrcPort 1 DstBlock "FFT in FIFO Ctrl" DstPort 4 } Line { Name "FFT in: tready" Labels [0, 0] SrcBlock "Gateway Out9" SrcPort 1 DstBlock "FFT in FIFO Ctrl" DstPort 5 } Line { Name "Pkt Det" Labels [0, 0] SrcBlock "Gateway Out10" SrcPort 1 DstBlock "ADC/Corr" DstPort 4 } Line { SrcBlock "CFO Estimation" SrcPort 1 Points [60, 0; 0, -55] DstBlock "CFO\nCorrection" DstPort 6 } Line { SrcBlock "LTS Sync" SrcPort 1 Points [175, 0] Branch { Points [0, -50] DstBlock "Slice2" DstPort 1 } Branch { DstBlock "Slice1" DstPort 1 } } Line { SrcBlock "Pkt Det" SrcPort 1 Points [125, 0] Branch { DstBlock "Samp Buffer" DstPort 1 } Branch { Points [0, -125] DstBlock "Gateway Out10" DstPort 1 } } Line { SrcBlock "Reset" SrcPort 1 Points [135, 0; 0, 0] Branch { Points [0, 0] Branch { Points [0, -190] DstBlock "Samp Buffer" DstPort 2 } Branch { DstBlock "CFO Estimation" DstPort 5 } } Branch { Points [0, 80; 350, 0] Branch { Points [445, 0] DstBlock "Gateway Out6" DstPort 1 } Branch { Points [0, -140] DstBlock "CFO\nCorrection" DstPort 7 } } } Line { Name "Reset" Labels [0, 0] SrcBlock "Gateway Out6" SrcPort 1 DstBlock "FFT in FIFO Ctrl" DstPort 7 } Annotation { Name "FIXME:\n-DDS runs 1 extra cycle during LTS; it's right for post-LTS FFT inputs\n(still true?)" Position [592, 750] HorizontalAlignment "left" } } } Block { BlockType SubSystem Name "Chan Est & EQ" SID "368" Ports [5, 5] Position [760, 156, 845, 244] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "Chan Est & EQ" Location [862, 511, 1417, 681] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "124" Block { BlockType Inport Name "Rx I" SID "369" Position [230, 253, 260, 267] NamePlacement "alternate" IconDisplay "Port number" } Block { BlockType Inport Name "Rx Q" SID "370" Position [230, 293, 260, 307] NamePlacement "alternate" Port "2" IconDisplay "Port number" } Block { BlockType Inport Name "iq_valid " SID "372" Position [230, 373, 260, 387] NamePlacement "alternate" Port "3" IconDisplay "Port number" } Block { BlockType Inport Name "sc_ind" SID "371" Position [230, 333, 260, 347] NamePlacement "alternate" Port "4" IconDisplay "Port number" } Block { BlockType Inport Name "sym_ind" SID "373" Position [230, 413, 260, 427] NamePlacement "alternate" Port "5" IconDisplay "Port number" } Block { BlockType SubSystem Name "Chan Est" SID "374" Ports [5, 7] Position [320, 239, 395, 441] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "Chan Est" Location [2, 74, 2464, 1576] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "121" Block { BlockType Inport Name "x_re" SID "375" Position [300, 28, 330, 42] NamePlacement "alternate" IconDisplay "Port number" } Block { BlockType Inport Name "x_im" SID "376" Position [300, 63, 330, 77] Port "2" IconDisplay "Port number" } Block { BlockType Inport Name "x_ind" SID "377" Position [440, 368, 470, 382] NamePlacement "alternate" Port "3" IconDisplay "Port number" } Block { BlockType Inport Name "x_valid" SID "378" Position [135, 203, 165, 217] NamePlacement "alternate" Port "4" IconDisplay "Port number" } Block { BlockType Inport Name "Sym Ind" SID "379" Position [135, 263, 165, 277] Port "5" IconDisplay "Port number" } Block { BlockType Abs Name "Abs" SID "380" Position [1140, 731, 1160, 749] ZOrder -1 ShowName off SaturateOnIntegerOverflow off } Block { BlockType Abs Name "Abs1" SID "381" Position [1140, 706, 1160, 724] ZOrder -1 ShowName off SaturateOnIntegerOverflow off } Block { BlockType SubSystem Name "Chan Est Offload" SID "382" Ports [5] Position [1070, 303, 1150, 367] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "Chan Est Offload" Location [1302, 750, 1870, 979] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "125" Block { BlockType Inport Name "x_ind" SID "383" Position [320, 228, 350, 242] NamePlacement "alternate" IconDisplay "Port number" } Block { BlockType Inport Name "x_I" SID "384" Position [320, 258, 350, 272] NamePlacement "alternate" Port "2" IconDisplay "Port number" } Block { BlockType Inport Name "x_Q" SID "385" Position [320, 273, 350, 287] Port "3" IconDisplay "Port number" } Block { BlockType Inport Name "x_valid" SID "386" Position [320, 333, 350, 347] Port "4" IconDisplay "Port number" } Block { BlockType Inport Name "sym_ind" SID "387" Position [320, 388, 350, 402] Port "5" IconDisplay "Port number" } Block { BlockType Reference Name "Concat" SID "388" Ports [2, 1] Position [685, 255, 730, 290] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Concat" SourceType "Xilinx Bus Concatenator Block" infoedit "Concatenates two or more inputs. Output will be cast to an unsigned value with the binary point at z" "ero." num_inputs "2" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "concat" sg_icon_stat "45,35,2,1,white,blue,0,16398980,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 35 35 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 45 45 0 0 ],[0 0 35 35 0 ]);\npatch([10.875 18.1 23.1 28.1 33.1 23.1 15.875 10.875 ],[22.55 22.55 2" "7.55 22.55 27.55 27.55 27.55 22.55 ],[1 1 1 ]);\npatch([15.875 23.1 18.1 10.875 15.875 ],[17.55 17.55 22.55 22.55 " "17.55 ],[0.931 0.946 0.973 ]);\npatch([10.875 18.1 23.1 15.875 10.875 ],[12.55 12.55 17.55 17.55 12.55 ],[1 1 1 ])" ";\npatch([15.875 33.1 28.1 23.1 18.1 10.875 15.875 ],[7.55 7.55 12.55 7.55 12.55 12.55 7.55 ],[0.931 0.946 0.973 ]" ");\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label(" "'input',1,'hi');\ncolor('black');port_label('input',2,'lo');\n\ncolor('black');disp('\\fontsize{20}\\}','texmode'," "'on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Constant1" SID "389" Ports [0, 1] Position [475, 445, 495, 465] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "7" gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "3" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "8" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" sg_icon_stat "20,20,0,1,white,blue,0,2a6960a5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 20 20 0 0 ],[0 0 20 20 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 20 20 0 0 ],[0 0 20 20 0 ]);\npatch([5.55 8.44 10.44 12.44 14.44 10.44 7.55 5.55 ],[12.22 12.22 14." "22 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([7.55 10.44 8.44 5.55 7.55 ],[10.22 10.22 12.22 12.22 10.22 ]" ",[0.931 0.946 0.973 ]);\npatch([5.55 8.44 10.44 7.55 5.55 ],[8.22 8.22 10.22 10.22 8.22 ],[1 1 1 ]);\npatch([7.55 " "14.44 12.44 10.44 8.44 5.55 7.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.931 0.946 0.973 ]);\nfprintf('','COMME" "NT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'7');\nfpr" "intf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Constant3" SID "390" Ports [0, 1] Position [535, 365, 555, 385] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "2" gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "2" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "8" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" sg_icon_stat "20,20,0,1,white,blue,0,fca86624,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 20 20 0 0 ],[0 0 20 20 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 20 20 0 0 ],[0 0 20 20 0 ]);\npatch([5.55 8.44 10.44 12.44 14.44 10.44 7.55 5.55 ],[12.22 12.22 14." "22 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([7.55 10.44 8.44 5.55 7.55 ],[10.22 10.22 12.22 12.22 10.22 ]" ",[0.931 0.946 0.973 ]);\npatch([5.55 8.44 10.44 7.55 5.55 ],[8.22 8.22 10.22 10.22 8.22 ],[1 1 1 ]);\npatch([7.55 " "14.44 12.44 10.44 8.44 5.55 7.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.931 0.946 0.973 ]);\nfprintf('','COMME" "NT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'2');\nfpr" "intf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Convert1" SID "391" Ports [1, 1] Position [510, 257, 540, 273] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do not." gui_display_data_type "Fixed-point" arith_type "Signed (2's comp)" n_bits "16" bin_pt "15" float_type "Single" exp_bits "8" fraction_bits "24" quantization "Truncate" overflow "Wrap" en off latency "0" dbl_ovrd off pipeline off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "convert" sg_icon_stat "30,16,1,1,white,blue,0,edca21da,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 16 16 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 30 30 0 0 ],[0 0 16 16 0 ]);\npatch([10.55 13.44 15.44 17.44 19.44 15.44 12.55 10.55 ],[10.22 10.22" " 12.22 10.22 12.22 12.22 12.22 10.22 ],[1 1 1 ]);\npatch([12.55 15.44 13.44 10.55 12.55 ],[8.22 8.22 10.22 10.22 8" ".22 ],[0.931 0.946 0.973 ]);\npatch([10.55 13.44 15.44 12.55 10.55 ],[6.22 6.22 8.22 8.22 6.22 ],[1 1 1 ]);\npatch" "([12.55 19.44 17.44 15.44 13.44 10.55 12.55 ],[4.22 4.22 6.22 4.22 6.22 6.22 4.22 ],[0.931 0.946 0.973 ]);\nfprint" "f('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('output'" ",1,'cast');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Convert2" SID "392" Ports [1, 1] Position [510, 272, 540, 288] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do not." gui_display_data_type "Fixed-point" arith_type "Signed (2's comp)" n_bits "16" bin_pt "15" float_type "Single" exp_bits "8" fraction_bits "24" quantization "Truncate" overflow "Wrap" en off latency "0" dbl_ovrd off pipeline off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "convert" sg_icon_stat "30,16,1,1,white,blue,0,edca21da,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 16 16 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 30 30 0 0 ],[0 0 16 16 0 ]);\npatch([10.55 13.44 15.44 17.44 19.44 15.44 12.55 10.55 ],[10.22 10.22" " 12.22 10.22 12.22 12.22 12.22 10.22 ],[1 1 1 ]);\npatch([12.55 15.44 13.44 10.55 12.55 ],[8.22 8.22 10.22 10.22 8" ".22 ],[0.931 0.946 0.973 ]);\npatch([10.55 13.44 15.44 12.55 10.55 ],[6.22 6.22 8.22 8.22 6.22 ],[1 1 1 ]);\npatch" "([12.55 19.44 17.44 15.44 13.44 10.55 12.55 ],[4.22 4.22 6.22 4.22 6.22 6.22 4.22 ],[0.931 0.946 0.973 ]);\nfprint" "f('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('output'" ",1,'cast');\nfprintf('','COMMENT: end icon text');" } Block { BlockType From Name "From1" SID "393" Position [320, 473, 485, 497] ZOrder -9 ShowName off GotoTag "RX_PHY_MODE_11N" TagVisibility "global" } Block { BlockType Goto Name "Goto" SID "394" Position [845, 365, 995, 385] ZOrder -10 ShowName off GotoTag "CHAN_EST_VALID" TagVisibility "global" } Block { BlockType Goto Name "Goto1" SID "395" Position [820, 265, 970, 285] ZOrder -10 ShowName off GotoTag "CHAN_EST_IQ_32b" TagVisibility "global" } Block { BlockType Goto Name "Goto2" SID "396" Position [820, 225, 970, 245] ZOrder -10 ShowName off GotoTag "CHAN_EST_IND" TagVisibility "global" } Block { BlockType Reference Name "Logical1" SID "397" Ports [2, 1] Position [675, 363, 705, 447] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "OR" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" sg_icon_stat "30,84,2,1,white,blue,0,7ede7d88,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 84 84 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 30 30 0 0 ],[0 0 84 84 0 ]);\npatch([6.1 11.88 15.88 19.88 23.88 15.88 10.1 6.1 ],[46.44 46.44 50.4" "4 46.44 50.44 50.44 50.44 46.44 ],[1 1 1 ]);\npatch([10.1 15.88 11.88 6.1 10.1 ],[42.44 42.44 46.44 46.44 42.44 ]," "[0.931 0.946 0.973 ]);\npatch([6.1 11.88 15.88 10.1 6.1 ],[38.44 38.44 42.44 42.44 38.44 ],[1 1 1 ]);\npatch([10.1" " 23.88 19.88 15.88 11.88 6.1 10.1 ],[34.44 34.44 38.44 34.44 38.44 38.44 34.44 ],[0.931 0.946 0.973 ]);\nfprintf('" "','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\ncolor('black');disp('or');\nfprin" "tf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical3" SID "398" Ports [2, 1] Position [745, 309, 775, 436] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "AND" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" sg_icon_stat "30,127,2,1,white,blue,0,83a4b621,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 127 127 0 ],[0.77 0.82 0" ".91 ]);\nplot([0 30 30 0 0 ],[0 0 127 127 0 ]);\npatch([6.1 11.88 15.88 19.88 23.88 15.88 10.1 6.1 ],[67.44 67.44 " "71.44 67.44 71.44 71.44 71.44 67.44 ],[1 1 1 ]);\npatch([10.1 15.88 11.88 6.1 10.1 ],[63.44 63.44 67.44 67.44 63.4" "4 ],[0.931 0.946 0.973 ]);\npatch([6.1 11.88 15.88 10.1 6.1 ],[59.44 59.44 63.44 63.44 59.44 ],[1 1 1 ]);\npatch([" "10.1 23.88 19.88 15.88 11.88 6.1 10.1 ],[55.44 55.44 59.44 55.44 59.44 59.44 55.44 ],[0.931 0.946 0.973 ]);\nfprin" "tf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\ncolor('black');disp('and');\n" "fprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical4" SID "399" Ports [2, 1] Position [605, 423, 635, 507] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "AND" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" sg_icon_stat "30,84,2,1,white,blue,0,83a4b621,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 84 84 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 30 30 0 0 ],[0 0 84 84 0 ]);\npatch([6.1 11.88 15.88 19.88 23.88 15.88 10.1 6.1 ],[46.44 46.44 50.4" "4 46.44 50.44 50.44 50.44 46.44 ],[1 1 1 ]);\npatch([10.1 15.88 11.88 6.1 10.1 ],[42.44 42.44 46.44 46.44 42.44 ]," "[0.931 0.946 0.973 ]);\npatch([6.1 11.88 15.88 10.1 6.1 ],[38.44 38.44 42.44 42.44 38.44 ],[1 1 1 ]);\npatch([10.1" " 23.88 19.88 15.88 11.88 6.1 10.1 ],[34.44 34.44 38.44 34.44 38.44 38.44 34.44 ],[0.931 0.946 0.973 ]);\nfprintf('" "','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\ncolor('black');disp('and');\nfpri" "ntf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register" SID "9925" Ports [1, 1] Position [415, 222, 445, 248] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "30,26,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 26 26 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 30 30 0 0 ],[0 0 26 26 0 ]);\npatch([8.325 12.66 15.66 18.66 21.66 15.66 11.325 8.325 ],[16.33 16.3" "3 19.33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([11.325 15.66 12.66 8.325 11.325 ],[13.33 13.33 16.33 16" ".33 13.33 ],[0.931 0.946 0.973 ]);\npatch([8.325 12.66 15.66 11.325 8.325 ],[10.33 10.33 13.33 13.33 10.33 ],[1 1 " "1 ]);\npatch([11.325 21.66 18.66 15.66 12.66 8.325 11.325 ],[7.33 7.33 10.33 7.33 10.33 10.33 7.33 ],[0.931 0.946 " "0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port" "_label('input',1,'d');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\n" "fprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register1" SID "9926" Ports [1, 1] Position [415, 252, 445, 278] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "30,26,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 26 26 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 30 30 0 0 ],[0 0 26 26 0 ]);\npatch([8.325 12.66 15.66 18.66 21.66 15.66 11.325 8.325 ],[16.33 16.3" "3 19.33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([11.325 15.66 12.66 8.325 11.325 ],[13.33 13.33 16.33 16" ".33 13.33 ],[0.931 0.946 0.973 ]);\npatch([8.325 12.66 15.66 11.325 8.325 ],[10.33 10.33 13.33 13.33 10.33 ],[1 1 " "1 ]);\npatch([11.325 21.66 18.66 15.66 12.66 8.325 11.325 ],[7.33 7.33 10.33 7.33 10.33 10.33 7.33 ],[0.931 0.946 " "0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port" "_label('input',1,'d');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\n" "fprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register2" SID "9927" Ports [1, 1] Position [415, 267, 445, 293] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "30,26,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 26 26 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 30 30 0 0 ],[0 0 26 26 0 ]);\npatch([8.325 12.66 15.66 18.66 21.66 15.66 11.325 8.325 ],[16.33 16.3" "3 19.33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([11.325 15.66 12.66 8.325 11.325 ],[13.33 13.33 16.33 16" ".33 13.33 ],[0.931 0.946 0.973 ]);\npatch([8.325 12.66 15.66 11.325 8.325 ],[10.33 10.33 13.33 13.33 10.33 ],[1 1 " "1 ]);\npatch([11.325 21.66 18.66 15.66 12.66 8.325 11.325 ],[7.33 7.33 10.33 7.33 10.33 10.33 7.33 ],[0.931 0.946 " "0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port" "_label('input',1,'d');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\n" "fprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register3" SID "9928" Ports [1, 1] Position [415, 327, 445, 353] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "30,26,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 26 26 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 30 30 0 0 ],[0 0 26 26 0 ]);\npatch([8.325 12.66 15.66 18.66 21.66 15.66 11.325 8.325 ],[16.33 16.3" "3 19.33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([11.325 15.66 12.66 8.325 11.325 ],[13.33 13.33 16.33 16" ".33 13.33 ],[0.931 0.946 0.973 ]);\npatch([8.325 12.66 15.66 11.325 8.325 ],[10.33 10.33 13.33 13.33 10.33 ],[1 1 " "1 ]);\npatch([11.325 21.66 18.66 15.66 12.66 8.325 11.325 ],[7.33 7.33 10.33 7.33 10.33 10.33 7.33 ],[0.931 0.946 " "0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port" "_label('input',1,'d');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\n" "fprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register4" SID "9929" Ports [1, 1] Position [415, 382, 445, 408] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "30,26,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 26 26 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 30 30 0 0 ],[0 0 26 26 0 ]);\npatch([8.325 12.66 15.66 18.66 21.66 15.66 11.325 8.325 ],[16.33 16.3" "3 19.33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([11.325 15.66 12.66 8.325 11.325 ],[13.33 13.33 16.33 16" ".33 13.33 ],[0.931 0.946 0.973 ]);\npatch([8.325 12.66 15.66 11.325 8.325 ],[10.33 10.33 13.33 13.33 10.33 ],[1 1 " "1 ]);\npatch([11.325 21.66 18.66 15.66 12.66 8.325 11.325 ],[7.33 7.33 10.33 7.33 10.33 10.33 7.33 ],[0.931 0.946 " "0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port" "_label('input',1,'d');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\n" "fprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Reinterpret" SID "400" Ports [1, 1] Position [600, 257, 635, 273] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Reinterpret" SourceType "Xilinx Type Reinterpreter Block" infoedit "Changes signal type without altering the binary representation. You can change the signal between s" "igned and unsigned, and relocate the binary point.

Hardware notes: In hardware this block costs nothing.
Example: Suppose the input is 6 bits wide, signed, with 2 fractional bits, and the output is forced to unsig" "ned with 0 fractional bits. Then an input of -2.0 (1110.00 in binary 2's complement) becomes an output of 56 (111" "000 in binary)." force_arith_type on arith_type "Unsigned" force_bin_pt on bin_pt "0" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "reinterpret" sg_icon_stat "35,16,1,1,white,blue,0,6b04d0b0,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 16 16 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 35 35 0 0 ],[0 0 16 16 0 ]);\npatch([12.55 15.44 17.44 19.44 21.44 17.44 14.55 12.55 ],[10.22 10.22" " 12.22 10.22 12.22 12.22 12.22 10.22 ],[1 1 1 ]);\npatch([14.55 17.44 15.44 12.55 14.55 ],[8.22 8.22 10.22 10.22 8" ".22 ],[0.931 0.946 0.973 ]);\npatch([12.55 15.44 17.44 14.55 12.55 ],[6.22 6.22 8.22 8.22 6.22 ],[1 1 1 ]);\npatch" "([14.55 21.44 19.44 17.44 15.44 12.55 14.55 ],[4.22 4.22 6.22 4.22 6.22 6.22 4.22 ],[0.931 0.946 0.973 ]);\nfprint" "f('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');disp('reinterpret" "');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Reinterpret1" SID "401" Ports [1, 1] Position [600, 272, 635, 288] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Reinterpret" SourceType "Xilinx Type Reinterpreter Block" infoedit "Changes signal type without altering the binary representation. You can change the signal between s" "igned and unsigned, and relocate the binary point.

Hardware notes: In hardware this block costs nothing.
Example: Suppose the input is 6 bits wide, signed, with 2 fractional bits, and the output is forced to unsig" "ned with 0 fractional bits. Then an input of -2.0 (1110.00 in binary 2's complement) becomes an output of 56 (111" "000 in binary)." force_arith_type on arith_type "Unsigned" force_bin_pt on bin_pt "0" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "reinterpret" sg_icon_stat "35,16,1,1,white,blue,0,6b04d0b0,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 16 16 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 35 35 0 0 ],[0 0 16 16 0 ]);\npatch([12.55 15.44 17.44 19.44 21.44 17.44 14.55 12.55 ],[10.22 10.22" " 12.22 10.22 12.22 12.22 12.22 10.22 ],[1 1 1 ]);\npatch([14.55 17.44 15.44 12.55 14.55 ],[8.22 8.22 10.22 10.22 8" ".22 ],[0.931 0.946 0.973 ]);\npatch([12.55 15.44 17.44 14.55 12.55 ],[6.22 6.22 8.22 8.22 6.22 ],[1 1 1 ]);\npatch" "([14.55 21.44 19.44 17.44 15.44 12.55 14.55 ],[4.22 4.22 6.22 4.22 6.22 6.22 4.22 ],[0.931 0.946 0.973 ]);\nfprint" "f('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');disp('reinterpret" "');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Relational1" SID "402" Ports [2, 1] Position [535, 424, 580, 466] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Relational" SourceType "Xilinx Arithmetic Relational Operator Block" mode "a=b" en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "relational" sg_icon_stat "45,42,2,1,white,blue,0,2a81ff49,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 42 42 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 45 45 0 0 ],[0 0 42 42 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[27.66 27.66 3" "3.66 27.66 33.66 33.66 33.66 27.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[21.66 21.66 27.66 27.66 21" ".66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[15.66 15.66 21.66 21.66 15.66 ],[1 1 1 ]);\npa" "tch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[9.66 9.66 15.66 9.66 15.66 15.66 9.66 ],[0.931 0.946 0.973 ]);\nf" "printf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('inpu" "t',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('output',1,'\\bfa = b','texmode'," "'on');\ncolor('black');disp(' ');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Relational3" SID "403" Ports [2, 1] Position [600, 364, 645, 406] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Relational" SourceType "Xilinx Arithmetic Relational Operator Block" mode "a=b" en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "relational" sg_icon_stat "45,42,2,1,white,blue,0,2a81ff49,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 42 42 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 45 45 0 0 ],[0 0 42 42 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[27.66 27.66 3" "3.66 27.66 33.66 33.66 33.66 27.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[21.66 21.66 27.66 27.66 21" ".66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[15.66 15.66 21.66 21.66 15.66 ],[1 1 1 ]);\npa" "tch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[9.66 9.66 15.66 9.66 15.66 15.66 9.66 ],[0.931 0.946 0.973 ]);\nf" "printf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('inpu" "t',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('output',1,'\\bfa = b','texmode'," "'on');\ncolor('black');disp(' ');\nfprintf('','COMMENT: end icon text');" } Line { SrcBlock "x_ind" SrcPort 1 DstBlock "Register" DstPort 1 } Line { SrcBlock "x_I" SrcPort 1 DstBlock "Register1" DstPort 1 } Line { SrcBlock "x_Q" SrcPort 1 DstBlock "Register2" DstPort 1 } Line { SrcBlock "x_valid" SrcPort 1 DstBlock "Register3" DstPort 1 } Line { SrcBlock "sym_ind" SrcPort 1 DstBlock "Register4" DstPort 1 } Line { SrcBlock "Convert2" SrcPort 1 DstBlock "Reinterpret1" DstPort 1 } Line { SrcBlock "Convert1" SrcPort 1 DstBlock "Reinterpret" DstPort 1 } Line { SrcBlock "Logical3" SrcPort 1 DstBlock "Goto" DstPort 1 } Line { SrcBlock "Constant3" SrcPort 1 DstBlock "Relational3" DstPort 1 } Line { SrcBlock "Reinterpret1" SrcPort 1 DstBlock "Concat" DstPort 2 } Line { SrcBlock "Reinterpret" SrcPort 1 DstBlock "Concat" DstPort 1 } Line { SrcBlock "Concat" SrcPort 1 DstBlock "Goto1" DstPort 1 } Line { SrcBlock "Relational3" SrcPort 1 DstBlock "Logical1" DstPort 1 } Line { SrcBlock "Logical1" SrcPort 1 DstBlock "Logical3" DstPort 2 } Line { SrcBlock "Logical4" SrcPort 1 Points [10, 0; 0, -40] DstBlock "Logical1" DstPort 2 } Line { SrcBlock "Constant1" SrcPort 1 DstBlock "Relational1" DstPort 2 } Line { SrcBlock "Relational1" SrcPort 1 DstBlock "Logical4" DstPort 1 } Line { SrcBlock "From1" SrcPort 1 DstBlock "Logical4" DstPort 2 } Line { SrcBlock "Register" SrcPort 1 DstBlock "Goto2" DstPort 1 } Line { SrcBlock "Register1" SrcPort 1 DstBlock "Convert1" DstPort 1 } Line { SrcBlock "Register2" SrcPort 1 DstBlock "Convert2" DstPort 1 } Line { SrcBlock "Register3" SrcPort 1 DstBlock "Logical3" DstPort 1 } Line { SrcBlock "Register4" SrcPort 1 Points [45, 0] Branch { DstBlock "Relational3" DstPort 2 } Branch { Points [0, 40] DstBlock "Relational1" DstPort 1 } } Annotation { Name "These signals route to the packet buffer interface. The\nchan ests are written to dedicated bytes in eac" "h packet\nbuffer, ahead of the packet payload. This is way\nbetter than using a Sysgen shared memory block here\ns" "ince it allows CPU High to treat the H ests as meta data\nalongside the packet contents, with no further\ninvolvem" "ent from the PHY or CPU Low.\n\nEstimates are written to the pkt buf after all training is \ncomplete. Training fr" "om the L-LTF are written in OFDM\nsymbol 2 (SIGNAL). For 11n Rx the estimates are over-\nwritten during sybmol 7 (" "first DATA). This assumes 1\nspatial stream.\n\nThe timing of CHAN_EST_VALID is critical. This signal \nbecomes th" "e write enable on the pkt buf BRAM interface.\nThe CHAN_EST_VALID signal must *not* assert when actual\nbytes are " "being written to the pkt buf. Asserting on OFDM syms\n2 and 7 is safe- there cannot be any decoded bits at these s" "ymbol\nintervals. Any changes to pkt buf or decoder timing must be\nchecked for conflicts in BRAM write enable ass" "ertion between\nchan ests and decoded bytes!" Position [726, 600] HorizontalAlignment "left" } } } Block { BlockType Reference Name "Constant" SID "9605" Ports [0, 1] Position [1275, 327, 1330, 353] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "0.4625" gui_display_data_type "Fixed-point" arith_type "Signed (2's comp)" n_bits "19" bin_pt "17" preci_type "Single" exp_width "8" frac_width "24" explicit_period on period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" sg_icon_stat "55,26,0,1,white,blue,0,8a69a89d,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 55 55 0 0 ],[0 0 26 26 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 55 55 0 0 ],[0 0 26 26 0 ]);\npatch([20.325 24.66 27.66 30.66 33.66 27.66 23.325 20.325 ]" ",[16.33 16.33 19.33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([23.325 27.66 24.66 20.325 23.325 ],[13.3" "3 13.33 16.33 16.33 13.33 ],[0.931 0.946 0.973 ]);\npatch([20.325 24.66 27.66 23.325 20.325 ],[10.33 10.33 13.3" "3 13.33 10.33 ],[1 1 1 ]);\npatch([23.325 33.66 30.66 27.66 24.66 20.325 23.325 ],[7.33 7.33 10.33 7.33 10.33 1" "0.33 7.33 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon " "text');\ncolor('black');port_label('output',1,'0.46250152587890625');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Constant1" SID "9606" Ports [0, 1] Position [1275, 432, 1330, 458] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "0" gui_display_data_type "Fixed-point" arith_type "Signed (2's comp)" n_bits "19" bin_pt "17" preci_type "Single" exp_width "8" frac_width "24" explicit_period on period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" sg_icon_stat "55,26,0,1,white,blue,0,bf4ddd8b,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 55 55 0 0 ],[0 0 26 26 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 55 55 0 0 ],[0 0 26 26 0 ]);\npatch([20.325 24.66 27.66 30.66 33.66 27.66 23.325 20.325 ]" ",[16.33 16.33 19.33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([23.325 27.66 24.66 20.325 23.325 ],[13.3" "3 13.33 16.33 16.33 13.33 ],[0.931 0.946 0.973 ]);\npatch([20.325 24.66 27.66 23.325 20.325 ],[10.33 10.33 13.3" "3 13.33 10.33 ],[1 1 1 ]);\npatch([23.325 33.66 30.66 27.66 24.66 20.325 23.325 ],[7.33 7.33 10.33 7.33 10.33 1" "0.33 7.33 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon " "text');\ncolor('black');port_label('output',1,'0');\nfprintf('','COMMENT: end icon text');" } Block { BlockType SubSystem Name "Control" SID "404" Ports [1, 4] Position [250, 215, 355, 320] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "Control" Location [317, 558, 610, 737] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "125" Block { BlockType Inport Name "Sym Ind" SID "405" Position [210, 68, 240, 82] IconDisplay "Port number" } Block { BlockType Reference Name "Constant1" SID "406" Ports [0, 1] Position [295, 107, 330, 133] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "2" gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "2" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "8" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" sg_icon_stat "35,26,0,1,white,blue,0,fca86624,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 26 26 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 35 35 0 0 ],[0 0 26 26 0 ]);\npatch([10.325 14.66 17.66 20.66 23.66 17.66 13.325 10.325 ],[16.33 16" ".33 19.33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([13.325 17.66 14.66 10.325 13.325 ],[13.33 13.33 16.33" " 16.33 13.33 ],[0.931 0.946 0.973 ]);\npatch([10.325 14.66 17.66 13.325 10.325 ],[10.33 10.33 13.33 13.33 10.33 ]," "[1 1 1 ]);\npatch([13.325 23.66 20.66 17.66 14.66 10.325 13.325 ],[7.33 7.33 10.33 7.33 10.33 10.33 7.33 ],[0.931 " "0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black'" ");port_label('output',1,'2');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Constant2" SID "407" Ports [0, 1] Position [295, 42, 330, 68] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "0" gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "2" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "8" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" sg_icon_stat "35,26,0,1,white,blue,0,bf4ddd8b,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 26 26 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 35 35 0 0 ],[0 0 26 26 0 ]);\npatch([10.325 14.66 17.66 20.66 23.66 17.66 13.325 10.325 ],[16.33 16" ".33 19.33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([13.325 17.66 14.66 10.325 13.325 ],[13.33 13.33 16.33" " 16.33 13.33 ],[0.931 0.946 0.973 ]);\npatch([10.325 14.66 17.66 13.325 10.325 ],[10.33 10.33 13.33 13.33 10.33 ]," "[1 1 1 ]);\npatch([13.325 23.66 20.66 17.66 14.66 10.325 13.325 ],[7.33 7.33 10.33 7.33 10.33 10.33 7.33 ],[0.931 " "0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black'" ");port_label('output',1,'0');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Constant3" SID "408" Ports [0, 1] Position [295, 412, 330, 438] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "5" gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "3" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "8" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" sg_icon_stat "35,26,0,1,white,blue,0,98872051,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 26 26 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 35 35 0 0 ],[0 0 26 26 0 ]);\npatch([10.325 14.66 17.66 20.66 23.66 17.66 13.325 10.325 ],[16.33 16" ".33 19.33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([13.325 17.66 14.66 10.325 13.325 ],[13.33 13.33 16.33" " 16.33 13.33 ],[0.931 0.946 0.973 ]);\npatch([10.325 14.66 17.66 13.325 10.325 ],[10.33 10.33 13.33 13.33 10.33 ]," "[1 1 1 ]);\npatch([13.325 23.66 20.66 17.66 14.66 10.325 13.325 ],[7.33 7.33 10.33 7.33 10.33 10.33 7.33 ],[0.931 " "0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black'" ");port_label('output',1,'5');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Constant4" SID "409" Ports [0, 1] Position [295, 257, 330, 283] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "6" gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "3" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "8" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" sg_icon_stat "35,26,0,1,white,blue,0,f0403ad7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 26 26 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 35 35 0 0 ],[0 0 26 26 0 ]);\npatch([10.325 14.66 17.66 20.66 23.66 17.66 13.325 10.325 ],[16.33 16" ".33 19.33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([13.325 17.66 14.66 10.325 13.325 ],[13.33 13.33 16.33" " 16.33 13.33 ],[0.931 0.946 0.973 ]);\npatch([10.325 14.66 17.66 13.325 10.325 ],[10.33 10.33 13.33 13.33 10.33 ]," "[1 1 1 ]);\npatch([13.325 23.66 20.66 17.66 14.66 10.325 13.325 ],[7.33 7.33 10.33 7.33 10.33 10.33 7.33 ],[0.931 " "0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black'" ");port_label('output',1,'6');\nfprintf('','COMMENT: end icon text');" } Block { BlockType From Name "From" SID "410" Position [75, 298, 240, 322] ZOrder -9 ShowName off GotoTag "RX_PHY_MODE_11N_AC" TagVisibility "global" } Block { BlockType Reference Name "Logical1" SID "411" Ports [2, 1] Position [580, 329, 620, 371] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "AND" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" sg_icon_stat "40,42,2,1,white,blue,0,83a4b621,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 42 42 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 40 40 0 0 ],[0 0 42 42 0 ]);\npatch([8.875 16.1 21.1 26.1 31.1 21.1 13.875 8.875 ],[26.55 26.55 31." "55 26.55 31.55 31.55 31.55 26.55 ],[1 1 1 ]);\npatch([13.875 21.1 16.1 8.875 13.875 ],[21.55 21.55 26.55 26.55 21." "55 ],[0.931 0.946 0.973 ]);\npatch([8.875 16.1 21.1 13.875 8.875 ],[16.55 16.55 21.55 21.55 16.55 ],[1 1 1 ]);\npa" "tch([13.875 31.1 26.1 21.1 16.1 8.875 13.875 ],[11.55 11.55 16.55 11.55 16.55 16.55 11.55 ],[0.931 0.946 0.973 ]);" "\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\ncolor('black');disp('a" "nd');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical2" SID "412" Ports [2, 1] Position [690, 54, 730, 96] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "OR" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" sg_icon_stat "40,42,2,1,white,blue,0,7ede7d88,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 42 42 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 40 40 0 0 ],[0 0 42 42 0 ]);\npatch([8.875 16.1 21.1 26.1 31.1 21.1 13.875 8.875 ],[26.55 26.55 31." "55 26.55 31.55 31.55 31.55 26.55 ],[1 1 1 ]);\npatch([13.875 21.1 16.1 8.875 13.875 ],[21.55 21.55 26.55 26.55 21." "55 ],[0.931 0.946 0.973 ]);\npatch([8.875 16.1 21.1 13.875 8.875 ],[16.55 16.55 21.55 21.55 16.55 ],[1 1 1 ]);\npa" "tch([13.875 31.1 26.1 21.1 16.1 8.875 13.875 ],[11.55 11.55 16.55 11.55 16.55 16.55 11.55 ],[0.931 0.946 0.973 ]);" "\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\ncolor('black');disp('o" "r');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical3" SID "413" Ports [2, 1] Position [690, 99, 730, 141] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "OR" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" sg_icon_stat "40,42,2,1,white,blue,0,7ede7d88,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 42 42 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 40 40 0 0 ],[0 0 42 42 0 ]);\npatch([8.875 16.1 21.1 26.1 31.1 21.1 13.875 8.875 ],[26.55 26.55 31." "55 26.55 31.55 31.55 31.55 26.55 ],[1 1 1 ]);\npatch([13.875 21.1 16.1 8.875 13.875 ],[21.55 21.55 26.55 26.55 21." "55 ],[0.931 0.946 0.973 ]);\npatch([8.875 16.1 21.1 13.875 8.875 ],[16.55 16.55 21.55 21.55 16.55 ],[1 1 1 ]);\npa" "tch([13.875 31.1 26.1 21.1 16.1 8.875 13.875 ],[11.55 11.55 16.55 11.55 16.55 16.55 11.55 ],[0.931 0.946 0.973 ]);" "\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\ncolor('black');disp('o" "r');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical4" SID "414" Ports [2, 1] Position [580, 249, 620, 291] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "AND" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" sg_icon_stat "40,42,2,1,white,blue,0,83a4b621,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 42 42 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 40 40 0 0 ],[0 0 42 42 0 ]);\npatch([8.875 16.1 21.1 26.1 31.1 21.1 13.875 8.875 ],[26.55 26.55 31." "55 26.55 31.55 31.55 31.55 26.55 ],[1 1 1 ]);\npatch([13.875 21.1 16.1 8.875 13.875 ],[21.55 21.55 26.55 26.55 21." "55 ],[0.931 0.946 0.973 ]);\npatch([8.875 16.1 21.1 13.875 8.875 ],[16.55 16.55 21.55 21.55 16.55 ],[1 1 1 ]);\npa" "tch([13.875 31.1 26.1 21.1 16.1 8.875 13.875 ],[11.55 11.55 16.55 11.55 16.55 16.55 11.55 ],[0.931 0.946 0.973 ]);" "\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\ncolor('black');disp('a" "nd');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical5" SID "415" Ports [2, 1] Position [495, 392, 525, 483] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "OR" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" sg_icon_stat "30,91,2,1,white,blue,0,7ede7d88,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 91 91 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 30 30 0 0 ],[0 0 91 91 0 ]);\npatch([6.1 11.88 15.88 19.88 23.88 15.88 10.1 6.1 ],[49.44 49.44 53.4" "4 49.44 53.44 53.44 53.44 49.44 ],[1 1 1 ]);\npatch([10.1 15.88 11.88 6.1 10.1 ],[45.44 45.44 49.44 49.44 45.44 ]," "[0.931 0.946 0.973 ]);\npatch([6.1 11.88 15.88 10.1 6.1 ],[41.44 41.44 45.44 45.44 41.44 ],[1 1 1 ]);\npatch([10.1" " 23.88 19.88 15.88 11.88 6.1 10.1 ],[37.44 37.44 41.44 37.44 41.44 41.44 37.44 ],[0.931 0.946 0.973 ]);\nfprintf('" "','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\ncolor('black');disp('or');\nfprin" "tf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical6" SID "416" Ports [2, 1] Position [580, 409, 620, 451] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "AND" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" sg_icon_stat "40,42,2,1,white,blue,0,83a4b621,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 42 42 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 40 40 0 0 ],[0 0 42 42 0 ]);\npatch([8.875 16.1 21.1 26.1 31.1 21.1 13.875 8.875 ],[26.55 26.55 31." "55 26.55 31.55 31.55 31.55 26.55 ],[1 1 1 ]);\npatch([13.875 21.1 16.1 8.875 13.875 ],[21.55 21.55 26.55 26.55 21." "55 ],[0.931 0.946 0.973 ]);\npatch([8.875 16.1 21.1 13.875 8.875 ],[16.55 16.55 21.55 21.55 16.55 ],[1 1 1 ]);\npa" "tch([13.875 31.1 26.1 21.1 16.1 8.875 13.875 ],[11.55 11.55 16.55 11.55 16.55 16.55 11.55 ],[0.931 0.946 0.973 ]);" "\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\ncolor('black');disp('a" "nd');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical7" SID "417" Ports [2, 1] Position [675, 399, 715, 441] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "OR" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" sg_icon_stat "40,42,2,1,white,blue,0,7ede7d88,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 42 42 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 40 40 0 0 ],[0 0 42 42 0 ]);\npatch([8.875 16.1 21.1 26.1 31.1 21.1 13.875 8.875 ],[26.55 26.55 31." "55 26.55 31.55 31.55 31.55 26.55 ],[1 1 1 ]);\npatch([13.875 21.1 16.1 8.875 13.875 ],[21.55 21.55 26.55 26.55 21." "55 ],[0.931 0.946 0.973 ]);\npatch([8.875 16.1 21.1 13.875 8.875 ],[16.55 16.55 21.55 21.55 16.55 ],[1 1 1 ]);\npa" "tch([13.875 31.1 26.1 21.1 16.1 8.875 13.875 ],[11.55 11.55 16.55 11.55 16.55 16.55 11.55 ],[0.931 0.946 0.973 ]);" "\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\ncolor('black');disp('o" "r');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Relational1" SID "418" Ports [2, 1] Position [410, 89, 455, 131] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Relational" SourceType "Xilinx Arithmetic Relational Operator Block" mode "a=b" en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "relational" sg_icon_stat "45,42,2,1,white,blue,0,6218dc92,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 42 42 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 45 45 0 0 ],[0 0 42 42 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[27.66 27.66 3" "3.66 27.66 33.66 33.66 33.66 27.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[21.66 21.66 27.66 27.66 21" ".66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[15.66 15.66 21.66 21.66 15.66 ],[1 1 1 ]);\npa" "tch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[9.66 9.66 15.66 9.66 15.66 15.66 9.66 ],[0.931 0.946 0.973 ]);\nf" "printf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('inpu" "t',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('output',1,'\\bfa \\geq b','texmo" "de','on');\ncolor('black');disp(' ');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Relational4" SID "421" Ports [2, 1] Position [410, 239, 455, 281] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Relational" SourceType "Xilinx Arithmetic Relational Operator Block" mode "a=b" en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "relational" sg_icon_stat "45,42,2,1,white,blue,0,2a81ff49,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 42 42 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 45 45 0 0 ],[0 0 42 42 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[27.66 27.66 3" "3.66 27.66 33.66 33.66 33.66 27.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[21.66 21.66 27.66 27.66 21" ".66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[15.66 15.66 21.66 21.66 15.66 ],[1 1 1 ]);\npa" "tch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[9.66 9.66 15.66 9.66 15.66 15.66 9.66 ],[0.931 0.946 0.973 ]);\nf" "printf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('inpu" "t',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('output',1,'\\bfa = b','texmode'," "'on');\ncolor('black');disp(' ');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Relational5" SID "422" Ports [2, 1] Position [410, 439, 455, 481] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Relational" SourceType "Xilinx Arithmetic Relational Operator Block" mode "a=b" en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "relational" sg_icon_stat "45,42,2,1,white,blue,0,2a81ff49,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 42 42 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 45 45 0 0 ],[0 0 42 42 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[27.66 27.66 3" "3.66 27.66 33.66 33.66 33.66 27.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[21.66 21.66 27.66 27.66 21" ".66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[15.66 15.66 21.66 21.66 15.66 ],[1 1 1 ]);\npa" "tch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[9.66 9.66 15.66 9.66 15.66 15.66 9.66 ],[0.931 0.946 0.973 ]);\nf" "printf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('inpu" "t',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('output',1,'\\bfa = b','texmode'," "'on');\ncolor('black');disp(' ');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Relational6" SID "423" Ports [2, 1] Position [410, 394, 455, 436] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Relational" SourceType "Xilinx Arithmetic Relational Operator Block" mode "a=b" en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "relational" sg_icon_stat "45,42,2,1,white,blue,0,2a81ff49,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 42 42 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 45 45 0 0 ],[0 0 42 42 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[27.66 27.66 3" "3.66 27.66 33.66 33.66 33.66 27.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[21.66 21.66 27.66 27.66 21" ".66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[15.66 15.66 21.66 21.66 15.66 ],[1 1 1 ]);\npa" "tch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[9.66 9.66 15.66 9.66 15.66 15.66 9.66 ],[0.931 0.946 0.973 ]);\nf" "printf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('inpu" "t',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('output',1,'\\bfa = b','texmode'," "'on');\ncolor('black');disp(' ');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Outport Name "Est WrEn" SID "425" Position [800, 113, 830, 127] IconDisplay "Port number" } Block { BlockType Outport Name "Est Overwrite" SID "424" Position [800, 68, 830, 82] Port "2" IconDisplay "Port number" } Block { BlockType Outport Name "Scale" SID "426" Position [800, 343, 830, 357] Port "3" IconDisplay "Port number" } Block { BlockType Outport Name "Sym Invalid" SID "427" Position [800, 413, 830, 427] Port "4" IconDisplay "Port number" } Line { SrcBlock "Constant2" SrcPort 1 DstBlock "Relational2" DstPort 1 } Line { SrcBlock "Constant1" SrcPort 1 DstBlock "Relational1" DstPort 2 } Line { SrcBlock "Sym Ind" SrcPort 1 Points [130, 0] Branch { DstBlock "Relational2" DstPort 2 } Branch { Points [0, 25] Branch { DstBlock "Relational1" DstPort 1 } Branch { Points [0, 150] Branch { DstBlock "Relational4" DstPort 1 } Branch { Points [0, 80] Branch { DstBlock "Relational3" DstPort 1 } Branch { Points [0, 75] Branch { Points [0, 45] DstBlock "Relational5" DstPort 1 } Branch { DstBlock "Relational6" DstPort 1 } } } } } } Line { SrcBlock "Relational2" SrcPort 1 DstBlock "Logical2" DstPort 1 } Line { SrcBlock "Relational1" SrcPort 1 Points [190, 0] Branch { DstBlock "Logical3" DstPort 1 } Branch { Points [0, 300] DstBlock "Logical7" DstPort 1 } } Line { SrcBlock "Logical2" SrcPort 1 DstBlock "Est Overwrite" DstPort 1 } Line { SrcBlock "Logical4" SrcPort 1 Points [20, 0; 0, -140] Branch { DstBlock "Logical3" DstPort 2 } Branch { Points [0, -45] DstBlock "Logical2" DstPort 2 } } Line { SrcBlock "Logical3" SrcPort 1 DstBlock "Est WrEn" DstPort 1 } Line { SrcBlock "Relational4" SrcPort 1 DstBlock "Logical4" DstPort 1 } Line { SrcBlock "Constant4" SrcPort 1 Points [35, 0] Branch { DstBlock "Relational4" DstPort 2 } Branch { Points [0, 80] Branch { DstBlock "Relational3" DstPort 2 } Branch { Points [0, 120] DstBlock "Relational5" DstPort 2 } } } Line { SrcBlock "From" SrcPort 1 Points [310, 0] Branch { Points [0, -30] DstBlock "Logical4" DstPort 2 } Branch { Points [0, 50] Branch { DstBlock "Logical1" DstPort 2 } Branch { Points [0, 60] DstBlock "Logical6" DstPort 1 } } } Line { SrcBlock "Relational3" SrcPort 1 DstBlock "Logical1" DstPort 1 } Line { SrcBlock "Logical1" SrcPort 1 DstBlock "Scale" DstPort 1 } Line { SrcBlock "Constant3" SrcPort 1 DstBlock "Relational6" DstPort 2 } Line { SrcBlock "Relational6" SrcPort 1 DstBlock "Logical5" DstPort 1 } Line { SrcBlock "Relational5" SrcPort 1 DstBlock "Logical5" DstPort 2 } Line { SrcBlock "Logical5" SrcPort 1 DstBlock "Logical6" DstPort 2 } Line { SrcBlock "Logical7" SrcPort 1 DstBlock "Sym Invalid" DstPort 1 } Line { SrcBlock "Logical6" SrcPort 1 DstBlock "Logical7" DstPort 2 } Annotation { Name "OFDM Symbols in 11a/g:\n0: LTF (BPSK)\n1: LTF (BPSK)\n2: SIG (BPSK)\n3-N: Data" Position [144, 588] HorizontalAlignment "left" } Annotation { Name "OFDM Symbols in 11n SISO:\n0: L-LTF (BPSK)\n1: L-LTF (BPSK)\n2: L-SIG (BPSK)\n3: HT-SIG1 (QBPSK)\n4: HT-" "SIG2 (QBPSK)\n5: HT-STF\n6: HT-LFT1\n7-N: Data" Position [294, 613] HorizontalAlignment "left" } Annotation { Name "OFDM Symbols in 11ac SISO:\n0: L-LTF (BPSK)\n1: L-LTF (BPSK)\n2: L-SIG (BPSK)\n3: VHT-SIGA1 (BPSK)\n4: V" "HT-SIGA2 (QBPSK)\n5: VHT-STF\n6: VHT-LFT1\n7: VHT-SIGB\n8-N: Data" Position [469, 628] HorizontalAlignment "left" } Annotation { Name "Downstream blocks should ignore Rx I/Q and H_est I/Q\nduring all training symbols in all PHY modes" Position [987, 424] } } } Block { BlockType Reference Name "Delay1" SID "9950" Ports [1, 1] Position [810, 436, 830, 454] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flo" "p." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en off latency "6" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[0, 0, 0, 0, 0, 0, 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" block_version "VER_STRING_GOES_HERE" sg_icon_stat "20,18,1,1,white,blue,0,aa5bc30d,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 20 20 0 0 ],[0 0 18 18 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 20 20 0 0 ],[0 0 18 18 0 ]);\npatch([5.55 8.44 10.44 12.44 14.44 10.44 7.55 5.55 ],[11.22" " 11.22 13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([7.55 10.44 8.44 5.55 7.55 ],[9.22 9.22 11.22 11" ".22 9.22 ],[0.931 0.946 0.973 ]);\npatch([5.55 8.44 10.44 7.55 5.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);\np" "atch([7.55 14.44 12.44 10.44 8.44 5.55 7.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\nfpr" "intf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');disp('z^{-6" "}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Delay2" SID "9951" Ports [1, 1] Position [810, 486, 830, 504] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flo" "p." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en off latency "6" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[0, 0, 0, 0, 0, 0, 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" block_version "VER_STRING_GOES_HERE" sg_icon_stat "20,18,1,1,white,blue,0,aa5bc30d,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 20 20 0 0 ],[0 0 18 18 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 20 20 0 0 ],[0 0 18 18 0 ]);\npatch([5.55 8.44 10.44 12.44 14.44 10.44 7.55 5.55 ],[11.22" " 11.22 13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([7.55 10.44 8.44 5.55 7.55 ],[9.22 9.22 11.22 11" ".22 9.22 ],[0.931 0.946 0.973 ]);\npatch([5.55 8.44 10.44 7.55 5.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);\np" "atch([7.55 14.44 12.44 10.44 8.44 5.55 7.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\nfpr" "intf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');disp('z^{-6" "}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Delay3" SID "9952" Ports [1, 1] Position [810, 26, 830, 44] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flo" "p." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en off latency "6" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[0, 0, 0, 0, 0, 0, 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" block_version "VER_STRING_GOES_HERE" sg_icon_stat "20,18,1,1,white,blue,0,aa5bc30d,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 20 20 0 0 ],[0 0 18 18 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 20 20 0 0 ],[0 0 18 18 0 ]);\npatch([5.55 8.44 10.44 12.44 14.44 10.44 7.55 5.55 ],[11.22" " 11.22 13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([7.55 10.44 8.44 5.55 7.55 ],[9.22 9.22 11.22 11" ".22 9.22 ],[0.931 0.946 0.973 ]);\npatch([5.55 8.44 10.44 7.55 5.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);\np" "atch([7.55 14.44 12.44 10.44 8.44 5.55 7.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\nfpr" "intf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');disp('z^{-6" "}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Delay4" SID "9953" Ports [1, 1] Position [810, 61, 830, 79] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flo" "p." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en off latency "6" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[0, 0, 0, 0, 0, 0, 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" block_version "VER_STRING_GOES_HERE" sg_icon_stat "20,18,1,1,white,blue,0,aa5bc30d,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 20 20 0 0 ],[0 0 18 18 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 20 20 0 0 ],[0 0 18 18 0 ]);\npatch([5.55 8.44 10.44 12.44 14.44 10.44 7.55 5.55 ],[11.22" " 11.22 13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([7.55 10.44 8.44 5.55 7.55 ],[9.22 9.22 11.22 11" ".22 9.22 ],[0.931 0.946 0.973 ]);\npatch([5.55 8.44 10.44 7.55 5.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);\np" "atch([7.55 14.44 12.44 10.44 8.44 5.55 7.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\nfpr" "intf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');disp('z^{-6" "}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Delay5" SID "9753" Ports [1, 1] Position [810, 366, 830, 384] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flo" "p." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en off latency "6" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[0, 0, 0, 0, 0, 0, 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" block_version "VER_STRING_GOES_HERE" sg_icon_stat "20,18,1,1,white,blue,0,aa5bc30d,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 20 20 0 0 ],[0 0 18 18 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 20 20 0 0 ],[0 0 18 18 0 ]);\npatch([5.55 8.44 10.44 12.44 14.44 10.44 7.55 5.55 ],[11.22" " 11.22 13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([7.55 10.44 8.44 5.55 7.55 ],[9.22 9.22 11.22 11" ".22 9.22 ],[0.931 0.946 0.973 ]);\npatch([5.55 8.44 10.44 7.55 5.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);\np" "atch([7.55 14.44 12.44 10.44 8.44 5.55 7.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\nfpr" "intf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');disp('z^{-6" "}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType SubSystem Name "Estimate Buffers" SID "441" Ports [7, 2] Position [740, 135, 850, 325] NamePlacement "alternate" MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "Estimate Buffers" Location [2, 70, 2464, 1580] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "x_I" SID "442" Position [145, 218, 175, 232] IconDisplay "Port number" } Block { BlockType Inport Name "x_Q" SID "9824" Position [145, 588, 175, 602] Port "2" IconDisplay "Port number" } Block { BlockType Inport Name "Empty Sc" SID "9669" Position [145, 438, 175, 452] Port "3" IconDisplay "Port number" } Block { BlockType Inport Name "Est_WE" SID "444" Position [145, 278, 175, 292] Port "4" IconDisplay "Port number" } Block { BlockType Inport Name "First Sym" SID "445" Position [145, 358, 175, 372] Port "5" IconDisplay "Port number" } Block { BlockType Inport Name "Scale" SID "446" Position [810, 218, 840, 232] Port "6" IconDisplay "Port number" } Block { BlockType Inport Name "Est_Addr" SID "443" Position [145, 313, 175, 327] Port "7" IconDisplay "Port number" } Block { BlockType Reference Name "AddSub1" SID "9830" Ports [2, 1] Position [390, 563, 435, 607] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/AddSub" SourceType "Xilinx Adder/Subtracter Block" mode "Addition" use_carryin off use_carryout off en off latency "0" precision "User Defined" arith_type "Signed (2's comp)" n_bits "18" bin_pt "15" quantization "Truncate" overflow "Flag as error" dbl_ovrd off use_behavioral_HDL on hw_selection "Fabric" pipelined off xl_use_area off xl_area "[0, 0, 0, 0, 0, 0, 0]" use_rpm "on" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "addsub" block_version "VER_STRING_GOES_HERE" sg_icon_stat "45,44,2,1,white,blue,0,e139daf6,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 44 44 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 45 45 0 0 ],[0 0 44 44 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[28.66 28.66 3" "4.66 28.66 34.66 34.66 34.66 28.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[22.66 22.66 28.66 28.66 22" ".66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[16.66 16.66 22.66 22.66 16.66 ],[1 1 1 ]);\npa" "tch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[10.66 10.66 16.66 10.66 16.66 16.66 10.66 ],[0.931 0.946 0.973 ])" ";\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('" "input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('output',1,'\\bf{a + b}','tex" "mode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "AddSub2" SID "447" Ports [2, 1] Position [405, 193, 450, 237] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/AddSub" SourceType "Xilinx Adder/Subtracter Block" mode "Addition" use_carryin off use_carryout off en off latency "0" precision "User Defined" arith_type "Signed (2's comp)" n_bits "18" bin_pt "15" quantization "Truncate" overflow "Flag as error" dbl_ovrd off use_behavioral_HDL on hw_selection "Fabric" pipelined off xl_use_area off xl_area "[0, 0, 0, 0, 0, 0, 0]" use_rpm "on" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "addsub" block_version "VER_STRING_GOES_HERE" sg_icon_stat "45,44,2,1,white,blue,0,e139daf6,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 44 44 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 45 45 0 0 ],[0 0 44 44 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[28.66 28.66 3" "4.66 28.66 34.66 34.66 34.66 28.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[22.66 22.66 28.66 28.66 22" ".66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[16.66 16.66 22.66 22.66 16.66 ],[1 1 1 ]);\npa" "tch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[10.66 10.66 16.66 10.66 16.66 16.66 10.66 ],[0.931 0.946 0.973 ])" ";\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('" "input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('output',1,'\\bf{a + b}','tex" "mode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Constant\nRead State" SID "448" Ports [0, 1] Position [415, 338, 435, 352] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "0" gui_display_data_type "Fixed-point" arith_type "Boolean" n_bits "1" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" block_version "VER_STRING_GOES_HERE" sg_icon_stat "20,14,0,1,white,blue,0,bf4ddd8b,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 20 20 0 0 ],[0 0 14 14 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 20 20 0 0 ],[0 0 14 14 0 ]);\npatch([5.55 8.44 10.44 12.44 14.44 10.44 7.55 5.55 ],[9.22 9.22 11.22" " 9.22 11.22 11.22 11.22 9.22 ],[1 1 1 ]);\npatch([7.55 10.44 8.44 5.55 7.55 ],[7.22 7.22 9.22 9.22 7.22 ],[0.931 0" ".946 0.973 ]);\npatch([5.55 8.44 10.44 7.55 5.55 ],[5.22 5.22 7.22 7.22 5.22 ],[1 1 1 ]);\npatch([7.55 14.44 12.44" " 10.44 8.44 5.55 7.55 ],[3.22 3.22 5.22 3.22 5.22 5.22 3.22 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end ico" "n graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'0');\nfprintf('','CO" "MMENT: end icon text');" } Block { BlockType Reference Name "Constant\nRead State1" SID "9831" Ports [0, 1] Position [400, 708, 420, 722] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "0" gui_display_data_type "Fixed-point" arith_type "Boolean" n_bits "1" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" block_version "VER_STRING_GOES_HERE" sg_icon_stat "20,14,0,1,white,blue,0,bf4ddd8b,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 20 20 0 0 ],[0 0 14 14 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 20 20 0 0 ],[0 0 14 14 0 ]);\npatch([5.55 8.44 10.44 12.44 14.44 10.44 7.55 5.55 ],[9.22 9.22 11.22" " 9.22 11.22 11.22 11.22 9.22 ],[1 1 1 ]);\npatch([7.55 10.44 8.44 5.55 7.55 ],[7.22 7.22 9.22 9.22 7.22 ],[0.931 0" ".946 0.973 ]);\npatch([5.55 8.44 10.44 7.55 5.55 ],[5.22 5.22 7.22 7.22 5.22 ],[1 1 1 ]);\npatch([7.55 14.44 12.44" " 10.44 8.44 5.55 7.55 ],[3.22 3.22 5.22 3.22 5.22 5.22 3.22 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end ico" "n graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'0');\nfprintf('','CO" "MMENT: end icon text');" } Block { BlockType Reference Name "Constant1" SID "9832" Ports [0, 1] Position [400, 688, 420, 702] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "0" gui_display_data_type "Fixed-point" arith_type "Signed (2's comp)" n_bits "18" bin_pt "15" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" block_version "VER_STRING_GOES_HERE" sg_icon_stat "20,14,0,1,white,blue,0,bf4ddd8b,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 20 20 0 0 ],[0 0 14 14 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 20 20 0 0 ],[0 0 14 14 0 ]);\npatch([5.55 8.44 10.44 12.44 14.44 10.44 7.55 5.55 ],[9.22 9.22 11.22" " 9.22 11.22 11.22 11.22 9.22 ],[1 1 1 ]);\npatch([7.55 10.44 8.44 5.55 7.55 ],[7.22 7.22 9.22 9.22 7.22 ],[0.931 0" ".946 0.973 ]);\npatch([5.55 8.44 10.44 7.55 5.55 ],[5.22 5.22 7.22 7.22 5.22 ],[1 1 1 ]);\npatch([7.55 14.44 12.44" " 10.44 8.44 5.55 7.55 ],[3.22 3.22 5.22 3.22 5.22 5.22 3.22 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end ico" "n graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'0');\nfprintf('','CO" "MMENT: end icon text');" } Block { BlockType Reference Name "Constant4" SID "449" Ports [0, 1] Position [415, 318, 435, 332] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "0" gui_display_data_type "Fixed-point" arith_type "Signed (2's comp)" n_bits "18" bin_pt "15" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" block_version "VER_STRING_GOES_HERE" sg_icon_stat "20,14,0,1,white,blue,0,bf4ddd8b,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 20 20 0 0 ],[0 0 14 14 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 20 20 0 0 ],[0 0 14 14 0 ]);\npatch([5.55 8.44 10.44 12.44 14.44 10.44 7.55 5.55 ],[9.22 9.22 11.22" " 9.22 11.22 11.22 11.22 9.22 ],[1 1 1 ]);\npatch([7.55 10.44 8.44 5.55 7.55 ],[7.22 7.22 9.22 9.22 7.22 ],[0.931 0" ".946 0.973 ]);\npatch([5.55 8.44 10.44 7.55 5.55 ],[5.22 5.22 7.22 7.22 5.22 ],[1 1 1 ]);\npatch([7.55 14.44 12.44" " 10.44 8.44 5.55 7.55 ],[3.22 3.22 5.22 3.22 5.22 5.22 3.22 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end ico" "n graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'0');\nfprintf('','CO" "MMENT: end icon text');" } Block { BlockType Reference Name "Convert1" SID "450" Ports [1, 1] Position [510, 155, 555, 185] BlockMirror on ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do not." gui_display_data_type "Fixed-point" arith_type "Signed (2's comp)" n_bits "18" bin_pt "15" float_type "Single" exp_bits "8" fraction_bits "24" quantization "Truncate" overflow "Flag as error" en off latency "0" dbl_ovrd off pipeline off xl_use_area off xl_area "[0, 0, 0, 0, 0, 0, 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "convert" block_version "VER_STRING_GOES_HERE" sg_icon_stat "45,30,1,1,white,blue,0,edca21da,left,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 30 30 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 45 45 0 0 ],[0 0 30 30 0 ]);\npatch([13.1 18.88 22.88 26.88 30.88 22.88 17.1 13.1 ],[19.44 19.44 23" ".44 19.44 23.44 23.44 23.44 19.44 ],[1 1 1 ]);\npatch([17.1 22.88 18.88 13.1 17.1 ],[15.44 15.44 19.44 19.44 15.44" " ],[0.931 0.946 0.973 ]);\npatch([13.1 18.88 22.88 17.1 13.1 ],[11.44 11.44 15.44 15.44 11.44 ],[1 1 1 ]);\npatch(" "[17.1 30.88 26.88 22.88 18.88 13.1 17.1 ],[7.44 7.44 11.44 7.44 11.44 11.44 7.44 ],[0.931 0.946 0.973 ]);\nfprintf" "('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('output'," "1,'cast');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Convert3" SID "451" Ports [1, 1] Position [685, 255, 730, 285] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do not." gui_display_data_type "Fixed-point" arith_type "Signed (2's comp)" n_bits "17" bin_pt "15" float_type "Single" exp_bits "8" fraction_bits "24" quantization "Truncate" overflow "Flag as error" en off latency "0" dbl_ovrd off pipeline off xl_use_area off xl_area "[0, 0, 0, 0, 0, 0, 0]" has_advanced_control "0" sggui_pos "20,20,374,366" block_type "convert" block_version "VER_STRING_GOES_HERE" sg_icon_stat "45,30,1,1,white,blue,0,edca21da,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 30 30 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 45 45 0 0 ],[0 0 30 30 0 ]);\npatch([13.1 18.88 22.88 26.88 30.88 22.88 17.1 13.1 ],[19.44 19.44 23" ".44 19.44 23.44 23.44 23.44 19.44 ],[1 1 1 ]);\npatch([17.1 22.88 18.88 13.1 17.1 ],[15.44 15.44 19.44 19.44 15.44" " ],[0.931 0.946 0.973 ]);\npatch([13.1 18.88 22.88 17.1 13.1 ],[11.44 11.44 15.44 15.44 11.44 ],[1 1 1 ]);\npatch(" "[17.1 30.88 26.88 22.88 18.88 13.1 17.1 ],[7.44 7.44 11.44 7.44 11.44 11.44 7.44 ],[0.931 0.946 0.973 ]);\nfprintf" "('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('output'," "1,'cast');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Convert4" SID "9833" Ports [1, 1] Position [495, 525, 540, 555] BlockMirror on ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do not." gui_display_data_type "Fixed-point" arith_type "Signed (2's comp)" n_bits "18" bin_pt "15" float_type "Single" exp_bits "8" fraction_bits "24" quantization "Truncate" overflow "Flag as error" en off latency "0" dbl_ovrd off pipeline off xl_use_area off xl_area "[0, 0, 0, 0, 0, 0, 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "convert" block_version "VER_STRING_GOES_HERE" sg_icon_stat "45,30,1,1,white,blue,0,edca21da,left,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 30 30 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 45 45 0 0 ],[0 0 30 30 0 ]);\npatch([13.1 18.88 22.88 26.88 30.88 22.88 17.1 13.1 ],[19.44 19.44 23" ".44 19.44 23.44 23.44 23.44 19.44 ],[1 1 1 ]);\npatch([17.1 22.88 18.88 13.1 17.1 ],[15.44 15.44 19.44 19.44 15.44" " ],[0.931 0.946 0.973 ]);\npatch([13.1 18.88 22.88 17.1 13.1 ],[11.44 11.44 15.44 15.44 11.44 ],[1 1 1 ]);\npatch(" "[17.1 30.88 26.88 22.88 18.88 13.1 17.1 ],[7.44 7.44 11.44 7.44 11.44 11.44 7.44 ],[0.931 0.946 0.973 ]);\nfprintf" "('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('output'," "1,'cast');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Convert6" SID "9879" Ports [1, 1] Position [685, 625, 730, 655] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do not." gui_display_data_type "Fixed-point" arith_type "Signed (2's comp)" n_bits "17" bin_pt "15" float_type "Single" exp_bits "8" fraction_bits "24" quantization "Truncate" overflow "Flag as error" en off latency "0" dbl_ovrd off pipeline off xl_use_area off xl_area "[0, 0, 0, 0, 0, 0, 0]" has_advanced_control "0" sggui_pos "20,20,374,366" block_type "convert" block_version "VER_STRING_GOES_HERE" sg_icon_stat "45,30,1,1,white,blue,0,edca21da,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 30 30 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 45 45 0 0 ],[0 0 30 30 0 ]);\npatch([13.1 18.88 22.88 26.88 30.88 22.88 17.1 13.1 ],[19.44 19.44 23" ".44 19.44 23.44 23.44 23.44 19.44 ],[1 1 1 ]);\npatch([17.1 22.88 18.88 13.1 17.1 ],[15.44 15.44 19.44 19.44 15.44" " ],[0.931 0.946 0.973 ]);\npatch([13.1 18.88 22.88 17.1 13.1 ],[11.44 11.44 15.44 15.44 11.44 ],[1 1 1 ]);\npatch(" "[17.1 30.88 26.88 22.88 18.88 13.1 17.1 ],[7.44 7.44 11.44 7.44 11.44 11.44 7.44 ],[0.931 0.946 0.973 ]);\nfprintf" "('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('output'," "1,'cast');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Delay1" SID "9732" Ports [1, 1] Position [515, 436, 535, 454] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flop. If r" "egister retiming is enabled, the delay line is a chain of flip-flops." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en off latency "1" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[0, 0, 0, 0, 0, 0, 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" block_version "VER_STRING_GOES_HERE" sg_icon_stat "20,18,1,1,white,blue,0,07b98262,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 20 20 0 0 ],[0 0 18 18 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 20 20 0 0 ],[0 0 18 18 0 ]);\npatch([5.55 8.44 10.44 12.44 14.44 10.44 7.55 5.55 ],[11.22 11.22 13." "22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([7.55 10.44 8.44 5.55 7.55 ],[9.22 9.22 11.22 11.22 9.22 ],[0" ".931 0.946 0.973 ]);\npatch([5.55 8.44 10.44 7.55 5.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);\npatch([7.55 14.44" " 12.44 10.44 8.44 5.55 7.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: e" "nd icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');disp('z^{-1}','texmode','on');\nf" "printf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Delay10" SID "11308" Ports [1, 1] Position [1225, 203, 1260, 237] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flop." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en off latency "3" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" sg_icon_stat "35,34,1,1,white,blue,0,83e6bb61,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 34 34 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 35 35 0 0 ],[0 0 34 34 0 ]);\npatch([8.1 13.88 17.88 21.88 25.88 17.88 12.1 8.1 ],[21.44 21.44 25.4" "4 21.44 25.44 25.44 25.44 21.44 ],[1 1 1 ]);\npatch([12.1 17.88 13.88 8.1 12.1 ],[17.44 17.44 21.44 21.44 17.44 ]," "[0.931 0.946 0.973 ]);\npatch([8.1 13.88 17.88 12.1 8.1 ],[13.44 13.44 17.44 17.44 13.44 ],[1 1 1 ]);\npatch([12.1" " 25.88 21.88 17.88 13.88 8.1 12.1 ],[9.44 9.44 13.44 9.44 13.44 13.44 9.44 ],[0.931 0.946 0.973 ]);\nfprintf('','C" "OMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');disp('z^{-3}','texmode'," "'on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Delay11" SID "11309" Ports [1, 1] Position [1230, 728, 1265, 762] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flop." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en off latency "3" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" sg_icon_stat "35,34,1,1,white,blue,0,83e6bb61,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 34 34 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 35 35 0 0 ],[0 0 34 34 0 ]);\npatch([8.1 13.88 17.88 21.88 25.88 17.88 12.1 8.1 ],[21.44 21.44 25.4" "4 21.44 25.44 25.44 25.44 21.44 ],[1 1 1 ]);\npatch([12.1 17.88 13.88 8.1 12.1 ],[17.44 17.44 21.44 21.44 17.44 ]," "[0.931 0.946 0.973 ]);\npatch([8.1 13.88 17.88 12.1 8.1 ],[13.44 13.44 17.44 17.44 13.44 ],[1 1 1 ]);\npatch([12.1" " 25.88 21.88 17.88 13.88 8.1 12.1 ],[9.44 9.44 13.44 9.44 13.44 13.44 9.44 ],[0.931 0.946 0.973 ]);\nfprintf('','C" "OMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');disp('z^{-3}','texmode'," "'on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Delay2" SID "9917" Ports [1, 1] Position [895, 401, 915, 419] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flop. If r" "egister retiming is enabled, the delay line is a chain of flip-flops." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en off latency "1" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[0, 0, 0, 0, 0, 0, 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" block_version "VER_STRING_GOES_HERE" sg_icon_stat "20,18,1,1,white,blue,0,07b98262,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 20 20 0 0 ],[0 0 18 18 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 20 20 0 0 ],[0 0 18 18 0 ]);\npatch([5.55 8.44 10.44 12.44 14.44 10.44 7.55 5.55 ],[11.22 11.22 13." "22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([7.55 10.44 8.44 5.55 7.55 ],[9.22 9.22 11.22 11.22 9.22 ],[0" ".931 0.946 0.973 ]);\npatch([5.55 8.44 10.44 7.55 5.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);\npatch([7.55 14.44" " 12.44 10.44 8.44 5.55 7.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: e" "nd icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');disp('z^{-1}','texmode','on');\nf" "printf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Delay3" SID "452" Ports [1, 1] Position [340, 276, 360, 294] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flop. If r" "egister retiming is enabled, the delay line is a chain of flip-flops." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en off latency "1" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[0, 0, 0, 0, 0, 0, 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" block_version "VER_STRING_GOES_HERE" sg_icon_stat "20,18,1,1,white,blue,0,07b98262,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 20 20 0 0 ],[0 0 18 18 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 20 20 0 0 ],[0 0 18 18 0 ]);\npatch([5.55 8.44 10.44 12.44 14.44 10.44 7.55 5.55 ],[11.22 11.22 13." "22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([7.55 10.44 8.44 5.55 7.55 ],[9.22 9.22 11.22 11.22 9.22 ],[0" ".931 0.946 0.973 ]);\npatch([5.55 8.44 10.44 7.55 5.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);\npatch([7.55 14.44" " 12.44 10.44 8.44 5.55 7.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: e" "nd icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');disp('z^{-1}','texmode','on');\nf" "printf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Delay4" SID "9837" Ports [1, 1] Position [325, 646, 345, 664] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flop. If r" "egister retiming is enabled, the delay line is a chain of flip-flops." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en off latency "1" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[0, 0, 0, 0, 0, 0, 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" block_version "VER_STRING_GOES_HERE" sg_icon_stat "20,18,1,1,white,blue,0,07b98262,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 20 20 0 0 ],[0 0 18 18 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 20 20 0 0 ],[0 0 18 18 0 ]);\npatch([5.55 8.44 10.44 12.44 14.44 10.44 7.55 5.55 ],[11.22 11.22 13." "22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([7.55 10.44 8.44 5.55 7.55 ],[9.22 9.22 11.22 11.22 9.22 ],[0" ".931 0.946 0.973 ]);\npatch([5.55 8.44 10.44 7.55 5.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);\npatch([7.55 14.44" " 12.44 10.44 8.44 5.55 7.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: e" "nd icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');disp('z^{-1}','texmode','on');\nf" "printf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Delay5" SID "9838" Ports [1, 1] Position [325, 606, 345, 624] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flop. If r" "egister retiming is enabled, the delay line is a chain of flip-flops." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en off latency "1" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[0, 0, 0, 0, 0, 0, 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" block_version "VER_STRING_GOES_HERE" sg_icon_stat "20,18,1,1,white,blue,0,07b98262,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 20 20 0 0 ],[0 0 18 18 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 20 20 0 0 ],[0 0 18 18 0 ]);\npatch([5.55 8.44 10.44 12.44 14.44 10.44 7.55 5.55 ],[11.22 11.22 13." "22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([7.55 10.44 8.44 5.55 7.55 ],[9.22 9.22 11.22 11.22 9.22 ],[0" ".931 0.946 0.973 ]);\npatch([5.55 8.44 10.44 7.55 5.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);\npatch([7.55 14.44" " 12.44 10.44 8.44 5.55 7.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: e" "nd icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');disp('z^{-1}','texmode','on');\nf" "printf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Delay6" SID "453" Ports [1, 1] Position [340, 236, 360, 254] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flop. If r" "egister retiming is enabled, the delay line is a chain of flip-flops." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en off latency "1" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[0, 0, 0, 0, 0, 0, 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" block_version "VER_STRING_GOES_HERE" sg_icon_stat "20,18,1,1,white,blue,0,07b98262,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 20 20 0 0 ],[0 0 18 18 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 20 20 0 0 ],[0 0 18 18 0 ]);\npatch([5.55 8.44 10.44 12.44 14.44 10.44 7.55 5.55 ],[11.22 11.22 13." "22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([7.55 10.44 8.44 5.55 7.55 ],[9.22 9.22 11.22 11.22 9.22 ],[0" ".931 0.946 0.973 ]);\npatch([5.55 8.44 10.44 7.55 5.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);\npatch([7.55 14.44" " 12.44 10.44 8.44 5.55 7.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: e" "nd icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');disp('z^{-1}','texmode','on');\nf" "printf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Delay7" SID "454" Ports [1, 1] Position [340, 216, 360, 234] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flop. If r" "egister retiming is enabled, the delay line is a chain of flip-flops." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en off latency "1" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[0, 0, 0, 0, 0, 0, 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" block_version "VER_STRING_GOES_HERE" sg_icon_stat "20,18,1,1,white,blue,0,07b98262,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 20 20 0 0 ],[0 0 18 18 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 20 20 0 0 ],[0 0 18 18 0 ]);\npatch([5.55 8.44 10.44 12.44 14.44 10.44 7.55 5.55 ],[11.22 11.22 13." "22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([7.55 10.44 8.44 5.55 7.55 ],[9.22 9.22 11.22 11.22 9.22 ],[0" ".931 0.946 0.973 ]);\npatch([5.55 8.44 10.44 7.55 5.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);\npatch([7.55 14.44" " 12.44 10.44 8.44 5.55 7.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: e" "nd icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');disp('z^{-1}','texmode','on');\nf" "printf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Delay8" SID "9839" Ports [1, 1] Position [325, 586, 345, 604] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flop. If r" "egister retiming is enabled, the delay line is a chain of flip-flops." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en off latency "1" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[0, 0, 0, 0, 0, 0, 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" block_version "VER_STRING_GOES_HERE" sg_icon_stat "20,18,1,1,white,blue,0,07b98262,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 20 20 0 0 ],[0 0 18 18 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 20 20 0 0 ],[0 0 18 18 0 ]);\npatch([5.55 8.44 10.44 12.44 14.44 10.44 7.55 5.55 ],[11.22 11.22 13." "22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([7.55 10.44 8.44 5.55 7.55 ],[9.22 9.22 11.22 11.22 9.22 ],[0" ".931 0.946 0.973 ]);\npatch([5.55 8.44 10.44 7.55 5.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);\npatch([7.55 14.44" " 12.44 10.44 8.44 5.55 7.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: e" "nd icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');disp('z^{-1}','texmode','on');\nf" "printf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Delay9" SID "9919" Ports [1, 1] Position [895, 436, 915, 454] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flop. If r" "egister retiming is enabled, the delay line is a chain of flip-flops." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en off latency "1" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[0, 0, 0, 0, 0, 0, 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" block_version "VER_STRING_GOES_HERE" sg_icon_stat "20,18,1,1,white,blue,0,07b98262,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 20 20 0 0 ],[0 0 18 18 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 20 20 0 0 ],[0 0 18 18 0 ]);\npatch([5.55 8.44 10.44 12.44 14.44 10.44 7.55 5.55 ],[11.22 11.22 13." "22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([7.55 10.44 8.44 5.55 7.55 ],[9.22 9.22 11.22 11.22 9.22 ],[0" ".931 0.946 0.973 ]);\npatch([5.55 8.44 10.44 7.55 5.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);\npatch([7.55 14.44" " 12.44 10.44 8.44 5.55 7.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: e" "nd icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');disp('z^{-1}','texmode','on');\nf" "printf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Dual Port RAM" SID "455" Ports [7, 2] Position [500, 233, 570, 377] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Dual Port RAM" SourceType "Xilinx Dual Port Random Access Memory Block" depth "MAX_NUM_SC" initVector "0" distributed_mem "Block RAM" init_a "0" init_b "0" rst_a off rst_b on en_a off en_b off latency "1" write_mode_A "Read After Write" write_mode_B "Read After Write" dbl_ovrd off optimize "Area" xl_use_area off xl_area "[0, 0, 0, 0, 0, 0, 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "dpram" block_version "VER_STRING_GOES_HERE" sg_icon_stat "70,144,7,2,white,blue,0,7d88b3c1,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 70 70 0 0 ],[0 0 144 144 0 ],[0.77 0.82 0" ".91 ]);\nplot([0 70 70 0 0 ],[0 0 144 144 0 ]);\npatch([12.75 27.2 37.2 47.2 57.2 37.2 22.75 12.75 ],[83.1 83.1 93" ".1 83.1 93.1 93.1 93.1 83.1 ],[1 1 1 ]);\npatch([22.75 37.2 27.2 12.75 22.75 ],[73.1 73.1 83.1 83.1 73.1 ],[0.931 " "0.946 0.973 ]);\npatch([12.75 27.2 37.2 22.75 12.75 ],[63.1 63.1 73.1 73.1 63.1 ],[1 1 1 ]);\npatch([22.75 57.2 47" ".2 37.2 27.2 12.75 22.75 ],[53.1 53.1 63.1 53.1 63.1 63.1 53.1 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end " "icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'addra');\ncolor('b" "lack');port_label('input',2,'dina');\ncolor('black');port_label('input',3,'wea');\ncolor('black');port_label('inpu" "t',4,'addrb');\ncolor('black');port_label('input',5,'dinb');\ncolor('black');port_label('input',6,'web');\ncolor('" "black');port_label('input',7,'rstb');\ncolor('black');port_label('output',1,'A');\ncolor('black');port_label('outp" "ut',2,'B');\nfprintf('','COMMENT: end icon text');\n" } Block { BlockType Reference Name "Dual Port RAM1" SID "9840" Ports [7, 2] Position [485, 603, 555, 747] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Dual Port RAM" SourceType "Xilinx Dual Port Random Access Memory Block" depth "MAX_NUM_SC" initVector "0" distributed_mem "Block RAM" init_a "0" init_b "0" rst_a off rst_b on en_a off en_b off latency "1" write_mode_A "Read After Write" write_mode_B "Read After Write" dbl_ovrd off optimize "Area" xl_use_area off xl_area "[0, 0, 0, 0, 0, 0, 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "dpram" block_version "VER_STRING_GOES_HERE" sg_icon_stat "70,144,7,2,white,blue,0,7d88b3c1,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 70 70 0 0 ],[0 0 144 144 0 ],[0.77 0.82 0" ".91 ]);\nplot([0 70 70 0 0 ],[0 0 144 144 0 ]);\npatch([12.75 27.2 37.2 47.2 57.2 37.2 22.75 12.75 ],[83.1 83.1 93" ".1 83.1 93.1 93.1 93.1 83.1 ],[1 1 1 ]);\npatch([22.75 37.2 27.2 12.75 22.75 ],[73.1 73.1 83.1 83.1 73.1 ],[0.931 " "0.946 0.973 ]);\npatch([12.75 27.2 37.2 22.75 12.75 ],[63.1 63.1 73.1 73.1 63.1 ],[1 1 1 ]);\npatch([22.75 57.2 47" ".2 37.2 27.2 12.75 22.75 ],[53.1 53.1 63.1 53.1 63.1 63.1 53.1 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end " "icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'addra');\ncolor('b" "lack');port_label('input',2,'dina');\ncolor('black');port_label('input',3,'wea');\ncolor('black');port_label('inpu" "t',4,'addrb');\ncolor('black');port_label('input',5,'dinb');\ncolor('black');port_label('input',6,'web');\ncolor('" "black');port_label('input',7,'rstb');\ncolor('black');port_label('output',1,'A');\ncolor('black');port_label('outp" "ut',2,'B');\nfprintf('','COMMENT: end icon text');\n" } Block { BlockType Reference Name "Gateway Out1" SID "9896" Ports [1, 1] Position [1360, 379, 1395, 391] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type Sim" "ulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top level o" "utput ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0.88 0.8" "8 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[7.11 7.1" "1 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7.11 7.11 6.11 " "],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]);\npatch(" "[15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.964 ]);\nfpri" "ntf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input'," "1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf('','COMMENT: end i" "con text');" Port { PortNumber 1 Name "A" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out2" SID "9897" Ports [1, 1] Position [1360, 404, 1395, 416] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type Sim" "ulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top level o" "utput ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0.88 0.8" "8 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[7.11 7.1" "1 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7.11 7.11 6.11 " "],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]);\npatch(" "[15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.964 ]);\nfpri" "ntf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input'," "1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf('','COMMENT: end i" "con text');" Port { PortNumber 1 Name "B" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out3" SID "9908" Ports [1, 1] Position [1140, 829, 1175, 841] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type Sim" "ulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top level o" "utput ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0.88 0.8" "8 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[7.11 7.1" "1 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7.11 7.11 6.11 " "],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]);\npatch(" "[15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.964 ]);\nfpri" "ntf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input'," "1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf('','COMMENT: end i" "con text');" } Block { BlockType Reference Name "Gateway Out4" SID "9910" Ports [1, 1] Position [1140, 874, 1175, 886] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type Sim" "ulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top level o" "utput ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0.88 0.8" "8 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[7.11 7.1" "1 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7.11 7.11 6.11 " "],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]);\npatch(" "[15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.964 ]);\nfpri" "ntf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input'," "1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf('','COMMENT: end i" "con text');" } Block { BlockType Reference Name "Gateway Out6" SID "9902" Ports [1, 1] Position [1360, 504, 1395, 516] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type Sim" "ulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top level o" "utput ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0.88 0.8" "8 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[7.11 7.1" "1 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7.11 7.11 6.11 " "],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]);\npatch(" "[15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.964 ]);\nfpri" "ntf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input'," "1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf('','COMMENT: end i" "con text');" Port { PortNumber 1 Name "H Out" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out7" SID "9906" Ports [1, 1] Position [1360, 529, 1395, 541] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type Sim" "ulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top level o" "utput ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0.88 0.8" "8 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[7.11 7.1" "1 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7.11 7.11 6.11 " "],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]);\npatch(" "[15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.964 ]);\nfpri" "ntf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input'," "1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf('','COMMENT: end i" "con text');" Port { PortNumber 1 Name "Next Empty Sc" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out8" SID "9894" Ports [1, 1] Position [1360, 354, 1395, 366] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type Sim" "ulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top level o" "utput ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0.88 0.8" "8 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[7.11 7.1" "1 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7.11 7.11 6.11 " "],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]);\npatch(" "[15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.964 ]);\nfpri" "ntf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input'," "1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf('','COMMENT: end i" "con text');" Port { PortNumber 1 Name "H" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Mux1" SID "9841" Ports [3, 1] Position [980, 572, 1005, 708] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Mux" SourceType "Xilinx Bus Multiplexer Block" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "14" quantization "Truncate" overflow "Wrap" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "mux" sg_icon_stat "25,136,3,1,white,blue,3,eb98d690,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 19.4286 116.571 136 0 ],[0" ".77 0.82 0.91 ]);\nplot([0 25 25 0 0 ],[0 19.4286 116.571 136 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.3" "25 5.325 ],[71.33 71.33 74.33 71.33 74.33 74.33 74.33 71.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[6" "8.33 68.33 71.33 71.33 68.33 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[65.33 65.33 68.33 68" ".33 65.33 ],[1 1 1 ]);\npatch([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[62.33 62.33 65.33 62.33 65.33 65.33 62." "33 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\nc" "olor('black');port_label('input',1,'sel');\ncolor('black');port_label('input',2,'d0');\ncolor('black');port_label(" "'input',3,'d1');\n\ncolor('black');disp('\\bf{}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Mux2" SID "465" Ports [3, 1] Position [980, 202, 1005, 338] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Mux" SourceType "Xilinx Bus Multiplexer Block" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "14" quantization "Truncate" overflow "Wrap" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "mux" sg_icon_stat "25,136,3,1,white,blue,3,eb98d690,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 19.4286 116.571 136 0 ],[0" ".77 0.82 0.91 ]);\nplot([0 25 25 0 0 ],[0 19.4286 116.571 136 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.3" "25 5.325 ],[71.33 71.33 74.33 71.33 74.33 74.33 74.33 71.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[6" "8.33 68.33 71.33 71.33 68.33 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[65.33 65.33 68.33 68" ".33 65.33 ],[1 1 1 ]);\npatch([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[62.33 62.33 65.33 62.33 65.33 65.33 62." "33 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\nc" "olor('black');port_label('input',1,'sel');\ncolor('black');port_label('input',2,'d0');\ncolor('black');port_label(" "'input',3,'d1');\n\ncolor('black');disp('\\bf{}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register" SID "9916" Ports [2, 1] Position [1085, 260, 1125, 295] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst on en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "40,35,2,1,white,blue,0,140cc11c,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 35 35 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 40 40 0 0 ],[0 0 35 35 0 ]);\npatch([8.875 16.1 21.1 26.1 31.1 21.1 13.875 8.875 ],[22.55 22.55 27." "55 22.55 27.55 27.55 27.55 22.55 ],[1 1 1 ]);\npatch([13.875 21.1 16.1 8.875 13.875 ],[17.55 17.55 22.55 22.55 17." "55 ],[0.931 0.946 0.973 ]);\npatch([8.875 16.1 21.1 13.875 8.875 ],[12.55 12.55 17.55 17.55 12.55 ],[1 1 1 ]);\npa" "tch([13.875 31.1 26.1 21.1 16.1 8.875 13.875 ],[7.55 7.55 12.55 7.55 12.55 12.55 7.55 ],[0.931 0.946 0.973 ]);\nfp" "rintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input" "',1,'d');\ncolor('black');port_label('input',2,'rst');\ncolor('black');port_label('output',1,'q');\ncolor('black')" ";disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register1" SID "9918" Ports [2, 1] Position [1090, 630, 1130, 665] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst on en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "40,35,2,1,white,blue,0,140cc11c,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 35 35 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 40 40 0 0 ],[0 0 35 35 0 ]);\npatch([8.875 16.1 21.1 26.1 31.1 21.1 13.875 8.875 ],[22.55 22.55 27." "55 22.55 27.55 27.55 27.55 22.55 ],[1 1 1 ]);\npatch([13.875 21.1 16.1 8.875 13.875 ],[17.55 17.55 22.55 22.55 17." "55 ],[0.931 0.946 0.973 ]);\npatch([8.875 16.1 21.1 13.875 8.875 ],[12.55 12.55 17.55 17.55 12.55 ],[1 1 1 ]);\npa" "tch([13.875 31.1 26.1 21.1 16.1 8.875 13.875 ],[7.55 7.55 12.55 7.55 12.55 12.55 7.55 ],[0.931 0.946 0.973 ]);\nfp" "rintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input" "',1,'d');\ncolor('black');port_label('input',2,'rst');\ncolor('black');port_label('output',1,'q');\ncolor('black')" ";disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType SubSystem Name "Smoothing Coef" SID "9863" Ports [1, 2] Position [935, 426, 1005, 464] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "Smoothing Coef" Location [61, 101, 2373, 1521] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "156" Block { BlockType Inport Name "Next Empty" SID "9864" Position [315, 188, 345, 202] NamePlacement "alternate" IconDisplay "Port number" } Block { BlockType Reference Name "AddSub1" SID "9815" Ports [2, 1] Position [480, 288, 525, 332] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/AddSub" SourceType "Xilinx Adder/Subtracter Block" mode "Addition" use_carryin off use_carryout off en off latency "1" precision "User Defined" arith_type "Unsigned" n_bits "12" bin_pt "12" quantization "Truncate" overflow "Flag as error" dbl_ovrd off use_behavioral_HDL on hw_selection "Fabric" pipelined off xl_use_area off xl_area "[0, 0, 0, 0, 0, 0, 0]" use_rpm "on" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "addsub" block_version "VER_STRING_GOES_HERE" sg_icon_stat "45,44,2,1,white,blue,0,e85d8a90,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 44 44 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 45 45 0 0 ],[0 0 44 44 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[28.66 2" "8.66 34.66 28.66 34.66 34.66 34.66 28.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[22.66 22.66 28.66 " "28.66 22.66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[16.66 16.66 22.66 22.66 16.66 ],[1 1" " 1 ]);\npatch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[10.66 10.66 16.66 10.66 16.66 16.66 10.66 ],[0.931 0." "946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black'" ");port_label('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('output',1,'\\" "bf{a + b}','texmode','on');\ncolor('black');disp('z^{-1}\\newline ','texmode','on');\ncolor('black');disp(' \\ne" "wline\\bf{}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Delay3" SID "9726" Ports [1, 1] Position [420, 183, 450, 207] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flop." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en off latency "2" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" sg_icon_stat "30,24,1,1,white,blue,0,85ce9542,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 24 24 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 24 24 0 ]);\npatch([8.325 12.66 15.66 18.66 21.66 15.66 11.325 8.325 ],[15.3" "3 15.33 18.33 15.33 18.33 18.33 18.33 15.33 ],[1 1 1 ]);\npatch([11.325 15.66 12.66 8.325 11.325 ],[12.33 12.33 " "15.33 15.33 12.33 ],[0.931 0.946 0.973 ]);\npatch([8.325 12.66 15.66 11.325 8.325 ],[9.33 9.33 12.33 12.33 9.33 " "],[1 1 1 ]);\npatch([11.325 21.66 18.66 15.66 12.66 8.325 11.325 ],[6.33 6.33 9.33 6.33 9.33 9.33 6.33 ],[0.931 " "0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('" "black');disp('z^{-2}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Display Name "Display" SID "9811" Ports [1] Position [680, 403, 775, 427] ZOrder -1 ShowName off Decimation "1" Lockdown off } Block { BlockType Display Name "Display1" SID "9813" Ports [1] Position [680, 433, 775, 457] ZOrder -1 ShowName off Decimation "1" Lockdown off } Block { BlockType Display Name "Display2" SID "9892" Ports [1] Position [680, 468, 775, 492] ZOrder -1 ShowName off Decimation "1" Lockdown off } Block { BlockType From Name "From" SID "9808" Position [145, 344, 325, 366] ZOrder -9 ShowName off GotoTag "regRx_Chan_Est_Smoothing_B" TagVisibility "global" } Block { BlockType From Name "From1" SID "9809" Position [145, 239, 325, 261] ZOrder -9 ShowName off GotoTag "regRx_Chan_Est_Smoothing_A" TagVisibility "global" } Block { BlockType Reference Name "Gateway Out1" SID "9814" Ports [1, 1] Position [600, 439, 635, 451] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type" " Simulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top l" "evel output ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[7." "11 7.11 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7.11 7." "11 6.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out2" SID "9893" Ports [1, 1] Position [600, 474, 635, 486] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type" " Simulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top l" "evel output ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[7." "11 7.11 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7.11 7." "11 6.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out8" SID "9812" Ports [1, 1] Position [600, 409, 635, 421] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type" " Simulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top l" "evel output ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[7." "11 7.11 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7.11 7." "11 6.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" } Block { BlockType Reference Name "Logical" SID "9727" Ports [2, 1] Position [495, 173, 525, 202] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "OR" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" sg_icon_stat "30,29,2,1,white,blue,0,7ede7d88,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 29 29 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 29 29 0 ]);\npatch([6.1 11.88 15.88 19.88 23.88 15.88 10.1 6.1 ],[18.44 18.4" "4 22.44 18.44 22.44 22.44 22.44 18.44 ],[1 1 1 ]);\npatch([10.1 15.88 11.88 6.1 10.1 ],[14.44 14.44 18.44 18.44 " "14.44 ],[0.931 0.946 0.973 ]);\npatch([6.1 11.88 15.88 10.1 6.1 ],[10.44 10.44 14.44 14.44 10.44 ],[1 1 1 ]);\np" "atch([10.1 23.88 19.88 15.88 11.88 6.1 10.1 ],[6.44 6.44 10.44 6.44 10.44 10.44 6.44 ],[0.931 0.946 0.973 ]);\nf" "printf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\ncolor('black');disp('or" "');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Mux" SID "9730" Ports [3, 1] Position [590, 163, 615, 337] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Mux" SourceType "Xilinx Bus Multiplexer Block" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "14" quantization "Truncate" overflow "Wrap" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "mux" sg_icon_stat "25,174,3,1,white,blue,3,eb98d690,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 24.8571 149.143 174 0 " "],[0.77 0.82 0.91 ]);\nplot([0 25 25 0 0 ],[0 24.8571 149.143 174 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12." "66 8.325 5.325 ],[90.33 90.33 93.33 90.33 93.33 93.33 93.33 90.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8." "325 ],[87.33 87.33 90.33 90.33 87.33 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[84.33 84.3" "3 87.33 87.33 84.33 ],[1 1 1 ]);\npatch([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[81.33 81.33 84.33 81.33 84." "33 84.33 81.33 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin i" "con text');\ncolor('black');port_label('input',1,'sel');\ncolor('black');port_label('input',2,'d0');\ncolor('bla" "ck');port_label('input',3,'d1');\n\ncolor('black');disp('\\bf{}','texmode','on');\nfprintf('','COMMENT: end icon" " text');" } Block { BlockType Outport Name "A" SID "9865" Position [725, 243, 755, 257] IconDisplay "Port number" } Block { BlockType Outport Name "B" SID "9866" Position [725, 348, 755, 362] Port "2" IconDisplay "Port number" } Line { SrcBlock "From" SrcPort 1 Points [20, 0] Branch { Points [210, 0] Branch { DstBlock "B" DstPort 1 } Branch { Points [0, 125] DstBlock "Gateway Out2" DstPort 1 } } Branch { Points [0, -35] DstBlock "AddSub1" DstPort 2 } } Line { SrcBlock "Next Empty" SrcPort 1 Points [50, 0] Branch { DstBlock "Delay3" DstPort 1 } Branch { Points [0, -15] DstBlock "Logical" DstPort 1 } } Line { SrcBlock "From1" SrcPort 1 Points [20, 0] Branch { Points [0, 50] DstBlock "AddSub1" DstPort 1 } Branch { Points [220, 0] Branch { DstBlock "Mux" DstPort 2 } Branch { Points [0, 165] DstBlock "Gateway Out8" DstPort 1 } } } Line { SrcBlock "Delay3" SrcPort 1 DstBlock "Logical" DstPort 2 } Line { SrcBlock "Logical" SrcPort 1 DstBlock "Mux" DstPort 1 } Line { SrcBlock "Gateway Out8" SrcPort 1 DstBlock "Display" DstPort 1 } Line { SrcBlock "Gateway Out1" SrcPort 1 DstBlock "Display1" DstPort 1 } Line { SrcBlock "Mux" SrcPort 1 DstBlock "A" DstPort 1 } Line { SrcBlock "Gateway Out2" SrcPort 1 DstBlock "Display2" DstPort 1 } Line { SrcBlock "AddSub1" SrcPort 1 Points [35, 0] Branch { DstBlock "Mux" DstPort 3 } Branch { Points [0, 135] DstBlock "Gateway Out1" DstPort 1 } } Annotation { Name "Increase A coefficient to (A+B) when next or previous subcarrier is empty" Position [588, 143] } } } Block { BlockType SubSystem Name "Smoothing I" SID "9716" Ports [3, 1] Position [1195, 271, 1295, 329] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "Smoothing I" Location [2, 70, 2469, 1580] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "153" Block { BlockType Inport Name "H" SID "9717" Position [225, 288, 255, 302] NamePlacement "alternate" IconDisplay "Port number" } Block { BlockType Inport Name "A" SID "9718" Position [225, 313, 255, 327] Port "2" IconDisplay "Port number" } Block { BlockType Inport Name "B" SID "9867" Position [225, 373, 255, 387] Port "3" IconDisplay "Port number" } Block { BlockType Reference Name "AddSub1" SID "9721" Ports [2, 1] Position [705, 298, 750, 342] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/AddSub" SourceType "Xilinx Adder/Subtracter Block" mode "Addition" use_carryin off use_carryout off en off latency "0" precision "User Defined" arith_type "Signed (2's comp)" n_bits "18" bin_pt "16" quantization "Truncate" overflow "Flag as error" dbl_ovrd off use_behavioral_HDL on hw_selection "Fabric" pipelined off xl_use_area off xl_area "[0, 0, 0, 0, 0, 0, 0]" use_rpm "on" has_advanced_control "0" sggui_pos "20,27,348,319" block_type "addsub" block_version "VER_STRING_GOES_HERE" sg_icon_stat "45,44,2,1,white,blue,0,e139daf6,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 44 44 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 45 45 0 0 ],[0 0 44 44 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[28.66 2" "8.66 34.66 28.66 34.66 34.66 34.66 28.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[22.66 22.66 28.66 " "28.66 22.66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[16.66 16.66 22.66 22.66 16.66 ],[1 1" " 1 ]);\npatch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[10.66 10.66 16.66 10.66 16.66 16.66 10.66 ],[0.931 0." "946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black'" ");port_label('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('output',1,'\\" "bf{a + b}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "AddSub3" SID "9722" Ports [2, 1] Position [600, 338, 645, 382] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/AddSub" SourceType "Xilinx Adder/Subtracter Block" mode "Addition" use_carryin off use_carryout off en off latency "1" precision "User Defined" arith_type "Signed (2's comp)" n_bits "18" bin_pt "16" quantization "Truncate" overflow "Flag as error" dbl_ovrd off use_behavioral_HDL on hw_selection "Fabric" pipelined off xl_use_area off xl_area "[0, 0, 0, 0, 0, 0, 0]" use_rpm "on" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "addsub" block_version "VER_STRING_GOES_HERE" sg_icon_stat "45,44,2,1,white,blue,0,e85d8a90,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 44 44 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 45 45 0 0 ],[0 0 44 44 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[28.66 2" "8.66 34.66 28.66 34.66 34.66 34.66 28.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[22.66 22.66 28.66 " "28.66 22.66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[16.66 16.66 22.66 22.66 16.66 ],[1 1" " 1 ]);\npatch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[10.66 10.66 16.66 10.66 16.66 16.66 10.66 ],[0.931 0." "946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black'" ");port_label('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('output',1,'\\" "bf{a + b}','texmode','on');\ncolor('black');disp('z^{-1}\\newline ','texmode','on');\ncolor('black');disp(' \\ne" "wline\\bf{}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Delay1" SID "9724" Ports [1, 1] Position [495, 293, 530, 327] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flop." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en off latency "1" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" sg_icon_stat "35,34,1,1,white,blue,0,07b98262,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 34 34 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 34 34 0 ]);\npatch([8.1 13.88 17.88 21.88 25.88 17.88 12.1 8.1 ],[21.44 21.4" "4 25.44 21.44 25.44 25.44 25.44 21.44 ],[1 1 1 ]);\npatch([12.1 17.88 13.88 8.1 12.1 ],[17.44 17.44 21.44 21.44 " "17.44 ],[0.931 0.946 0.973 ]);\npatch([8.1 13.88 17.88 12.1 8.1 ],[13.44 13.44 17.44 17.44 13.44 ],[1 1 1 ]);\np" "atch([12.1 25.88 21.88 17.88 13.88 8.1 12.1 ],[9.44 9.44 13.44 9.44 13.44 13.44 9.44 ],[0.931 0.946 0.973 ]);\nf" "printf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');disp('z^{-" "1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Delay2" SID "9725" Ports [1, 1] Position [495, 333, 530, 367] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flop." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en off latency "2" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" sg_icon_stat "35,34,1,1,white,blue,0,85ce9542,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 34 34 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 34 34 0 ]);\npatch([8.1 13.88 17.88 21.88 25.88 17.88 12.1 8.1 ],[21.44 21.4" "4 25.44 21.44 25.44 25.44 25.44 21.44 ],[1 1 1 ]);\npatch([12.1 17.88 13.88 8.1 12.1 ],[17.44 17.44 21.44 21.44 " "17.44 ],[0.931 0.946 0.973 ]);\npatch([8.1 13.88 17.88 12.1 8.1 ],[13.44 13.44 17.44 17.44 13.44 ],[1 1 1 ]);\np" "atch([12.1 25.88 21.88 17.88 13.88 8.1 12.1 ],[9.44 9.44 13.44 9.44 13.44 13.44 9.44 ],[0.931 0.946 0.973 ]);\nf" "printf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');disp('z^{-" "2}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out1" SID "9915" Ports [1, 1] Position [665, 514, 700, 526] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type" " Simulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top l" "evel output ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[7." "11 7.11 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7.11 7." "11 6.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "A" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out2" SID "9914" Ports [1, 1] Position [665, 539, 700, 551] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type" " Simulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top l" "evel output ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[7." "11 7.11 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7.11 7." "11 6.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "B" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out3" SID "9898" Ports [1, 1] Position [665, 564, 700, 576] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type" " Simulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top l" "evel output ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[7." "11 7.11 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7.11 7." "11 6.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "Sum 1" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out4" SID "9899" Ports [1, 1] Position [665, 589, 700, 601] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type" " Simulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top l" "evel output ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[7." "11 7.11 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7.11 7." "11 6.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "Sum 2" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out5" SID "9901" Ports [1, 1] Position [665, 614, 700, 626] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type" " Simulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top l" "evel output ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[7." "11 7.11 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7.11 7." "11 6.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "Sum 3" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out6" SID "9913" Ports [1, 1] Position [665, 639, 700, 651] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type" " Simulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top l" "evel output ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[7." "11 7.11 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7.11 7." "11 6.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "H Out" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out8" SID "9912" Ports [1, 1] Position [665, 489, 700, 501] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type" " Simulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top l" "evel output ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[7." "11 7.11 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7.11 7." "11 6.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "H" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Mult" SID "9728" Ports [2, 1] Position [375, 283, 425, 332] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Mult" SourceType "Xilinx Multiplier Block" infoedit "Hardware notes: To check for the optimum internal pipeline stages of the dedicated multiplier you" " must select 'Test for optimum pipelining'.

Optimization Goal: For implementation into device fabric (LUT" "s), the Speed or Area optimization will take effect only if it's supported by IP for the particular device famil" "y. Otherwise, the results will be identical regardless of the selection." precision "User Defined" arith_type "Signed (2's comp)" n_bits "18" bin_pt "16" quantization "Truncate" overflow "Wrap" en off latency "1" dbl_ovrd off use_behavioral_HDL off opt "Speed" use_embedded on optimum_pipeline off xl_use_area off xl_area "[0,0,0,0,0,0,0]" pipeline "on" use_rpm "on" placement_style "Triangular" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "mult" sg_icon_stat "50,49,2,1,white,blue,0,82c891c1,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 50 50 0 0 ],[0 0 49 49 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 50 50 0 0 ],[0 0 49 49 0 ]);\npatch([9.425 19.54 26.54 33.54 40.54 26.54 16.425 9.425 ],[31.7" "7 31.77 38.77 31.77 38.77 38.77 38.77 31.77 ],[1 1 1 ]);\npatch([16.425 26.54 19.54 9.425 16.425 ],[24.77 24.77 " "31.77 31.77 24.77 ],[0.931 0.946 0.973 ]);\npatch([9.425 19.54 26.54 16.425 9.425 ],[17.77 17.77 24.77 24.77 17." "77 ],[1 1 1 ]);\npatch([16.425 40.54 33.54 26.54 19.54 9.425 16.425 ],[10.77 10.77 17.77 10.77 17.77 17.77 10.77" " ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\nc" "olor('black');port_label('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('" "output',1,'\\bfa \\times b','texmode','on');\ncolor('black');disp('z^{-1}\\newline ','texmode','on');\ncolor('bl" "ack');disp(' \\n ');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Mult1" SID "9880" Ports [2, 1] Position [375, 343, 425, 392] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Mult" SourceType "Xilinx Multiplier Block" infoedit "Hardware notes: To check for the optimum internal pipeline stages of the dedicated multiplier you" " must select 'Test for optimum pipelining'.

Optimization Goal: For implementation into device fabric (LUT" "s), the Speed or Area optimization will take effect only if it's supported by IP for the particular device famil" "y. Otherwise, the results will be identical regardless of the selection." precision "User Defined" arith_type "Signed (2's comp)" n_bits "18" bin_pt "16" quantization "Truncate" overflow "Wrap" en off latency "1" dbl_ovrd off use_behavioral_HDL off opt "Speed" use_embedded on optimum_pipeline off xl_use_area off xl_area "[0,0,0,0,0,0,0]" pipeline "on" use_rpm "on" placement_style "Triangular" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "mult" sg_icon_stat "50,49,2,1,white,blue,0,82c891c1,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 50 50 0 0 ],[0 0 49 49 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 50 50 0 0 ],[0 0 49 49 0 ]);\npatch([9.425 19.54 26.54 33.54 40.54 26.54 16.425 9.425 ],[31.7" "7 31.77 38.77 31.77 38.77 38.77 38.77 31.77 ],[1 1 1 ]);\npatch([16.425 26.54 19.54 9.425 16.425 ],[24.77 24.77 " "31.77 31.77 24.77 ],[0.931 0.946 0.973 ]);\npatch([9.425 19.54 26.54 16.425 9.425 ],[17.77 17.77 24.77 24.77 17." "77 ],[1 1 1 ]);\npatch([16.425 40.54 33.54 26.54 19.54 9.425 16.425 ],[10.77 10.77 17.77 10.77 17.77 17.77 10.77" " ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\nc" "olor('black');port_label('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('" "output',1,'\\bfa \\times b','texmode','on');\ncolor('black');disp('z^{-1}\\newline ','texmode','on');\ncolor('bl" "ack');disp(' \\n ');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register" SID "9924" Ports [1, 1] Position [605, 297, 635, 323] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "30,26,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 26 26 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 26 26 0 ]);\npatch([8.325 12.66 15.66 18.66 21.66 15.66 11.325 8.325 ],[16.3" "3 16.33 19.33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([11.325 15.66 12.66 8.325 11.325 ],[13.33 13.33 " "16.33 16.33 13.33 ],[0.931 0.946 0.973 ]);\npatch([8.325 12.66 15.66 11.325 8.325 ],[10.33 10.33 13.33 13.33 10." "33 ],[1 1 1 ]);\npatch([11.325 21.66 18.66 15.66 12.66 8.325 11.325 ],[7.33 7.33 10.33 7.33 10.33 10.33 7.33 ],[" "0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor" "('black');port_label('input',1,'d');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','" "texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Scope Name "Smoothing I" SID "9911" Ports [9] Position [855, 490, 890, 700] ZOrder -3 Floating off Location [6, 202, 1686, 1206] Open off NumInputPorts "9" ZoomMode "xonly" List { ListType AxesTitles axes1 "%" axes2 "%" axes3 "%" axes4 "%" axes5 "%" axes6 "%" axes7 "%" axes8 "%" axes9 "%" } List { ListType ScopeGraphics FigureColor "[0.5 0.5 0.5]" AxesColor "[0 0 0]" AxesTickColor "[1 1 1]" LineColors "[1 1 0;1 0 1;0 1 1;1 0 0;0 1 0;0 0 1]" LineStyles "-|-|-|-|-|-" LineWidths "[0.5 0.5 0.5 0.5 0.5 0.5]" MarkerStyles "none|none|none|none|none|none" } TimeRange "772.0815318097584" YMin "-0.5~-0.6~-0.5~-0.5~0~0~0~0~0" YMax "0.7~0.5~0.5~0.5~70~3~1~0.5~0.7" SaveName "ScopeData7" DataFormat "StructureWithTime" LimitDataPoints off SampleTime "0" } Block { BlockType Outport Name "H-sm" SID "9731" Position [805, 313, 835, 327] IconDisplay "Port number" } Line { SrcBlock "H" SrcPort 1 Points [90, 0] Branch { DstBlock "Mult" DstPort 1 } Branch { Points [0, 60] Branch { DstBlock "Mult1" DstPort 1 } Branch { Points [0, 140] DstBlock "Gateway Out8" DstPort 1 } } } Line { SrcBlock "Mult1" SrcPort 1 Points [35, 0] Branch { Points [0, -20] DstBlock "Delay2" DstPort 1 } Branch { Points [95, 0] Branch { DstBlock "AddSub3" DstPort 2 } Branch { Points [0, 250] DstBlock "Gateway Out5" DstPort 1 } } } Line { SrcBlock "Delay2" SrcPort 1 Points [30, 0] Branch { DstBlock "AddSub3" DstPort 1 } Branch { Points [0, 245] DstBlock "Gateway Out4" DstPort 1 } } Line { SrcBlock "Mult" SrcPort 1 DstBlock "Delay1" DstPort 1 } Line { SrcBlock "AddSub3" SrcPort 1 Points [20, 0; 0, -30] DstBlock "AddSub1" DstPort 2 } Line { SrcBlock "AddSub1" SrcPort 1 Points [20, 0] Branch { DstBlock "H-sm" DstPort 1 } Branch { Points [0, 150; -155, 0; 0, 175] DstBlock "Gateway Out6" DstPort 1 } } Line { SrcBlock "Delay1" SrcPort 1 Points [35, 0] Branch { Points [0, 260] DstBlock "Gateway Out3" DstPort 1 } Branch { DstBlock "Register" DstPort 1 } } Line { SrcBlock "A" SrcPort 1 Points [85, 0] Branch { DstBlock "Mult" DstPort 2 } Branch { Points [0, 200] DstBlock "Gateway Out1" DstPort 1 } } Line { SrcBlock "B" SrcPort 1 Points [80, 0] Branch { DstBlock "Mult1" DstPort 2 } Branch { Points [0, 165] DstBlock "Gateway Out2" DstPort 1 } } Line { Name "H" Labels [0, 0] SrcBlock "Gateway Out8" SrcPort 1 DstBlock "Smoothing I" DstPort 1 } Line { Name "A" Labels [0, 0] SrcBlock "Gateway Out1" SrcPort 1 DstBlock "Smoothing I" DstPort 2 } Line { Name "B" Labels [0, 0] SrcBlock "Gateway Out2" SrcPort 1 DstBlock "Smoothing I" DstPort 3 } Line { Name "Sum 1" Labels [0, 0] SrcBlock "Gateway Out3" SrcPort 1 DstBlock "Smoothing I" DstPort 4 } Line { Name "Sum 2" Labels [0, 0] SrcBlock "Gateway Out4" SrcPort 1 DstBlock "Smoothing I" DstPort 5 } Line { Name "Sum 3" Labels [0, 0] SrcBlock "Gateway Out5" SrcPort 1 DstBlock "Smoothing I" DstPort 6 } Line { Name "H Out" Labels [0, 0] SrcBlock "Gateway Out6" SrcPort 1 DstBlock "Smoothing I" DstPort 7 } Line { SrcBlock "Register" SrcPort 1 DstBlock "AddSub1" DstPort 1 } Annotation { Name "S(n-1) = AH(n-1) + BH(n) + BH(n-2)" Position [452, 238] } } } Block { BlockType Scope Name "Smoothing I1" SID "9895" Ports [9] Position [1550, 355, 1585, 565] ZOrder -3 Floating off Location [1, 45, 2472, 1599] Open off NumInputPorts "9" ZoomMode "xonly" List { ListType AxesTitles axes1 "%" axes2 "%" axes3 "%" axes4 "%" axes5 "%" axes6 "%" axes7 "%" axes8 "%" axes9 "%" } List { ListType ScopeGraphics FigureColor "[0.5 0.5 0.5]" AxesColor "[0 0 0]" AxesTickColor "[1 1 1]" LineColors "[1 1 0;1 0 1;0 1 1;1 0 0;0 1 0;0 0 1]" LineStyles "-|-|-|-|-|-" LineWidths "[0.5 0.5 0.5 0.5 0.5 0.5]" MarkerStyles "none|none|none|none|none|none" } TimeRange "772.0815318097584" YMin "-0.5~-0.6~-0.5~-0.5~0~0~0~0~0" YMax "0.7~0.5~0.5~0.5~70~3~1~0.5~0.7" SaveName "ScopeData7" DataFormat "StructureWithTime" LimitDataPoints off SampleTime "0" } Block { BlockType SubSystem Name "Smoothing Q" SID "9930" Ports [3, 1] Position [1200, 641, 1300, 699] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "Smoothing Q" Location [2, 70, 2469, 1580] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "153" Block { BlockType Inport Name "H" SID "9931" Position [225, 288, 255, 302] NamePlacement "alternate" IconDisplay "Port number" } Block { BlockType Inport Name "A" SID "9932" Position [225, 313, 255, 327] Port "2" IconDisplay "Port number" } Block { BlockType Inport Name "B" SID "9933" Position [225, 373, 255, 387] Port "3" IconDisplay "Port number" } Block { BlockType Reference Name "AddSub1" SID "9934" Ports [2, 1] Position [705, 298, 750, 342] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/AddSub" SourceType "Xilinx Adder/Subtracter Block" mode "Addition" use_carryin off use_carryout off en off latency "0" precision "User Defined" arith_type "Signed (2's comp)" n_bits "18" bin_pt "16" quantization "Truncate" overflow "Flag as error" dbl_ovrd off use_behavioral_HDL on hw_selection "Fabric" pipelined off xl_use_area off xl_area "[0, 0, 0, 0, 0, 0, 0]" use_rpm "on" has_advanced_control "0" sggui_pos "20,27,348,319" block_type "addsub" block_version "VER_STRING_GOES_HERE" sg_icon_stat "45,44,2,1,white,blue,0,e139daf6,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 44 44 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 45 45 0 0 ],[0 0 44 44 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[28.66 2" "8.66 34.66 28.66 34.66 34.66 34.66 28.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[22.66 22.66 28.66 " "28.66 22.66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[16.66 16.66 22.66 22.66 16.66 ],[1 1" " 1 ]);\npatch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[10.66 10.66 16.66 10.66 16.66 16.66 10.66 ],[0.931 0." "946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black'" ");port_label('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('output',1,'\\" "bf{a + b}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "AddSub3" SID "9935" Ports [2, 1] Position [600, 338, 645, 382] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/AddSub" SourceType "Xilinx Adder/Subtracter Block" mode "Addition" use_carryin off use_carryout off en off latency "1" precision "User Defined" arith_type "Signed (2's comp)" n_bits "18" bin_pt "16" quantization "Truncate" overflow "Flag as error" dbl_ovrd off use_behavioral_HDL on hw_selection "Fabric" pipelined off xl_use_area off xl_area "[0, 0, 0, 0, 0, 0, 0]" use_rpm "on" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "addsub" block_version "VER_STRING_GOES_HERE" sg_icon_stat "45,44,2,1,white,blue,0,e85d8a90,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 44 44 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 45 45 0 0 ],[0 0 44 44 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[28.66 2" "8.66 34.66 28.66 34.66 34.66 34.66 28.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[22.66 22.66 28.66 " "28.66 22.66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[16.66 16.66 22.66 22.66 16.66 ],[1 1" " 1 ]);\npatch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[10.66 10.66 16.66 10.66 16.66 16.66 10.66 ],[0.931 0." "946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black'" ");port_label('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('output',1,'\\" "bf{a + b}','texmode','on');\ncolor('black');disp('z^{-1}\\newline ','texmode','on');\ncolor('black');disp(' \\ne" "wline\\bf{}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Delay1" SID "9936" Ports [1, 1] Position [495, 293, 530, 327] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flop." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en off latency "1" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" sg_icon_stat "35,34,1,1,white,blue,0,07b98262,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 34 34 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 34 34 0 ]);\npatch([8.1 13.88 17.88 21.88 25.88 17.88 12.1 8.1 ],[21.44 21.4" "4 25.44 21.44 25.44 25.44 25.44 21.44 ],[1 1 1 ]);\npatch([12.1 17.88 13.88 8.1 12.1 ],[17.44 17.44 21.44 21.44 " "17.44 ],[0.931 0.946 0.973 ]);\npatch([8.1 13.88 17.88 12.1 8.1 ],[13.44 13.44 17.44 17.44 13.44 ],[1 1 1 ]);\np" "atch([12.1 25.88 21.88 17.88 13.88 8.1 12.1 ],[9.44 9.44 13.44 9.44 13.44 13.44 9.44 ],[0.931 0.946 0.973 ]);\nf" "printf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');disp('z^{-" "1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Delay2" SID "9937" Ports [1, 1] Position [495, 333, 530, 367] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flop." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en off latency "2" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" sg_icon_stat "35,34,1,1,white,blue,0,85ce9542,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 34 34 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 34 34 0 ]);\npatch([8.1 13.88 17.88 21.88 25.88 17.88 12.1 8.1 ],[21.44 21.4" "4 25.44 21.44 25.44 25.44 25.44 21.44 ],[1 1 1 ]);\npatch([12.1 17.88 13.88 8.1 12.1 ],[17.44 17.44 21.44 21.44 " "17.44 ],[0.931 0.946 0.973 ]);\npatch([8.1 13.88 17.88 12.1 8.1 ],[13.44 13.44 17.44 17.44 13.44 ],[1 1 1 ]);\np" "atch([12.1 25.88 21.88 17.88 13.88 8.1 12.1 ],[9.44 9.44 13.44 9.44 13.44 13.44 9.44 ],[0.931 0.946 0.973 ]);\nf" "printf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');disp('z^{-" "2}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out1" SID "9938" Ports [1, 1] Position [665, 514, 700, 526] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type" " Simulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top l" "evel output ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[7." "11 7.11 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7.11 7." "11 6.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "A" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out2" SID "9939" Ports [1, 1] Position [665, 539, 700, 551] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type" " Simulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top l" "evel output ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[7." "11 7.11 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7.11 7." "11 6.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "B" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out3" SID "9940" Ports [1, 1] Position [665, 564, 700, 576] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type" " Simulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top l" "evel output ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[7." "11 7.11 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7.11 7." "11 6.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "Sum 1" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out4" SID "9941" Ports [1, 1] Position [665, 589, 700, 601] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type" " Simulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top l" "evel output ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[7." "11 7.11 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7.11 7." "11 6.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "Sum 2" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out5" SID "9942" Ports [1, 1] Position [665, 614, 700, 626] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type" " Simulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top l" "evel output ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[7." "11 7.11 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7.11 7." "11 6.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "Sum 3" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out6" SID "9943" Ports [1, 1] Position [665, 639, 700, 651] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type" " Simulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top l" "evel output ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[7." "11 7.11 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7.11 7." "11 6.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "H Out" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out8" SID "9944" Ports [1, 1] Position [665, 489, 700, 501] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type" " Simulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become top l" "evel output ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0.88" " 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ],[7." "11 7.11 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7.11 7." "11 6.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]" ");\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.9" "64 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf(''" ",'COMMENT: end icon text');" Port { PortNumber 1 Name "H" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Mult" SID "9945" Ports [2, 1] Position [375, 283, 425, 332] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Mult" SourceType "Xilinx Multiplier Block" infoedit "Hardware notes: To check for the optimum internal pipeline stages of the dedicated multiplier you" " must select 'Test for optimum pipelining'.

Optimization Goal: For implementation into device fabric (LUT" "s), the Speed or Area optimization will take effect only if it's supported by IP for the particular device famil" "y. Otherwise, the results will be identical regardless of the selection." precision "User Defined" arith_type "Signed (2's comp)" n_bits "18" bin_pt "16" quantization "Truncate" overflow "Wrap" en off latency "1" dbl_ovrd off use_behavioral_HDL off opt "Speed" use_embedded on optimum_pipeline off xl_use_area off xl_area "[0,0,0,0,0,0,0]" pipeline "on" use_rpm "on" placement_style "Triangular" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "mult" sg_icon_stat "50,49,2,1,white,blue,0,82c891c1,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 50 50 0 0 ],[0 0 49 49 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 50 50 0 0 ],[0 0 49 49 0 ]);\npatch([9.425 19.54 26.54 33.54 40.54 26.54 16.425 9.425 ],[31.7" "7 31.77 38.77 31.77 38.77 38.77 38.77 31.77 ],[1 1 1 ]);\npatch([16.425 26.54 19.54 9.425 16.425 ],[24.77 24.77 " "31.77 31.77 24.77 ],[0.931 0.946 0.973 ]);\npatch([9.425 19.54 26.54 16.425 9.425 ],[17.77 17.77 24.77 24.77 17." "77 ],[1 1 1 ]);\npatch([16.425 40.54 33.54 26.54 19.54 9.425 16.425 ],[10.77 10.77 17.77 10.77 17.77 17.77 10.77" " ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\nc" "olor('black');port_label('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('" "output',1,'\\bfa \\times b','texmode','on');\ncolor('black');disp('z^{-1}\\newline ','texmode','on');\ncolor('bl" "ack');disp(' \\n ');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Mult1" SID "9946" Ports [2, 1] Position [375, 343, 425, 392] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Mult" SourceType "Xilinx Multiplier Block" infoedit "Hardware notes: To check for the optimum internal pipeline stages of the dedicated multiplier you" " must select 'Test for optimum pipelining'.

Optimization Goal: For implementation into device fabric (LUT" "s), the Speed or Area optimization will take effect only if it's supported by IP for the particular device famil" "y. Otherwise, the results will be identical regardless of the selection." precision "User Defined" arith_type "Signed (2's comp)" n_bits "18" bin_pt "16" quantization "Truncate" overflow "Wrap" en off latency "1" dbl_ovrd off use_behavioral_HDL off opt "Speed" use_embedded on optimum_pipeline off xl_use_area off xl_area "[0,0,0,0,0,0,0]" pipeline "on" use_rpm "on" placement_style "Triangular" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "mult" sg_icon_stat "50,49,2,1,white,blue,0,82c891c1,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 50 50 0 0 ],[0 0 49 49 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 50 50 0 0 ],[0 0 49 49 0 ]);\npatch([9.425 19.54 26.54 33.54 40.54 26.54 16.425 9.425 ],[31.7" "7 31.77 38.77 31.77 38.77 38.77 38.77 31.77 ],[1 1 1 ]);\npatch([16.425 26.54 19.54 9.425 16.425 ],[24.77 24.77 " "31.77 31.77 24.77 ],[0.931 0.946 0.973 ]);\npatch([9.425 19.54 26.54 16.425 9.425 ],[17.77 17.77 24.77 24.77 17." "77 ],[1 1 1 ]);\npatch([16.425 40.54 33.54 26.54 19.54 9.425 16.425 ],[10.77 10.77 17.77 10.77 17.77 17.77 10.77" " ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\nc" "olor('black');port_label('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('" "output',1,'\\bfa \\times b','texmode','on');\ncolor('black');disp('z^{-1}\\newline ','texmode','on');\ncolor('bl" "ack');disp(' \\n ');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register" SID "9947" Ports [1, 1] Position [605, 297, 635, 323] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "30,26,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 26 26 0 ],[0.77 0.82" " 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 26 26 0 ]);\npatch([8.325 12.66 15.66 18.66 21.66 15.66 11.325 8.325 ],[16.3" "3 16.33 19.33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([11.325 15.66 12.66 8.325 11.325 ],[13.33 13.33 " "16.33 16.33 13.33 ],[0.931 0.946 0.973 ]);\npatch([8.325 12.66 15.66 11.325 8.325 ],[10.33 10.33 13.33 13.33 10." "33 ],[1 1 1 ]);\npatch([11.325 21.66 18.66 15.66 12.66 8.325 11.325 ],[7.33 7.33 10.33 7.33 10.33 10.33 7.33 ],[" "0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor" "('black');port_label('input',1,'d');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','" "texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Scope Name "Smoothing I" SID "9948" Ports [9] Position [855, 490, 890, 700] ZOrder -3 Floating off Location [6, 202, 1686, 1206] Open off NumInputPorts "9" ZoomMode "xonly" List { ListType AxesTitles axes1 "%" axes2 "%" axes3 "%" axes4 "%" axes5 "%" axes6 "%" axes7 "%" axes8 "%" axes9 "%" } List { ListType ScopeGraphics FigureColor "[0.5 0.5 0.5]" AxesColor "[0 0 0]" AxesTickColor "[1 1 1]" LineColors "[1 1 0;1 0 1;0 1 1;1 0 0;0 1 0;0 0 1]" LineStyles "-|-|-|-|-|-" LineWidths "[0.5 0.5 0.5 0.5 0.5 0.5]" MarkerStyles "none|none|none|none|none|none" } TimeRange "772.0815318097584" YMin "-0.5~-0.6~-0.5~-0.5~0~0~0~0~0" YMax "0.7~0.5~0.5~0.5~70~3~1~0.5~0.7" SaveName "ScopeData7" DataFormat "StructureWithTime" LimitDataPoints off SampleTime "0" } Block { BlockType Outport Name "H-sm" SID "9949" Position [805, 313, 835, 327] IconDisplay "Port number" } Line { SrcBlock "Register" SrcPort 1 DstBlock "AddSub1" DstPort 1 } Line { Name "H Out" Labels [0, 0] SrcBlock "Gateway Out6" SrcPort 1 DstBlock "Smoothing I" DstPort 7 } Line { Name "Sum 3" Labels [0, 0] SrcBlock "Gateway Out5" SrcPort 1 DstBlock "Smoothing I" DstPort 6 } Line { Name "Sum 2" Labels [0, 0] SrcBlock "Gateway Out4" SrcPort 1 DstBlock "Smoothing I" DstPort 5 } Line { Name "Sum 1" Labels [0, 0] SrcBlock "Gateway Out3" SrcPort 1 DstBlock "Smoothing I" DstPort 4 } Line { Name "B" Labels [0, 0] SrcBlock "Gateway Out2" SrcPort 1 DstBlock "Smoothing I" DstPort 3 } Line { Name "A" Labels [0, 0] SrcBlock "Gateway Out1" SrcPort 1 DstBlock "Smoothing I" DstPort 2 } Line { Name "H" Labels [0, 0] SrcBlock "Gateway Out8" SrcPort 1 DstBlock "Smoothing I" DstPort 1 } Line { SrcBlock "B" SrcPort 1 Points [80, 0] Branch { Points [0, 165] DstBlock "Gateway Out2" DstPort 1 } Branch { DstBlock "Mult1" DstPort 2 } } Line { SrcBlock "A" SrcPort 1 Points [85, 0] Branch { Points [0, 200] DstBlock "Gateway Out1" DstPort 1 } Branch { DstBlock "Mult" DstPort 2 } } Line { SrcBlock "Delay1" SrcPort 1 Points [35, 0] Branch { DstBlock "Register" DstPort 1 } Branch { Points [0, 260] DstBlock "Gateway Out3" DstPort 1 } } Line { SrcBlock "AddSub1" SrcPort 1 Points [20, 0] Branch { Points [0, 150; -155, 0; 0, 175] DstBlock "Gateway Out6" DstPort 1 } Branch { DstBlock "H-sm" DstPort 1 } } Line { SrcBlock "AddSub3" SrcPort 1 Points [20, 0; 0, -30] DstBlock "AddSub1" DstPort 2 } Line { SrcBlock "Mult" SrcPort 1 DstBlock "Delay1" DstPort 1 } Line { SrcBlock "Delay2" SrcPort 1 Points [30, 0] Branch { Points [0, 245] DstBlock "Gateway Out4" DstPort 1 } Branch { DstBlock "AddSub3" DstPort 1 } } Line { SrcBlock "Mult1" SrcPort 1 Points [35, 0] Branch { Points [95, 0] Branch { Points [0, 250] DstBlock "Gateway Out5" DstPort 1 } Branch { DstBlock "AddSub3" DstPort 2 } } Branch { Points [0, -20] DstBlock "Delay2" DstPort 1 } } Line { SrcBlock "H" SrcPort 1 Points [90, 0] Branch { Points [0, 60] Branch { Points [0, 140] DstBlock "Gateway Out8" DstPort 1 } Branch { DstBlock "Mult1" DstPort 1 } } Branch { DstBlock "Mult" DstPort 1 } } Annotation { Name "S(n-1) = AH(n-1) + BH(n) + BH(n-2)" Position [452, 238] } } } Block { BlockType ToWorkspace Name "To Workspace" SID "9907" Ports [1] Position [1240, 825, 1415, 845] ZOrder -7 VariableName "h_est_smoothing_next_empty" MaxDataPoints "inf" SampleTime "-1" SaveFormat "Structure With Time" } Block { BlockType ToWorkspace Name "To Workspace1" SID "9909" Ports [1] Position [1240, 870, 1415, 890] ZOrder -7 VariableName "h_est_smoothing_H_I" MaxDataPoints "inf" SampleTime "-1" SaveFormat "Structure With Time" } Block { BlockType Reference Name "div_2" SID "466" Ports [1, 1] Position [900, 259, 930, 281] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Scale" SourceType "Xilinx Input Scaler Block" infoedit "Scales input by a power of two by adjusting the binary point position.

Hardware notes: In hard" "ware this block costs nothing." scale_factor "-1" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "scale" sg_icon_stat "30,22,1,1,white,blue,0,315b7d78,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 22 22 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 30 30 0 0 ],[0 0 22 22 0 ]);\npatch([8.325 12.66 15.66 18.66 21.66 15.66 11.325 8.325 ],[14.33 14.3" "3 17.33 14.33 17.33 17.33 17.33 14.33 ],[1 1 1 ]);\npatch([11.325 15.66 12.66 8.325 11.325 ],[11.33 11.33 14.33 14" ".33 11.33 ],[0.931 0.946 0.973 ]);\npatch([8.325 12.66 15.66 11.325 8.325 ],[8.33 8.33 11.33 11.33 8.33 ],[1 1 1 ]" ");\npatch([11.325 21.66 18.66 15.66 12.66 8.325 11.325 ],[5.33 5.33 8.33 5.33 8.33 8.33 5.33 ],[0.931 0.946 0.973 " "]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');disp('" "\\bf{2^{-1}}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "div_2 " SID "9861" Ports [1, 1] Position [900, 629, 930, 651] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Scale" SourceType "Xilinx Input Scaler Block" infoedit "Scales input by a power of two by adjusting the binary point position.

Hardware notes: In hard" "ware this block costs nothing." scale_factor "-1" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "scale" sg_icon_stat "30,22,1,1,white,blue,0,315b7d78,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 22 22 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 30 30 0 0 ],[0 0 22 22 0 ]);\npatch([8.325 12.66 15.66 18.66 21.66 15.66 11.325 8.325 ],[14.33 14.3" "3 17.33 14.33 17.33 17.33 17.33 14.33 ],[1 1 1 ]);\npatch([11.325 15.66 12.66 8.325 11.325 ],[11.33 11.33 14.33 14" ".33 11.33 ],[0.931 0.946 0.973 ]);\npatch([8.325 12.66 15.66 11.325 8.325 ],[8.33 8.33 11.33 11.33 8.33 ],[1 1 1 ]" ");\npatch([11.325 21.66 18.66 15.66 12.66 8.325 11.325 ],[5.33 5.33 8.33 5.33 8.33 8.33 5.33 ],[0.931 0.946 0.973 " "]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');disp('" "\\bf{2^{-1}}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Outport Name "h_I[n]" SID "467" Position [1365, 293, 1395, 307] IconDisplay "Port number" } Block { BlockType Outport Name "h_Q[n]" SID "9862" Position [1365, 663, 1395, 677] Port "2" IconDisplay "Port number" } Line { SrcBlock "Constant4" SrcPort 1 DstBlock "Dual Port RAM" DstPort 5 } Line { SrcBlock "Constant\nRead State" SrcPort 1 DstBlock "Dual Port RAM" DstPort 6 } Line { SrcBlock "AddSub2" SrcPort 1 Points [5, 0; 0, 50] DstBlock "Dual Port RAM" DstPort 2 } Line { SrcBlock "Convert1" SrcPort 1 Points [-115, 0] DstBlock "AddSub2" DstPort 1 } Line { SrcBlock "Delay6" SrcPort 1 DstBlock "Dual Port RAM" DstPort 1 } Line { SrcBlock "Delay3" SrcPort 1 DstBlock "Dual Port RAM" DstPort 3 } Line { SrcBlock "Delay7" SrcPort 1 DstBlock "AddSub2" DstPort 2 } Line { SrcBlock "Est_WE" SrcPort 1 Points [25, 0] Branch { DstBlock "Delay3" DstPort 1 } Branch { Points [0, 370] DstBlock "Delay4" DstPort 1 } } Line { SrcBlock "Est_Addr" SrcPort 1 Points [20, 0] Branch { Points [95, 0; 0, -15] Branch { Points [0, -60] DstBlock "Delay6" DstPort 1 } Branch { DstBlock "Dual Port RAM" DstPort 4 } } Branch { Points [0, 355; 95, 0] Branch { DstBlock "Dual Port RAM1" DstPort 4 } Branch { Points [0, -60] DstBlock "Delay5" DstPort 1 } } } Line { SrcBlock "First Sym" SrcPort 1 Points [15, 0] Branch { DstBlock "Dual Port RAM" DstPort 7 } Branch { Points [0, 370] DstBlock "Dual Port RAM1" DstPort 7 } } Line { SrcBlock "x_I" SrcPort 1 DstBlock "Delay7" DstPort 1 } Line { SrcBlock "Dual Port RAM" SrcPort 2 Points [40, 0; 0, -170] DstBlock "Convert1" DstPort 1 } Line { SrcBlock "Convert3" SrcPort 1 Points [135, 0] Branch { DstBlock "div_2" DstPort 1 } Branch { Points [0, 45] DstBlock "Mux2" DstPort 3 } } Line { SrcBlock "Dual Port RAM" SrcPort 1 DstBlock "Convert3" DstPort 1 } Line { SrcBlock "Scale" SrcPort 1 Points [10, 0] Branch { DstBlock "Mux2" DstPort 1 } Branch { Points [0, 370] DstBlock "Mux1" DstPort 1 } } Line { SrcBlock "div_2" SrcPort 1 DstBlock "Mux2" DstPort 2 } Line { SrcBlock "Mux2" SrcPort 1 Points [30, 0] Branch { Points [0, 90] Branch { DstBlock "Gateway Out8" DstPort 1 } Branch { Points [0, 520] DstBlock "Gateway Out4" DstPort 1 } } Branch { DstBlock "Register" DstPort 1 } } Line { SrcBlock "Empty Sc" SrcPort 1 DstBlock "Delay1" DstPort 1 } Line { SrcBlock "Smoothing I" SrcPort 1 Points [25, 0] Branch { Points [0, 210] DstBlock "Gateway Out6" DstPort 1 } Branch { DstBlock "h_I[n]" DstPort 1 } } Line { SrcBlock "div_2 " SrcPort 1 DstBlock "Mux1" DstPort 2 } Line { SrcBlock "Dual Port RAM1" SrcPort 1 DstBlock "Convert6" DstPort 1 } Line { SrcBlock "Convert6" SrcPort 1 Points [125, 0] Branch { Points [0, 45] DstBlock "Mux1" DstPort 3 } Branch { DstBlock "div_2 " DstPort 1 } } Line { SrcBlock "Dual Port RAM1" SrcPort 2 Points [40, 0; 0, -170] DstBlock "Convert4" DstPort 1 } Line { SrcBlock "x_Q" SrcPort 1 DstBlock "Delay8" DstPort 1 } Line { SrcBlock "Delay8" SrcPort 1 DstBlock "AddSub1" DstPort 2 } Line { SrcBlock "Delay4" SrcPort 1 DstBlock "Dual Port RAM1" DstPort 3 } Line { SrcBlock "Delay5" SrcPort 1 DstBlock "Dual Port RAM1" DstPort 1 } Line { SrcBlock "Convert4" SrcPort 1 Points [-115, 0] DstBlock "AddSub1" DstPort 1 } Line { SrcBlock "AddSub1" SrcPort 1 Points [0, 50] DstBlock "Dual Port RAM1" DstPort 2 } Line { SrcBlock "Constant\nRead State1" SrcPort 1 DstBlock "Dual Port RAM1" DstPort 6 } Line { SrcBlock "Constant1" SrcPort 1 DstBlock "Dual Port RAM1" DstPort 5 } Line { SrcBlock "Smoothing Q" SrcPort 1 DstBlock "h_Q[n]" DstPort 1 } Line { SrcBlock "Delay1" SrcPort 1 Points [330, 0] Branch { Points [0, 90] Branch { DstBlock "Gateway Out7" DstPort 1 } Branch { Points [0, 300] DstBlock "Gateway Out3" DstPort 1 } } Branch { Points [0, -35] DstBlock "Delay2" DstPort 1 } Branch { DstBlock "Delay9" DstPort 1 } } Line { SrcBlock "Smoothing Coef" SrcPort 1 Points [150, 0] Branch { Points [0, -50] Branch { Points [0, -85] DstBlock "Smoothing I" DstPort 2 } Branch { DstBlock "Gateway Out1" DstPort 1 } } Branch { Points [0, 235] DstBlock "Smoothing Q" DstPort 2 } } Line { SrcBlock "Smoothing Coef" SrcPort 2 Points [145, 0] Branch { Points [0, -45] Branch { Points [0, -90] DstBlock "Smoothing I" DstPort 3 } Branch { DstBlock "Gateway Out2" DstPort 1 } } Branch { Points [0, 235] DstBlock "Smoothing Q" DstPort 3 } } Line { Name "H" Labels [0, 0] SrcBlock "Gateway Out8" SrcPort 1 DstBlock "Smoothing I1" DstPort 1 } Line { Name "A" Labels [0, 0] SrcBlock "Gateway Out1" SrcPort 1 DstBlock "Smoothing I1" DstPort 2 } Line { Name "B" Labels [0, 0] SrcBlock "Gateway Out2" SrcPort 1 DstBlock "Smoothing I1" DstPort 3 } Line { Name "Sum 1" Labels [0, 0] Points [1400, 435] DstBlock "Smoothing I1" DstPort 4 } Line { Name "Sum 2" Labels [0, 0] Points [1400, 460] DstBlock "Smoothing I1" DstPort 5 } Line { Name "Sum 3" Labels [0, 0] Points [1400, 485] DstBlock "Smoothing I1" DstPort 6 } Line { Name "H Out" Labels [0, 0] SrcBlock "Gateway Out6" SrcPort 1 DstBlock "Smoothing I1" DstPort 7 } Line { Name "Next Empty Sc" Labels [0, 0] SrcBlock "Gateway Out7" SrcPort 1 DstBlock "Smoothing I1" DstPort 8 } Line { SrcBlock "Gateway Out3" SrcPort 1 DstBlock "To Workspace" DstPort 1 } Line { SrcBlock "Gateway Out4" SrcPort 1 DstBlock "To Workspace1" DstPort 1 } Line { SrcBlock "Register" SrcPort 1 Points [50, 0] Branch { Points [0, -60] DstBlock "Delay10" DstPort 1 } Branch { DstBlock "Smoothing I" DstPort 1 } } Line { SrcBlock "Delay2" SrcPort 1 Points [130, 0] Branch { Points [0, -125] DstBlock "Register" DstPort 2 } Branch { Points [0, 245] DstBlock "Register1" DstPort 2 } } Line { SrcBlock "Mux1" SrcPort 1 DstBlock "Register1" DstPort 1 } Line { SrcBlock "Register1" SrcPort 1 Points [45, 0] Branch { DstBlock "Smoothing Q" DstPort 1 } Branch { Points [0, 95] DstBlock "Delay11" DstPort 1 } } Line { SrcBlock "Delay9" SrcPort 1 DstBlock "Smoothing Coef" DstPort 1 } Annotation { Name "11a/g preamble has two L-LTF. Both generate estimates and are summed\nbefore the RAM. The sum must be di" "vided by 2 to properly scale\nthe H ests for the EQ.\n11n/ac have 1 HT-LTF for 1SS mode, so no scaling is required" "." Position [684, 144] HorizontalAlignment "left" } Annotation { Name "Delay by 1 less than buffer latency so smoothing\nlogic knows when \"next\" subcarrier is empty and \nca" "n adjust the smoothing coefficients accordingly." Position [530, 478] } } } Block { BlockType Reference Name "Gateway Out1" SID "433" Ports [1, 1] Position [1020, 559, 1055, 571] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of t" "ype Simulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become t" "op level output ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0" ".88 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ]" ",[7.11 7.11 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7." "11 7.11 6.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1" " 1 1 ]);\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0." "964 0.964 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black" "');port_label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nf" "printf('','COMMENT: end icon text');" Port { PortNumber 1 Name "x_Q" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out12" SID "10102" Ports [1, 1] Position [1140, 854, 1175, 866] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of t" "ype Simulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become t" "op level output ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0" ".88 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ]" ",[7.11 7.11 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7." "11 7.11 6.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1" " 1 1 ]);\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0." "964 0.964 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black" "');port_label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nf" "printf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out13" SID "10103" Ports [1, 1] Position [1140, 869, 1175, 881] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of t" "ype Simulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become t" "op level output ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0" ".88 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ]" ",[7.11 7.11 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7." "11 7.11 6.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1" " 1 1 ]);\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0." "964 0.964 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black" "');port_label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nf" "printf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out2" SID "434" Ports [1, 1] Position [1020, 584, 1055, 596] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of t" "ype Simulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become t" "op level output ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0" ".88 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ]" ",[7.11 7.11 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7." "11 7.11 6.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1" " 1 1 ]);\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0." "964 0.964 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black" "');port_label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nf" "printf('','COMMENT: end icon text');" Port { PortNumber 1 Name "H_I" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out3" SID "435" Ports [1, 1] Position [1020, 609, 1055, 621] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of t" "ype Simulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become t" "op level output ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0" ".88 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ]" ",[7.11 7.11 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7." "11 7.11 6.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1" " 1 1 ]);\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0." "964 0.964 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black" "');port_label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nf" "printf('','COMMENT: end icon text');" Port { PortNumber 1 Name "H_Q" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out4" SID "436" Ports [1, 1] Position [1020, 634, 1055, 646] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of t" "ype Simulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become t" "op level output ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0" ".88 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ]" ",[7.11 7.11 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7." "11 7.11 6.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1" " 1 1 ]);\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0." "964 0.964 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black" "');port_label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nf" "printf('','COMMENT: end icon text');" Port { PortNumber 1 Name "SC Ind" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out5" SID "437" Ports [1, 1] Position [1020, 684, 1055, 696] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of t" "ype Simulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become t" "op level output ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0" ".88 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ]" ",[7.11 7.11 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7." "11 7.11 6.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1" " 1 1 ]);\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0." "964 0.964 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black" "');port_label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nf" "printf('','COMMENT: end icon text');" Port { PortNumber 1 Name "Valid Out" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out6" SID "438" Ports [1, 1] Position [1020, 659, 1055, 671] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of t" "ype Simulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become t" "op level output ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0" ".88 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ]" ",[7.11 7.11 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7." "11 7.11 6.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1" " 1 1 ]);\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0." "964 0.964 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black" "');port_label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nf" "printf('','COMMENT: end icon text');" Port { PortNumber 1 Name "Sym Ind" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Gateway Out7" SID "10104" Ports [1, 1] Position [1140, 784, 1175, 796] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of t" "ype Simulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become t" "op level output ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0" ".88 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ]" ",[7.11 7.11 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7." "11 7.11 6.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1" " 1 1 ]);\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0." "964 0.964 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black" "');port_label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nf" "printf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out8" SID "439" Ports [1, 1] Position [1020, 534, 1055, 546] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of t" "ype Simulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become t" "op level output ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0" ".88 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ]" ",[7.11 7.11 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7." "11 7.11 6.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1" " 1 1 ]);\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0." "964 0.964 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black" "');port_label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nf" "printf('','COMMENT: end icon text');" Port { PortNumber 1 Name "x_I" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Scope Name "H Est Outputs" SID "440" Ports [9] Position [1210, 535, 1245, 745] ZOrder -3 Floating off Location [6, 40, 1841, 1194] Open off NumInputPorts "9" ZoomMode "xonly" List { ListType AxesTitles axes1 "%" axes2 "%" axes3 "%" axes4 "%" axes5 "%" axes6 "%" axes7 "%" axes8 "%" axes9 "%" } List { ListType ScopeGraphics FigureColor "[0.5 0.5 0.5]" AxesColor "[0 0 0]" AxesTickColor "[1 1 1]" LineColors "[1 1 0;1 0 1;0 1 1;1 0 0;0 1 0;0 0 1]" LineStyles "-|-|-|-|-|-" LineWidths "[0.5 0.5 0.5 0.5 0.5 0.5]" MarkerStyles "none|none|none|none|none|none" } TimeRange "50000" YMin "-1~-1~-0.5~-0.5~0~0~0~0~0" YMax "1~1~1~0.5~80~60~1~1~0.8" SaveName "ScopeData16" DataFormat "StructureWithTime" LimitDataPoints off SampleTime "0" } Block { BlockType Reference Name "Inverter" SID "468" Ports [1, 1] Position [420, 456, 455, 474] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Inverter" SourceType "Xilinx Inverter Block" infoedit "Bitwise logical negation (one's complement) operator." en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "inv" sg_icon_stat "35,18,1,1,white,blue,0,267846e5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 18 18 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 18 18 0 ]);\npatch([12.55 15.44 17.44 19.44 21.44 17.44 14.55 12.55 ],[1" "1.22 11.22 13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([14.55 17.44 15.44 12.55 14.55 ],[9.22 9.22 " "11.22 11.22 9.22 ],[0.931 0.946 0.973 ]);\npatch([12.55 15.44 17.44 14.55 12.55 ],[7.22 7.22 9.22 9.22 7.22 ],[" "1 1 1 ]);\npatch([14.55 21.44 19.44 17.44 15.44 12.55 14.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.94" "6 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('bla" "ck');disp('not');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Inverter1" SID "14909" Ports [1, 1] Position [655, 426, 690, 444] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Inverter" SourceType "Xilinx Inverter Block" infoedit "Bitwise logical negation (one's complement) operator." en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "inv" sg_icon_stat "35,18,1,1,white,blue,0,267846e5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 18 18 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 18 18 0 ]);\npatch([12.55 15.44 17.44 19.44 21.44 17.44 14.55 12.55 ],[1" "1.22 11.22 13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([14.55 17.44 15.44 12.55 14.55 ],[9.22 9.22 " "11.22 11.22 9.22 ],[0.931 0.946 0.973 ]);\npatch([12.55 15.44 17.44 14.55 12.55 ],[7.22 7.22 9.22 9.22 7.22 ],[" "1 1 1 ]);\npatch([14.55 21.44 19.44 17.44 15.44 12.55 14.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.94" "6 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('bla" "ck');disp('not');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical1" SID "469" Ports [2, 1] Position [490, 434, 530, 476] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "AND" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" sg_icon_stat "40,42,2,1,white,blue,0,83a4b621,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 42 42 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 42 42 0 ]);\npatch([8.875 16.1 21.1 26.1 31.1 21.1 13.875 8.875 ],[26.55" " 26.55 31.55 26.55 31.55 31.55 31.55 26.55 ],[1 1 1 ]);\npatch([13.875 21.1 16.1 8.875 13.875 ],[21.55 21.55 26" ".55 26.55 21.55 ],[0.931 0.946 0.973 ]);\npatch([8.875 16.1 21.1 13.875 8.875 ],[16.55 16.55 21.55 21.55 16.55 " "],[1 1 1 ]);\npatch([13.875 31.1 26.1 21.1 16.1 8.875 13.875 ],[11.55 11.55 16.55 11.55 16.55 16.55 11.55 ],[0." "931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\n" "color('black');disp('and');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical2" SID "470" Ports [2, 1] Position [450, 205, 480, 240] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "AND" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" sg_icon_stat "30,35,2,1,white,blue,0,83a4b621,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 35 35 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 35 35 0 ]);\npatch([6.1 11.88 15.88 19.88 23.88 15.88 10.1 6.1 ],[21.44 " "21.44 25.44 21.44 25.44 25.44 25.44 21.44 ],[1 1 1 ]);\npatch([10.1 15.88 11.88 6.1 10.1 ],[17.44 17.44 21.44 2" "1.44 17.44 ],[0.931 0.946 0.973 ]);\npatch([6.1 11.88 15.88 10.1 6.1 ],[13.44 13.44 17.44 17.44 13.44 ],[1 1 1 " "]);\npatch([10.1 23.88 19.88 15.88 11.88 6.1 10.1 ],[9.44 9.44 13.44 9.44 13.44 13.44 9.44 ],[0.931 0.946 0.973" " ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\ncolor('black');" "disp('and');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical3" SID "14908" Ports [2, 1] Position [715, 424, 755, 466] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "AND" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" sg_icon_stat "40,42,2,1,white,blue,0,83a4b621,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 42 42 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 42 42 0 ]);\npatch([8.875 16.1 21.1 26.1 31.1 21.1 13.875 8.875 ],[26.55" " 26.55 31.55 26.55 31.55 31.55 31.55 26.55 ],[1 1 1 ]);\npatch([13.875 21.1 16.1 8.875 13.875 ],[21.55 21.55 26" ".55 26.55 21.55 ],[0.931 0.946 0.973 ]);\npatch([8.875 16.1 21.1 13.875 8.875 ],[16.55 16.55 21.55 21.55 16.55 " "],[1 1 1 ]);\npatch([13.875 31.1 26.1 21.1 16.1 8.875 13.875 ],[11.55 11.55 16.55 11.55 16.55 16.55 11.55 ],[0." "931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\n" "color('black');disp('and');\nfprintf('','COMMENT: end icon text');" } Block { BlockType SubSystem Name "Mult by LTF" SID "471" Ports [5, 3] Position [540, 140, 620, 220] NamePlacement "alternate" MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "Mult by LTF" Location [-1678, 70, -2, 1030] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "x_re" SID "472" Position [525, 383, 555, 397] IconDisplay "Port number" } Block { BlockType Inport Name "x_im" SID "473" Position [525, 503, 555, 517] Port "2" IconDisplay "Port number" } Block { BlockType Inport Name "Sym Ind" SID "14917" Position [160, 208, 190, 222] NamePlacement "alternate" Port "3" IconDisplay "Port number" } Block { BlockType Inport Name "x_valid" SID "9903" Position [525, 123, 555, 137] Port "4" IconDisplay "Port number" } Block { BlockType Inport Name "x_ind" SID "474" Position [525, 218, 555, 232] Port "5" IconDisplay "Port number" } Block { BlockType Reference Name "Constant1" SID "475" Ports [0, 1] Position [960, 472, 995, 498] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "0" gui_display_data_type "Fixed-point" arith_type "Signed (2's comp)" n_bits "2" bin_pt "2" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "8" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" sg_icon_stat "35,26,0,1,white,blue,0,bf4ddd8b,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 26 26 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 35 35 0 0 ],[0 0 26 26 0 ]);\npatch([10.325 14.66 17.66 20.66 23.66 17.66 13.325 10.325 ],[16.33 16" ".33 19.33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([13.325 17.66 14.66 10.325 13.325 ],[13.33 13.33 16.33" " 16.33 13.33 ],[0.931 0.946 0.973 ]);\npatch([10.325 14.66 17.66 13.325 10.325 ],[10.33 10.33 13.33 13.33 10.33 ]," "[1 1 1 ]);\npatch([13.325 23.66 20.66 17.66 14.66 10.325 13.325 ],[7.33 7.33 10.33 7.33 10.33 10.33 7.33 ],[0.931 " "0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black'" ");port_label('output',1,'0');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Constant2" SID "476" Ports [0, 1] Position [960, 352, 995, 378] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "0" gui_display_data_type "Fixed-point" arith_type "Signed (2's comp)" n_bits "2" bin_pt "2" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "8" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" sg_icon_stat "35,26,0,1,white,blue,0,bf4ddd8b,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 26 26 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 35 35 0 0 ],[0 0 26 26 0 ]);\npatch([10.325 14.66 17.66 20.66 23.66 17.66 13.325 10.325 ],[16.33 16" ".33 19.33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([13.325 17.66 14.66 10.325 13.325 ],[13.33 13.33 16.33" " 16.33 13.33 ],[0.931 0.946 0.973 ]);\npatch([10.325 14.66 17.66 13.325 10.325 ],[10.33 10.33 13.33 13.33 10.33 ]," "[1 1 1 ]);\npatch([13.325 23.66 20.66 17.66 14.66 10.325 13.325 ],[7.33 7.33 10.33 7.33 10.33 10.33 7.33 ],[0.931 " "0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black'" ");port_label('output',1,'0');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Constant3" SID "14914" Ports [0, 1] Position [160, 222, 195, 248] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "6" gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "3" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "8" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" sg_icon_stat "35,26,0,1,white,blue,0,f0403ad7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 26 26 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 35 35 0 0 ],[0 0 26 26 0 ]);\npatch([10.325 14.66 17.66 20.66 23.66 17.66 13.325 10.325 ],[16.33 16" ".33 19.33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([13.325 17.66 14.66 10.325 13.325 ],[13.33 13.33 16.33" " 16.33 13.33 ],[0.931 0.946 0.973 ]);\npatch([10.325 14.66 17.66 13.325 10.325 ],[10.33 10.33 13.33 13.33 10.33 ]," "[1 1 1 ]);\npatch([13.325 23.66 20.66 17.66 14.66 10.325 13.325 ],[7.33 7.33 10.33 7.33 10.33 10.33 7.33 ],[0.931 " "0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black'" ");port_label('output',1,'6');\nfprintf('','COMMENT: end icon text');" } Block { BlockType From Name "From" SID "477" Position [125, 148, 345, 172] ZOrder -9 ShowName off GotoTag "RX_PHY_MODE_11N_AC" TagVisibility "global" } Block { BlockType Reference Name "HT-LTF" SID "478" Ports [1, 1] Position [605, 251, 680, 289] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/ROM" SourceType "Xilinx Single Port Read-Only Memory Block" depth "MAX_NUM_SC" initVector "ht_ltf_f" distributed_mem "Distributed memory" rst off init_reg "0" en off latency "0" gui_display_data_type "Fixed-point" arith_type "Signed (2's comp)" n_bits "2" bin_pt "1" preci_type "Single" exp_width "8" frac_width "24" dbl_ovrd off optimize "Area" use_rpm on xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "sprom" sg_icon_stat "75,38,1,1,white,blue,0,eff69a7e,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 75 75 0 0 ],[0 0 38 38 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 75 75 0 0 ],[0 0 38 38 0 ]);\npatch([25.875 33.1 38.1 43.1 48.1 38.1 30.875 25.875 ],[24.55 24.55 2" "9.55 24.55 29.55 29.55 29.55 24.55 ],[1 1 1 ]);\npatch([30.875 38.1 33.1 25.875 30.875 ],[19.55 19.55 24.55 24.55 " "19.55 ],[0.931 0.946 0.973 ]);\npatch([25.875 33.1 38.1 30.875 25.875 ],[14.55 14.55 19.55 19.55 14.55 ],[1 1 1 ])" ";\npatch([30.875 48.1 43.1 38.1 33.1 25.875 30.875 ],[9.55 9.55 14.55 9.55 14.55 14.55 9.55 ],[0.931 0.946 0.973 ]" ");\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label(" "'input',1,'addr');\n\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Inverter" SID "9904" Ports [1, 1] Position [1055, 202, 1090, 218] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Inverter" SourceType "Xilinx Inverter Block" infoedit "Bitwise logical negation (one's complement) operator." en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "inv" sg_icon_stat "35,16,1,1,white,blue,0,267846e5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 16 16 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 35 35 0 0 ],[0 0 16 16 0 ]);\npatch([12.55 15.44 17.44 19.44 21.44 17.44 14.55 12.55 ],[10.22 10.22" " 12.22 10.22 12.22 12.22 12.22 10.22 ],[1 1 1 ]);\npatch([14.55 17.44 15.44 12.55 14.55 ],[8.22 8.22 10.22 10.22 8" ".22 ],[0.931 0.946 0.973 ]);\npatch([12.55 15.44 17.44 14.55 12.55 ],[6.22 6.22 8.22 8.22 6.22 ],[1 1 1 ]);\npatch" "([14.55 21.44 19.44 17.44 15.44 12.55 14.55 ],[4.22 4.22 6.22 4.22 6.22 6.22 4.22 ],[0.931 0.946 0.973 ]);\nfprint" "f('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');disp('not');\nfpr" "intf('','COMMENT: end icon text');" } Block { BlockType Reference Name "L-LTF" SID "479" Ports [1, 1] Position [605, 206, 680, 244] NamePlacement "alternate" LibraryVersion "1.2" SourceBlock "xbsIndex_r4/ROM" SourceType "Xilinx Single Port Read-Only Memory Block" depth "MAX_NUM_SC" initVector "l_ltf_f" distributed_mem "Distributed memory" rst off init_reg "0" en off latency "0" gui_display_data_type "Fixed-point" arith_type "Signed (2's comp)" n_bits "2" bin_pt "1" preci_type "Single" exp_width "8" frac_width "24" dbl_ovrd off optimize "Area" use_rpm on xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "sprom" sg_icon_stat "75,38,1,1,white,blue,0,eff69a7e,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 75 75 0 0 ],[0 0 38 38 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 75 75 0 0 ],[0 0 38 38 0 ]);\npatch([25.875 33.1 38.1 43.1 48.1 38.1 30.875 25.875 ],[24.55 24.55 2" "9.55 24.55 29.55 29.55 29.55 24.55 ],[1 1 1 ]);\npatch([30.875 38.1 33.1 25.875 30.875 ],[19.55 19.55 24.55 24.55 " "19.55 ],[0.931 0.946 0.973 ]);\npatch([25.875 33.1 38.1 30.875 25.875 ],[14.55 14.55 19.55 19.55 14.55 ],[1 1 1 ])" ";\npatch([30.875 48.1 43.1 38.1 33.1 25.875 30.875 ],[9.55 9.55 14.55 9.55 14.55 14.55 9.55 ],[0.931 0.946 0.973 ]" ");\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label(" "'input',1,'addr');\n\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical" SID "9905" Ports [2, 1] Position [1145, 190, 1185, 270] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "OR" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" sg_icon_stat "40,80,2,1,white,blue,0,7ede7d88,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 80 80 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 40 40 0 0 ],[0 0 80 80 0 ]);\npatch([8.875 16.1 21.1 26.1 31.1 21.1 13.875 8.875 ],[45.55 45.55 50." "55 45.55 50.55 50.55 50.55 45.55 ],[1 1 1 ]);\npatch([13.875 21.1 16.1 8.875 13.875 ],[40.55 40.55 45.55 45.55 40." "55 ],[0.931 0.946 0.973 ]);\npatch([8.875 16.1 21.1 13.875 8.875 ],[35.55 35.55 40.55 40.55 35.55 ],[1 1 1 ]);\npa" "tch([13.875 31.1 26.1 21.1 16.1 8.875 13.875 ],[30.55 30.55 35.55 30.55 35.55 35.55 30.55 ],[0.931 0.946 0.973 ]);" "\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\ncolor('black');disp('o" "r');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical1" SID "14916" Ports [2, 1] Position [440, 140, 480, 220] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "AND" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" sg_icon_stat "40,80,2,1,white,blue,0,83a4b621,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 80 80 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 40 40 0 0 ],[0 0 80 80 0 ]);\npatch([8.875 16.1 21.1 26.1 31.1 21.1 13.875 8.875 ],[45.55 45.55 50." "55 45.55 50.55 50.55 50.55 45.55 ],[1 1 1 ]);\npatch([13.875 21.1 16.1 8.875 13.875 ],[40.55 40.55 45.55 45.55 40." "55 ],[0.931 0.946 0.973 ]);\npatch([8.875 16.1 21.1 13.875 8.875 ],[35.55 35.55 40.55 40.55 35.55 ],[1 1 1 ]);\npa" "tch([13.875 31.1 26.1 21.1 16.1 8.875 13.875 ],[30.55 30.55 35.55 30.55 35.55 35.55 30.55 ],[0.931 0.946 0.973 ]);" "\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\ncolor('black');disp('a" "nd');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Mux" SID "480" Ports [4, 1] Position [1060, 326, 1085, 429] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Mux" SourceType "Xilinx Bus Multiplexer Block" inputs "3" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "14" quantization "Truncate" overflow "Wrap" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "mux" sg_icon_stat "25,103,4,1,white,blue,3,58b3489d,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 14.7143 88.2857 103 0 ],[0" ".77 0.82 0.91 ]);\nplot([0 25 25 0 0 ],[0 14.7143 88.2857 103 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.3" "25 5.325 ],[54.33 54.33 57.33 54.33 57.33 57.33 57.33 54.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[5" "1.33 51.33 54.33 54.33 51.33 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[48.33 48.33 51.33 51" ".33 48.33 ],[1 1 1 ]);\npatch([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[45.33 45.33 48.33 45.33 48.33 48.33 45." "33 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\nc" "olor('black');port_label('input',1,'sel');\ncolor('black');port_label('input',2,'d0');\ncolor('black');port_label(" "'input',3,'d1');\ncolor('black');port_label('input',4,'d2');\n\ncolor('black');disp('\\bf{}','texmode','on');\nfpr" "intf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Mux1" SID "481" Ports [4, 1] Position [1060, 446, 1085, 549] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Mux" SourceType "Xilinx Bus Multiplexer Block" inputs "3" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "14" quantization "Truncate" overflow "Wrap" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "mux" sg_icon_stat "25,103,4,1,white,blue,3,58b3489d,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 14.7143 88.2857 103 0 ],[0" ".77 0.82 0.91 ]);\nplot([0 25 25 0 0 ],[0 14.7143 88.2857 103 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.3" "25 5.325 ],[54.33 54.33 57.33 54.33 57.33 57.33 57.33 54.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[5" "1.33 51.33 54.33 54.33 51.33 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[48.33 48.33 51.33 51" ".33 48.33 ],[1 1 1 ]);\npatch([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[45.33 45.33 48.33 45.33 48.33 48.33 45." "33 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\nc" "olor('black');port_label('input',1,'sel');\ncolor('black');port_label('input',2,'d0');\ncolor('black');port_label(" "'input',3,'d1');\ncolor('black');port_label('input',4,'d2');\n\ncolor('black');disp('\\bf{}','texmode','on');\nfpr" "intf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Mux2" SID "482" Ports [3, 1] Position [760, 157, 785, 293] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Mux" SourceType "Xilinx Bus Multiplexer Block" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "14" quantization "Truncate" overflow "Wrap" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "mux" sg_icon_stat "25,136,3,1,white,blue,3,eb98d690,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 19.4286 116.571 136 0 ],[0" ".77 0.82 0.91 ]);\nplot([0 25 25 0 0 ],[0 19.4286 116.571 136 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.3" "25 5.325 ],[71.33 71.33 74.33 71.33 74.33 74.33 74.33 71.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[6" "8.33 68.33 71.33 71.33 68.33 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[65.33 65.33 68.33 68" ".33 65.33 ],[1 1 1 ]);\npatch([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[62.33 62.33 65.33 62.33 65.33 65.33 62." "33 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\nc" "olor('black');port_label('input',1,'sel');\ncolor('black');port_label('input',2,'d0');\ncolor('black');port_label(" "'input',3,'d1');\n\ncolor('black');disp('\\bf{}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Negate" SID "483" Ports [1, 1] Position [960, 398, 990, 432] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Negate" SourceType "Xilinx Negate Block Block" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "14" quantization "Truncate" overflow "Wrap" en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "negate" sg_icon_stat "30,34,1,1,white,blue,0,36bd7045,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 34 34 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 30 30 0 0 ],[0 0 34 34 0 ]);\npatch([6.1 11.88 15.88 19.88 23.88 15.88 10.1 6.1 ],[21.44 21.44 25.4" "4 21.44 25.44 25.44 25.44 21.44 ],[1 1 1 ]);\npatch([10.1 15.88 11.88 6.1 10.1 ],[17.44 17.44 21.44 21.44 17.44 ]," "[0.931 0.946 0.973 ]);\npatch([6.1 11.88 15.88 10.1 6.1 ],[13.44 13.44 17.44 17.44 13.44 ],[1 1 1 ]);\npatch([10.1" " 23.88 19.88 15.88 11.88 6.1 10.1 ],[9.44 9.44 13.44 9.44 13.44 13.44 9.44 ],[0.931 0.946 0.973 ]);\nfprintf('','C" "OMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');disp('\\bf{x(-1)}','texm" "ode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Negate1" SID "484" Ports [1, 1] Position [960, 518, 990, 552] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Negate" SourceType "Xilinx Negate Block Block" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "14" quantization "Truncate" overflow "Wrap" en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "negate" sg_icon_stat "30,34,1,1,white,blue,0,36bd7045,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 34 34 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 30 30 0 0 ],[0 0 34 34 0 ]);\npatch([6.1 11.88 15.88 19.88 23.88 15.88 10.1 6.1 ],[21.44 21.44 25.4" "4 21.44 25.44 25.44 25.44 21.44 ],[1 1 1 ]);\npatch([10.1 15.88 11.88 6.1 10.1 ],[17.44 17.44 21.44 21.44 17.44 ]," "[0.931 0.946 0.973 ]);\npatch([6.1 11.88 15.88 10.1 6.1 ],[13.44 13.44 17.44 17.44 13.44 ],[1 1 1 ]);\npatch([10.1" " 23.88 19.88 15.88 11.88 6.1 10.1 ],[9.44 9.44 13.44 9.44 13.44 13.44 9.44 ],[0.931 0.946 0.973 ]);\nfprintf('','C" "OMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');disp('\\bf{x(-1)}','texm" "ode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Reinterpret" SID "485" Ports [1, 1] Position [900, 331, 935, 349] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Reinterpret" SourceType "Xilinx Type Reinterpreter Block" infoedit "Changes signal type without altering the binary representation. You can change the signal between s" "igned and unsigned, and relocate the binary point.

Hardware notes: In hardware this block costs nothing.
Example: Suppose the input is 6 bits wide, signed, with 2 fractional bits, and the output is forced to unsig" "ned with 0 fractional bits. Then an input of -2.0 (1110.00 in binary 2's complement) becomes an output of 56 (111" "000 in binary)." force_arith_type on arith_type "Unsigned" force_bin_pt on bin_pt "0" has_advanced_control "0" sggui_pos "20,20,356,278" block_type "cast" block_version "VER_STRING_GOES_HERE" sg_icon_stat "35,18,1,1,white,blue,0,6b04d0b0,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 18 18 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 35 35 0 0 ],[0 0 18 18 0 ]);\npatch([12.55 15.44 17.44 19.44 21.44 17.44 14.55 12.55 ],[11.22 11.22" " 13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([14.55 17.44 15.44 12.55 14.55 ],[9.22 9.22 11.22 11.22 9" ".22 ],[0.931 0.946 0.973 ]);\npatch([12.55 15.44 17.44 14.55 12.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);\npatch" "([14.55 21.44 19.44 17.44 15.44 12.55 14.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\nfprint" "f('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');disp('reinterpret" "');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Relational" SID "9714" Ports [2, 1] Position [1050, 231, 1095, 269] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Relational" SourceType "Xilinx Arithmetic Relational Operator Block" mode "a=b" en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "relational" sg_icon_stat "45,38,2,1,white,blue,0,2a81ff49,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 38 38 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 45 45 0 0 ],[0 0 38 38 0 ]);\npatch([10.875 18.1 23.1 28.1 33.1 23.1 15.875 10.875 ],[24.55 24.55 2" "9.55 24.55 29.55 29.55 29.55 24.55 ],[1 1 1 ]);\npatch([15.875 23.1 18.1 10.875 15.875 ],[19.55 19.55 24.55 24.55 " "19.55 ],[0.931 0.946 0.973 ]);\npatch([10.875 18.1 23.1 15.875 10.875 ],[14.55 14.55 19.55 19.55 14.55 ],[1 1 1 ])" ";\npatch([15.875 33.1 28.1 23.1 18.1 10.875 15.875 ],[9.55 9.55 14.55 9.55 14.55 14.55 9.55 ],[0.931 0.946 0.973 ]" ");\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label(" "'input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('output',1,'\\bfa = b','texm" "ode','on');\ncolor('black');disp(' ');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Relational3" SID "14915" Ports [2, 1] Position [260, 204, 305, 246] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Relational" SourceType "Xilinx Arithmetic Relational Operator Block" mode "a>=b" en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "relational" sg_icon_stat "45,42,2,1,white,blue,0,6218dc92,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 42 42 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 45 45 0 0 ],[0 0 42 42 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[27.66 27.66 3" "3.66 27.66 33.66 33.66 33.66 27.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[21.66 21.66 27.66 27.66 21" ".66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[15.66 15.66 21.66 21.66 15.66 ],[1 1 1 ]);\npa" "tch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[9.66 9.66 15.66 9.66 15.66 15.66 9.66 ],[0.931 0.946 0.973 ]);\nf" "printf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('inpu" "t',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('output',1,'\\bfa \\geq b','texmo" "de','on');\ncolor('black');disp(' ');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Outport Name "H_re" SID "486" Position [1220, 373, 1250, 387] IconDisplay "Port number" } Block { BlockType Outport Name "H_im" SID "487" Position [1220, 493, 1250, 507] Port "2" IconDisplay "Port number" } Block { BlockType Outport Name "Empty Sc" SID "9715" Position [1275, 223, 1305, 237] Port "3" IconDisplay "Port number" } Line { SrcBlock "Negate" SrcPort 1 DstBlock "Mux" DstPort 4 } Line { SrcBlock "Constant2" SrcPort 1 Points [25, 0] Branch { DstBlock "Mux" DstPort 2 } Branch { Points [0, -125] DstBlock "Relational" DstPort 1 } } Line { SrcBlock "x_re" SrcPort 1 Points [375, 0] Branch { DstBlock "Mux" DstPort 3 } Branch { Points [0, 25] DstBlock "Negate" DstPort 1 } } Line { SrcBlock "x_ind" SrcPort 1 Points [15, 0] Branch { DstBlock "L-LTF" DstPort 1 } Branch { Points [0, 45] DstBlock "HT-LTF" DstPort 1 } } Line { SrcBlock "Mux" SrcPort 1 DstBlock "H_re" DstPort 1 } Line { SrcBlock "Constant1" SrcPort 1 DstBlock "Mux1" DstPort 2 } Line { SrcBlock "x_im" SrcPort 1 Points [375, 0] Branch { Points [0, 25] DstBlock "Negate1" DstPort 1 } Branch { DstBlock "Mux1" DstPort 3 } } Line { SrcBlock "Mux1" SrcPort 1 DstBlock "H_im" DstPort 1 } Line { SrcBlock "Reinterpret" SrcPort 1 Points [95, 0] Branch { DstBlock "Mux" DstPort 1 } Branch { Points [0, 120] DstBlock "Mux1" DstPort 1 } Branch { DstBlock "Relational" DstPort 2 } } Line { SrcBlock "Negate1" SrcPort 1 DstBlock "Mux1" DstPort 4 } Line { SrcBlock "Logical1" SrcPort 1 DstBlock "Mux2" DstPort 1 } Line { SrcBlock "L-LTF" SrcPort 1 DstBlock "Mux2" DstPort 2 } Line { SrcBlock "HT-LTF" SrcPort 1 DstBlock "Mux2" DstPort 3 } Line { SrcBlock "Mux2" SrcPort 1 Points [55, 0; 0, 115] DstBlock "Reinterpret" DstPort 1 } Line { SrcBlock "Relational" SrcPort 1 DstBlock "Logical" DstPort 2 } Line { SrcBlock "Logical" SrcPort 1 DstBlock "Empty Sc" DstPort 1 } Line { SrcBlock "Inverter" SrcPort 1 DstBlock "Logical" DstPort 1 } Line { SrcBlock "x_valid" SrcPort 1 Points [415, 0; 0, 80] DstBlock "Inverter" DstPort 1 } Line { SrcBlock "From" SrcPort 1 DstBlock "Logical1" DstPort 1 } Line { SrcBlock "Sym Ind" SrcPort 1 DstBlock "Relational3" DstPort 1 } Line { SrcBlock "Constant3" SrcPort 1 DstBlock "Relational3" DstPort 2 } Line { SrcBlock "Relational3" SrcPort 1 Points [55, 0; 0, -25] DstBlock "Logical1" DstPort 2 } Annotation { Name "OFDM Symbols in 11a/g:\n0: LTF (BPSK)\n1: LTF (BPSK)\n2: SIG (BPSK)\n3-N: Data" Position [859, 918] HorizontalAlignment "left" } Annotation { Name "OFDM Symbols in 11n SISO:\n0: L-LTF (BPSK)\n1: L-LTF (BPSK)\n2: L-SIG (BPSK)\n3: HT-SIG1 (QBPSK)\n4: HT-" "SIG2 (QBPSK)\n5: HT-STF\n6: HT-LFT1\n7-N: Data" Position [1009, 943] HorizontalAlignment "left" } Annotation { Name "OFDM Symbols in 11ac SISO:\n0: L-LTF (BPSK)\n1: L-LTF (BPSK)\n2: L-SIG (BPSK)\n3: VHT-SIGA1 (BPSK)\n4: V" "HT-SIGA2 (QBPSK)\n5: VHT-STF\n6: VHT-LFT1\n7: VHT-SIGB\n8-N: Data" Position [1184, 958] HorizontalAlignment "left" } Annotation { Name "Ignore early phy_mode det - only use HT masks\nfor HT-LTF and later symbols" Position [245, 266] } } } Block { BlockType RealImagToComplex Name "Real-Imag to\nComplex" SID "514" Ports [2, 1] Position [1095, 732, 1120, 748] ZOrder -21 ShowName off Input "Real and imag" } Block { BlockType RealImagToComplex Name "Real-Imag to\nComplex1" SID "515" Ports [2, 1] Position [1095, 707, 1120, 723] ZOrder -21 ShowName off Input "Real and imag" } Block { BlockType RealImagToComplex Name "Real-Imag to\nComplex2" SID "10105" Ports [2, 1] Position [1215, 853, 1245, 882] ZOrder -21 Input "Real and imag" } Block { BlockType SubSystem Name "To Float" SID "516" Ports [7, 7] Position [1055, 22, 1160, 258] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "To Float" Location [2, 70, 2464, 1580] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "x_I " SID "517" Position [480, 423, 510, 437] NamePlacement "alternate" IconDisplay "Port number" } Block { BlockType Inport Name "x_Q " SID "518" Position [480, 463, 510, 477] Port "2" IconDisplay "Port number" } Block { BlockType Inport Name "H_I " SID "519" Position [480, 548, 510, 562] NamePlacement "alternate" Port "3" IconDisplay "Port number" } Block { BlockType Inport Name "H_Q " SID "520" Position [480, 573, 510, 587] Port "4" IconDisplay "Port number" } Block { BlockType Inport Name "x_ind" SID "521" Position [355, 733, 385, 747] Port "5" IconDisplay "Port number" } Block { BlockType Inport Name "x_valid" SID "522" Position [355, 628, 385, 642] Port "6" IconDisplay "Port number" } Block { BlockType Inport Name "sym_ind" SID "523" Position [355, 808, 385, 822] Port "7" IconDisplay "Port number" } Block { BlockType Reference Name "Delay1" SID "524" Ports [1, 1] Position [695, 678, 730, 702] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flop." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en off latency "3" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" sg_icon_stat "35,24,1,1,white,blue,0,83e6bb61,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 24 24 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 35 35 0 0 ],[0 0 24 24 0 ]);\npatch([10.325 14.66 17.66 20.66 23.66 17.66 13.325 10.325 ],[15.33 15" ".33 18.33 15.33 18.33 18.33 18.33 15.33 ],[1 1 1 ]);\npatch([13.325 17.66 14.66 10.325 13.325 ],[12.33 12.33 15.33" " 15.33 12.33 ],[0.931 0.946 0.973 ]);\npatch([10.325 14.66 17.66 13.325 10.325 ],[9.33 9.33 12.33 12.33 9.33 ],[1 " "1 1 ]);\npatch([13.325 23.66 20.66 17.66 14.66 10.325 13.325 ],[6.33 6.33 9.33 6.33 9.33 9.33 6.33 ],[0.931 0.946 " "0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');" "disp('z^{-3}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Delay2" SID "525" Ports [1, 1] Position [695, 728, 730, 752] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flop." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en off latency "3" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" sg_icon_stat "35,24,1,1,white,blue,0,83e6bb61,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 24 24 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 35 35 0 0 ],[0 0 24 24 0 ]);\npatch([10.325 14.66 17.66 20.66 23.66 17.66 13.325 10.325 ],[15.33 15" ".33 18.33 15.33 18.33 18.33 18.33 15.33 ],[1 1 1 ]);\npatch([13.325 17.66 14.66 10.325 13.325 ],[12.33 12.33 15.33" " 15.33 12.33 ],[0.931 0.946 0.973 ]);\npatch([10.325 14.66 17.66 13.325 10.325 ],[9.33 9.33 12.33 12.33 9.33 ],[1 " "1 1 ]);\npatch([13.325 23.66 20.66 17.66 14.66 10.325 13.325 ],[6.33 6.33 9.33 6.33 9.33 9.33 6.33 ],[0.931 0.946 " "0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');" "disp('z^{-3}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Delay3" SID "526" Ports [1, 1] Position [695, 803, 730, 827] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flop." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en off latency "3" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" sg_icon_stat "35,24,1,1,white,blue,0,83e6bb61,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 24 24 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 35 35 0 0 ],[0 0 24 24 0 ]);\npatch([10.325 14.66 17.66 20.66 23.66 17.66 13.325 10.325 ],[15.33 15" ".33 18.33 15.33 18.33 18.33 18.33 15.33 ],[1 1 1 ]);\npatch([13.325 17.66 14.66 10.325 13.325 ],[12.33 12.33 15.33" " 15.33 12.33 ],[0.931 0.946 0.973 ]);\npatch([10.325 14.66 17.66 13.325 10.325 ],[9.33 9.33 12.33 12.33 9.33 ],[1 " "1 1 ]);\npatch([13.325 23.66 20.66 17.66 14.66 10.325 13.325 ],[6.33 6.33 9.33 6.33 9.33 9.33 6.33 ],[0.931 0.946 " "0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');" "disp('z^{-3}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Inverter" SID "527" Ports [1, 1] Position [435, 627, 470, 643] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Inverter" SourceType "Xilinx Inverter Block" infoedit "Bitwise logical negation (one's complement) operator." en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "inv" sg_icon_stat "35,16,1,1,white,blue,0,267846e5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 16 16 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 35 35 0 0 ],[0 0 16 16 0 ]);\npatch([12.55 15.44 17.44 19.44 21.44 17.44 14.55 12.55 ],[10.22 10.22" " 12.22 10.22 12.22 12.22 12.22 10.22 ],[1 1 1 ]);\npatch([14.55 17.44 15.44 12.55 14.55 ],[8.22 8.22 10.22 10.22 8" ".22 ],[0.931 0.946 0.973 ]);\npatch([12.55 15.44 17.44 14.55 12.55 ],[6.22 6.22 8.22 8.22 6.22 ],[1 1 1 ]);\npatch" "([14.55 21.44 19.44 17.44 15.44 12.55 14.55 ],[4.22 4.22 6.22 4.22 6.22 6.22 4.22 ],[0.931 0.946 0.973 ]);\nfprint" "f('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');disp('not');\nfpr" "intf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register" SID "528" Ports [2, 1] Position [640, 422, 685, 453] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst on en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "45,31,2,1,white,blue,0,140cc11c,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 31 31 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 45 45 0 0 ],[0 0 31 31 0 ]);\npatch([13.1 18.88 22.88 26.88 30.88 22.88 17.1 13.1 ],[19.44 19.44 23" ".44 19.44 23.44 23.44 23.44 19.44 ],[1 1 1 ]);\npatch([17.1 22.88 18.88 13.1 17.1 ],[15.44 15.44 19.44 19.44 15.44" " ],[0.931 0.946 0.973 ]);\npatch([13.1 18.88 22.88 17.1 13.1 ],[11.44 11.44 15.44 15.44 11.44 ],[1 1 1 ]);\npatch(" "[17.1 30.88 26.88 22.88 18.88 13.1 17.1 ],[7.44 7.44 11.44 7.44 11.44 11.44 7.44 ],[0.931 0.946 0.973 ]);\nfprintf" "('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'" "d');\ncolor('black');port_label('input',2,'rst');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp" "('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register1" SID "529" Ports [2, 1] Position [640, 462, 685, 493] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst on en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "45,31,2,1,white,blue,0,140cc11c,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 31 31 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 45 45 0 0 ],[0 0 31 31 0 ]);\npatch([13.1 18.88 22.88 26.88 30.88 22.88 17.1 13.1 ],[19.44 19.44 23" ".44 19.44 23.44 23.44 23.44 19.44 ],[1 1 1 ]);\npatch([17.1 22.88 18.88 13.1 17.1 ],[15.44 15.44 19.44 19.44 15.44" " ],[0.931 0.946 0.973 ]);\npatch([13.1 18.88 22.88 17.1 13.1 ],[11.44 11.44 15.44 15.44 11.44 ],[1 1 1 ]);\npatch(" "[17.1 30.88 26.88 22.88 18.88 13.1 17.1 ],[7.44 7.44 11.44 7.44 11.44 11.44 7.44 ],[0.931 0.946 0.973 ]);\nfprintf" "('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'" "d');\ncolor('black');port_label('input',2,'rst');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp" "('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register2" SID "530" Ports [2, 1] Position [640, 547, 685, 578] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst on en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "45,31,2,1,white,blue,0,140cc11c,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 31 31 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 45 45 0 0 ],[0 0 31 31 0 ]);\npatch([13.1 18.88 22.88 26.88 30.88 22.88 17.1 13.1 ],[19.44 19.44 23" ".44 19.44 23.44 23.44 23.44 19.44 ],[1 1 1 ]);\npatch([17.1 22.88 18.88 13.1 17.1 ],[15.44 15.44 19.44 19.44 15.44" " ],[0.931 0.946 0.973 ]);\npatch([13.1 18.88 22.88 17.1 13.1 ],[11.44 11.44 15.44 15.44 11.44 ],[1 1 1 ]);\npatch(" "[17.1 30.88 26.88 22.88 18.88 13.1 17.1 ],[7.44 7.44 11.44 7.44 11.44 11.44 7.44 ],[0.931 0.946 0.973 ]);\nfprintf" "('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'" "d');\ncolor('black');port_label('input',2,'rst');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp" "('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register3" SID "531" Ports [2, 1] Position [640, 572, 685, 603] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst on en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "45,31,2,1,white,blue,0,140cc11c,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 31 31 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 45 45 0 0 ],[0 0 31 31 0 ]);\npatch([13.1 18.88 22.88 26.88 30.88 22.88 17.1 13.1 ],[19.44 19.44 23" ".44 19.44 23.44 23.44 23.44 19.44 ],[1 1 1 ]);\npatch([17.1 22.88 18.88 13.1 17.1 ],[15.44 15.44 19.44 19.44 15.44" " ],[0.931 0.946 0.973 ]);\npatch([13.1 18.88 22.88 17.1 13.1 ],[11.44 11.44 15.44 15.44 11.44 ],[1 1 1 ]);\npatch(" "[17.1 30.88 26.88 22.88 18.88 13.1 17.1 ],[7.44 7.44 11.44 7.44 11.44 11.44 7.44 ],[0.931 0.946 0.973 ]);\nfprintf" "('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'" "d');\ncolor('black');port_label('input',2,'rst');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp" "('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "To FP1" SID "532" Ports [1, 1] Position [745, 465, 790, 495] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do not." gui_display_data_type "Floating-point" arith_type "Floating-point" n_bits "16" bin_pt "14" float_type "Single" exp_bits "8" fraction_bits "24" quantization "Truncate" overflow "Wrap" en off latency "2" dbl_ovrd off pipeline off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "convert" sg_icon_stat "45,30,1,1,white,blue,0,b61d041b,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 30 30 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 45 45 0 0 ],[0 0 30 30 0 ]);\npatch([13.1 18.88 22.88 26.88 30.88 22.88 17.1 13.1 ],[19.44 19.44 23" ".44 19.44 23.44 23.44 23.44 19.44 ],[1 1 1 ]);\npatch([17.1 22.88 18.88 13.1 17.1 ],[15.44 15.44 19.44 19.44 15.44" " ],[0.931 0.946 0.973 ]);\npatch([13.1 18.88 22.88 17.1 13.1 ],[11.44 11.44 15.44 15.44 11.44 ],[1 1 1 ]);\npatch(" "[17.1 30.88 26.88 22.88 18.88 13.1 17.1 ],[7.44 7.44 11.44 7.44 11.44 11.44 7.44 ],[0.931 0.946 0.973 ]);\nfprintf" "('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('output'," "1,'cast');\ncolor('black');disp('z^{-2}\\newline ','texmode','on');\ncolor('black');disp(' \\n ');\nfprintf('','CO" "MMENT: end icon text');" } Block { BlockType Reference Name "To FP2" SID "533" Ports [1, 1] Position [745, 550, 790, 580] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do not." gui_display_data_type "Floating-point" arith_type "Floating-point" n_bits "16" bin_pt "14" float_type "Single" exp_bits "8" fraction_bits "24" quantization "Truncate" overflow "Wrap" en off latency "2" dbl_ovrd off pipeline off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "convert" sg_icon_stat "45,30,1,1,white,blue,0,b61d041b,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 30 30 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 45 45 0 0 ],[0 0 30 30 0 ]);\npatch([13.1 18.88 22.88 26.88 30.88 22.88 17.1 13.1 ],[19.44 19.44 23" ".44 19.44 23.44 23.44 23.44 19.44 ],[1 1 1 ]);\npatch([17.1 22.88 18.88 13.1 17.1 ],[15.44 15.44 19.44 19.44 15.44" " ],[0.931 0.946 0.973 ]);\npatch([13.1 18.88 22.88 17.1 13.1 ],[11.44 11.44 15.44 15.44 11.44 ],[1 1 1 ]);\npatch(" "[17.1 30.88 26.88 22.88 18.88 13.1 17.1 ],[7.44 7.44 11.44 7.44 11.44 11.44 7.44 ],[0.931 0.946 0.973 ]);\nfprintf" "('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('output'," "1,'cast');\ncolor('black');disp('z^{-2}\\newline ','texmode','on');\ncolor('black');disp(' \\n ');\nfprintf('','CO" "MMENT: end icon text');" } Block { BlockType Reference Name "To FP3" SID "534" Ports [1, 1] Position [745, 575, 790, 605] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do not." gui_display_data_type "Floating-point" arith_type "Floating-point" n_bits "16" bin_pt "14" float_type "Single" exp_bits "8" fraction_bits "24" quantization "Truncate" overflow "Wrap" en off latency "2" dbl_ovrd off pipeline off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "convert" sg_icon_stat "45,30,1,1,white,blue,0,b61d041b,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 30 30 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 45 45 0 0 ],[0 0 30 30 0 ]);\npatch([13.1 18.88 22.88 26.88 30.88 22.88 17.1 13.1 ],[19.44 19.44 23" ".44 19.44 23.44 23.44 23.44 19.44 ],[1 1 1 ]);\npatch([17.1 22.88 18.88 13.1 17.1 ],[15.44 15.44 19.44 19.44 15.44" " ],[0.931 0.946 0.973 ]);\npatch([13.1 18.88 22.88 17.1 13.1 ],[11.44 11.44 15.44 15.44 11.44 ],[1 1 1 ]);\npatch(" "[17.1 30.88 26.88 22.88 18.88 13.1 17.1 ],[7.44 7.44 11.44 7.44 11.44 11.44 7.44 ],[0.931 0.946 0.973 ]);\nfprintf" "('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('output'," "1,'cast');\ncolor('black');disp('z^{-2}\\newline ','texmode','on');\ncolor('black');disp(' \\n ');\nfprintf('','CO" "MMENT: end icon text');" } Block { BlockType Reference Name "To FP4" SID "535" Ports [1, 1] Position [745, 425, 790, 455] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do not." gui_display_data_type "Floating-point" arith_type "Floating-point" n_bits "16" bin_pt "14" float_type "Single" exp_bits "8" fraction_bits "24" quantization "Truncate" overflow "Wrap" en off latency "2" dbl_ovrd off pipeline off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "convert" sg_icon_stat "45,30,1,1,white,blue,0,b61d041b,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 30 30 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 45 45 0 0 ],[0 0 30 30 0 ]);\npatch([13.1 18.88 22.88 26.88 30.88 22.88 17.1 13.1 ],[19.44 19.44 23" ".44 19.44 23.44 23.44 23.44 19.44 ],[1 1 1 ]);\npatch([17.1 22.88 18.88 13.1 17.1 ],[15.44 15.44 19.44 19.44 15.44" " ],[0.931 0.946 0.973 ]);\npatch([13.1 18.88 22.88 17.1 13.1 ],[11.44 11.44 15.44 15.44 11.44 ],[1 1 1 ]);\npatch(" "[17.1 30.88 26.88 22.88 18.88 13.1 17.1 ],[7.44 7.44 11.44 7.44 11.44 11.44 7.44 ],[0.931 0.946 0.973 ]);\nfprintf" "('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('output'," "1,'cast');\ncolor('black');disp('z^{-2}\\newline ','texmode','on');\ncolor('black');disp(' \\n ');\nfprintf('','CO" "MMENT: end icon text');" } Block { BlockType Outport Name " x_I" SID "536" Position [895, 433, 925, 447] NamePlacement "alternate" IconDisplay "Port number" } Block { BlockType Outport Name " x_Q" SID "537" Position [895, 473, 925, 487] Port "2" IconDisplay "Port number" } Block { BlockType Outport Name "H_I" SID "538" Position [895, 558, 925, 572] NamePlacement "alternate" Port "3" IconDisplay "Port number" } Block { BlockType Outport Name " H_Q" SID "539" Position [895, 583, 925, 597] Port "4" IconDisplay "Port number" } Block { BlockType Outport Name " x_ind" SID "540" Position [895, 733, 925, 747] Port "5" IconDisplay "Port number" } Block { BlockType Outport Name " x_valid" SID "541" Position [895, 683, 925, 697] Port "6" IconDisplay "Port number" } Block { BlockType Outport Name " sym_ind" SID "542" Position [895, 808, 925, 822] Port "7" IconDisplay "Port number" } Line { SrcBlock "To FP3" SrcPort 1 DstBlock " H_Q" DstPort 1 } Line { SrcBlock "To FP2" SrcPort 1 DstBlock "H_I" DstPort 1 } Line { SrcBlock "To FP1" SrcPort 1 DstBlock " x_Q" DstPort 1 } Line { SrcBlock "To FP4" SrcPort 1 DstBlock " x_I" DstPort 1 } Line { SrcBlock "Register3" SrcPort 1 DstBlock "To FP3" DstPort 1 } Line { SrcBlock "Register2" SrcPort 1 DstBlock "To FP2" DstPort 1 } Line { SrcBlock "Inverter" SrcPort 1 Points [85, 0; 0, -40] Branch { DstBlock "Register3" DstPort 2 } Branch { Points [0, -25] Branch { DstBlock "Register2" DstPort 2 } Branch { Points [0, -85] Branch { DstBlock "Register1" DstPort 2 } Branch { Points [0, -40] DstBlock "Register" DstPort 2 } } } } Line { SrcBlock "Register1" SrcPort 1 DstBlock "To FP1" DstPort 1 } Line { SrcBlock "Register" SrcPort 1 DstBlock "To FP4" DstPort 1 } Line { SrcBlock "x_I " SrcPort 1 DstBlock "Register" DstPort 1 } Line { SrcBlock "x_Q " SrcPort 1 DstBlock "Register1" DstPort 1 } Line { SrcBlock "H_I " SrcPort 1 DstBlock "Register2" DstPort 1 } Line { SrcBlock "H_Q " SrcPort 1 DstBlock "Register3" DstPort 1 } Line { SrcBlock "x_valid" SrcPort 1 Points [15, 0] Branch { DstBlock "Inverter" DstPort 1 } Branch { Points [0, 55] DstBlock "Delay1" DstPort 1 } } Line { SrcBlock "Delay1" SrcPort 1 DstBlock " x_valid" DstPort 1 } Line { SrcBlock "x_ind" SrcPort 1 DstBlock "Delay2" DstPort 1 } Line { SrcBlock "Delay2" SrcPort 1 DstBlock " x_ind" DstPort 1 } Line { SrcBlock "sym_ind" SrcPort 1 DstBlock "Delay3" DstPort 1 } Line { SrcBlock "Delay3" SrcPort 1 DstBlock " sym_ind" DstPort 1 } } } Block { BlockType ToWorkspace Name "To Workspace" SID "10106" Ports [1] Position [1280, 855, 1340, 885] ZOrder -7 VariableName "pre_eq" MaxDataPoints "inf" SampleTime "-1" SaveFormat "Array" } Block { BlockType ToWorkspace Name "To Workspace1" SID "10107" Ports [1] Position [1280, 775, 1340, 805] ZOrder -7 VariableName "pre_eq_valid" MaxDataPoints "inf" SampleTime "-1" SaveFormat "Array" } Block { BlockType Outport Name " x_I" SID "543" Position [1230, 28, 1260, 42] IconDisplay "Port number" } Block { BlockType Outport Name " x_Q" SID "544" Position [1230, 63, 1260, 77] Port "2" IconDisplay "Port number" } Block { BlockType Outport Name "H_I" SID "545" Position [1230, 98, 1260, 112] Port "3" IconDisplay "Port number" } Block { BlockType Outport Name "H_Q" SID "546" Position [1230, 133, 1260, 147] Port "4" IconDisplay "Port number" } Block { BlockType Outport Name " valid" SID "547" Position [1230, 203, 1260, 217] Port "5" IconDisplay "Port number" } Block { BlockType Outport Name " x_ind" SID "548" Position [1230, 168, 1260, 182] Port "6" IconDisplay "Port number" } Block { BlockType Outport Name " sym_ind" SID "549" Position [1230, 238, 1260, 252] Port "7" IconDisplay "Port number" } Line { SrcBlock "Logical2" SrcPort 1 Points [0, 5] DstBlock "Estimate Buffers" DstPort 4 } Line { SrcBlock "x_valid" SrcPort 1 Points [235, 0] Branch { Points [0, -15] DstBlock "Mult by LTF" DstPort 4 } Branch { Points [0, 5] Branch { Points [0, 230] DstBlock "Logical1" DstPort 1 } Branch { DstBlock "Logical2" DstPort 1 } } } Line { SrcBlock "Sym Ind" SrcPort 1 Points [35, 0] Branch { Labels [0, 0] DstBlock "Control" DstPort 1 } Branch { Points [0, 225] DstBlock "Delay2" DstPort 1 } Branch { Points [0, -90] DstBlock "Mult by LTF" DstPort 3 } } Line { Labels [0, 0] SrcBlock "Control" SrcPort 2 DstBlock "Estimate Buffers" DstPort 5 } Line { SrcBlock "Control" SrcPort 1 DstBlock "Logical2" DstPort 2 } Line { SrcBlock "Logical1" SrcPort 1 DstBlock "Logical3" DstPort 2 } Line { SrcBlock "Inverter" SrcPort 1 DstBlock "Logical1" DstPort 2 } Line { SrcBlock "Estimate Buffers" SrcPort 2 Points [85, 0] Branch { Points [0, 335] DstBlock "Gateway Out3" DstPort 1 } Branch { Points [30, 0] Branch { Points [0, -140] DstBlock "To Float" DstPort 4 } Branch { Points [0, 55] DstBlock "Chan Est Offload" DstPort 3 } } } Line { Name "x_I" Labels [0, 0] SrcBlock "Gateway Out8" SrcPort 1 Points [10, 0] Branch { Points [0, 195] DstBlock "Real-Imag to\nComplex" DstPort 1 } Branch { DstBlock "H Est Outputs" DstPort 1 } } Line { Name "x_Q" Labels [0, 0] SrcBlock "Gateway Out1" SrcPort 1 Points [5, 0] Branch { Points [0, 180] DstBlock "Real-Imag to\nComplex" DstPort 2 } Branch { DstBlock "H Est Outputs" DstPort 2 } } Line { Name "H_I" Labels [0, 0] SrcBlock "Gateway Out2" SrcPort 1 Points [20, 0] Branch { DstBlock "Real-Imag to\nComplex1" DstPort 1 } Branch { DstBlock "H Est Outputs" DstPort 3 } } Line { Name "H_Q" Labels [0, 0] SrcBlock "Gateway Out3" SrcPort 1 Points [15, 0] Branch { Points [0, 105] DstBlock "Real-Imag to\nComplex1" DstPort 2 } Branch { DstBlock "H Est Outputs" DstPort 4 } } Line { Name "SC Ind" Labels [0, 0] SrcBlock "Gateway Out4" SrcPort 1 DstBlock "H Est Outputs" DstPort 5 } Line { Name "Valid Out" Labels [0, 0] SrcBlock "Gateway Out5" SrcPort 1 DstBlock "H Est Outputs" DstPort 7 } Line { SrcBlock "x_ind" SrcPort 1 Points [30, 0] Branch { Points [185, 0] Branch { Points [0, -70] DstBlock "Estimate Buffers" DstPort 7 } Branch { DstBlock "Delay5" DstPort 1 } } Branch { Points [0, -165] DstBlock "Mult by LTF" DstPort 5 } } Line { SrcBlock "x_re" SrcPort 1 Points [175, 0] Branch { Points [0, 115] DstBlock "Mult by LTF" DstPort 1 } Branch { DstBlock "Delay3" DstPort 1 } } Line { SrcBlock "x_im" SrcPort 1 Points [170, 0] Branch { Points [0, 95] DstBlock "Mult by LTF" DstPort 2 } Branch { DstBlock "Delay4" DstPort 1 } } Line { SrcBlock "Mult by LTF" SrcPort 2 Points [15, 0] Branch { DstBlock "Estimate Buffers" DstPort 2 } Branch { Points [0, 385] Branch { DstBlock "Gateway Out1" DstPort 1 } Branch { Points [0, 310] DstBlock "Gateway Out13" DstPort 1 } } } Line { SrcBlock "Mult by LTF" SrcPort 1 Points [30, 0] Branch { DstBlock "Estimate Buffers" DstPort 1 } Branch { Points [0, 385] Branch { DstBlock "Gateway Out8" DstPort 1 } Branch { Points [0, 320] DstBlock "Gateway Out12" DstPort 1 } } } Line { SrcBlock "To Float" SrcPort 1 DstBlock " x_I" DstPort 1 } Line { SrcBlock "To Float" SrcPort 2 DstBlock " x_Q" DstPort 1 } Line { SrcBlock "To Float" SrcPort 3 DstBlock "H_I" DstPort 1 } Line { SrcBlock "To Float" SrcPort 4 DstBlock "H_Q" DstPort 1 } Line { SrcBlock "To Float" SrcPort 5 DstBlock " x_ind" DstPort 1 } Line { SrcBlock "To Float" SrcPort 6 DstBlock " valid" DstPort 1 } Line { SrcBlock "To Float" SrcPort 7 DstBlock " sym_ind" DstPort 1 } Line { SrcBlock "Abs" SrcPort 1 DstBlock "H Est Outputs" DstPort 9 } Line { SrcBlock "Real-Imag to\nComplex" SrcPort 1 DstBlock "Abs" DstPort 1 } Line { SrcBlock "Real-Imag to\nComplex1" SrcPort 1 DstBlock "Abs1" DstPort 1 } Line { SrcBlock "Abs1" SrcPort 1 DstBlock "H Est Outputs" DstPort 8 } Line { Name "Sym Ind" Labels [0, 0] SrcBlock "Gateway Out6" SrcPort 1 DstBlock "H Est Outputs" DstPort 6 } Line { SrcBlock "Control" SrcPort 3 DstBlock "Estimate Buffers" DstPort 6 } Line { SrcBlock "Control" SrcPort 4 Points [20, 0; 0, 160] DstBlock "Inverter" DstPort 1 } Line { Labels [1, 0] SrcBlock "Estimate Buffers" SrcPort 1 Points [90, 0] Branch { Points [0, 405] DstBlock "Gateway Out2" DstPort 1 } Branch { Points [20, 0] Branch { Points [0, -80] DstBlock "To Float" DstPort 3 } Branch { Points [0, 140] DstBlock "Chan Est Offload" DstPort 2 } } } Line { SrcBlock "Mult by LTF" SrcPort 3 Points [10, 0] Branch { DstBlock "Estimate Buffers" DstPort 3 } Branch { Points [0, 230] DstBlock "Inverter1" DstPort 1 } } Line { SrcBlock "Delay5" SrcPort 1 Points [50, 0] Branch { Points [0, 265] DstBlock "Gateway Out4" DstPort 1 } Branch { Points [100, 0; 0, -60] Branch { Points [0, -140] DstBlock "To Float" DstPort 5 } Branch { DstBlock "Chan Est Offload" DstPort 1 } } } Line { SrcBlock "Delay1" SrcPort 1 Points [25, 0] Branch { Points [145, 0; 0, -100] Branch { DstBlock "Chan Est Offload" DstPort 4 } Branch { Points [0, -135] DstBlock "To Float" DstPort 6 } } Branch { Points [0, 245] Branch { DstBlock "Gateway Out5" DstPort 1 } Branch { Points [0, 100] DstBlock "Gateway Out7" DstPort 1 } } } Line { SrcBlock "Delay2" SrcPort 1 Points [35, 0] Branch { Points [150, 0; 0, -140] Branch { Points [0, -110] DstBlock "To Float" DstPort 7 } Branch { Labels [0, 0] DstBlock "Chan Est Offload" DstPort 5 } } Branch { Points [0, 170] DstBlock "Gateway Out6" DstPort 1 } } Line { SrcBlock "Delay4" SrcPort 1 DstBlock "To Float" DstPort 2 } Line { SrcBlock "Delay3" SrcPort 1 DstBlock "To Float" DstPort 1 } Line { SrcBlock "Gateway Out12" SrcPort 1 DstBlock "Real-Imag to\nComplex2" DstPort 1 } Line { SrcBlock "Gateway Out13" SrcPort 1 DstBlock "Real-Imag to\nComplex2" DstPort 2 } Line { SrcBlock "Real-Imag to\nComplex2" SrcPort 1 DstBlock "To Workspace" DstPort 1 } Line { SrcBlock "Gateway Out7" SrcPort 1 DstBlock "To Workspace1" DstPort 1 } Line { SrcBlock "Logical3" SrcPort 1 DstBlock "Delay1" DstPort 1 } Line { SrcBlock "Inverter1" SrcPort 1 DstBlock "Logical3" DstPort 1 } } } Block { BlockType SubSystem Name "Debug Outputs" SID "550" Ports [4] Position [800, 482, 870, 543] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "Debug Outputs" Location [2, 70, 2464, 1580] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "80" Block { BlockType Inport Name "I" SID "551" Position [390, 423, 420, 437] IconDisplay "Port number" } Block { BlockType Inport Name "Q" SID "552" Position [390, 458, 420, 472] Port "2" IconDisplay "Port number" } Block { BlockType Inport Name "valid" SID "553" Position [380, 533, 410, 547] NamePlacement "alternate" Port "3" IconDisplay "Port number" } Block { BlockType Inport Name "x_ind" SID "554" Position [380, 573, 410, 587] Port "4" IconDisplay "Port number" } Block { BlockType SubSystem Name "4x Buffer" SID "555" Ports [3, 3] Position [1235, 411, 1295, 519] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "4x Buffer" Location [1002, 291, 1570, 505] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "136" Block { BlockType Inport Name "I" SID "556" Position [245, 258, 275, 272] NamePlacement "alternate" IconDisplay "Port number" } Block { BlockType Inport Name "Q" SID "557" Position [245, 283, 275, 297] Port "2" IconDisplay "Port number" } Block { BlockType Inport Name "Vin" SID "558" Position [400, 308, 430, 322] Port "3" IconDisplay "Port number" } Block { BlockType Reference Name "14LSB" SID "559" Ports [1, 1] Position [660, 266, 690, 284] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The output type" " is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.

Hardw" "are notes: In hardware this block costs nothing." nbits "14" boolean_output off mode "Lower Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "0" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "slice" sg_icon_stat "30,18,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 18 18 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 30 30 0 0 ],[0 0 18 18 0 ]);\npatch([10.55 13.44 15.44 17.44 19.44 15.44 12.55 10.55 ],[11.22 11.22" " 13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([12.55 15.44 13.44 10.55 12.55 ],[9.22 9.22 11.22 11.22 9" ".22 ],[0.931 0.946 0.973 ]);\npatch([10.55 13.44 15.44 12.55 10.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);\npatch" "([12.55 19.44 17.44 15.44 13.44 10.55 12.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\nfprint" "f('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('output'" ",1,'[a:b]');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "14MSB" SID "560" Ports [1, 1] Position [660, 241, 690, 259] NamePlacement "alternate" LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The output type" " is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.

Hardw" "are notes: In hardware this block costs nothing." nbits "14" boolean_output off mode "Upper Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "0" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "slice" sg_icon_stat "30,18,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 18 18 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 30 30 0 0 ],[0 0 18 18 0 ]);\npatch([10.55 13.44 15.44 17.44 19.44 15.44 12.55 10.55 ],[11.22 11.22" " 13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([12.55 15.44 13.44 10.55 12.55 ],[9.22 9.22 11.22 11.22 9" ".22 ],[0.931 0.946 0.973 ]);\npatch([10.55 13.44 15.44 12.55 10.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);\npatch" "([12.55 19.44 17.44 15.44 13.44 10.55 12.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\nfprint" "f('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('output'" ",1,'[a:b]');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Concat" SID "561" Ports [2, 1] Position [400, 253, 430, 302] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Concat" SourceType "Xilinx Bus Concatenator Block" infoedit "Concatenates two or more inputs. Output will be cast to an unsigned value with the binary point at z" "ero." num_inputs "2" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "concat" sg_icon_stat "30,49,2,1,white,blue,0,16398980,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 49 49 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 30 30 0 0 ],[0 0 49 49 0 ]);\npatch([6.1 11.88 15.88 19.88 23.88 15.88 10.1 6.1 ],[28.44 28.44 32.4" "4 28.44 32.44 32.44 32.44 28.44 ],[1 1 1 ]);\npatch([10.1 15.88 11.88 6.1 10.1 ],[24.44 24.44 28.44 28.44 24.44 ]," "[0.931 0.946 0.973 ]);\npatch([6.1 11.88 15.88 10.1 6.1 ],[20.44 20.44 24.44 24.44 20.44 ],[1 1 1 ]);\npatch([10.1" " 23.88 19.88 15.88 11.88 6.1 10.1 ],[16.44 16.44 20.44 16.44 20.44 20.44 16.44 ],[0.931 0.946 0.973 ]);\nfprintf('" "','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'hi" "');\ncolor('black');port_label('input',2,'lo');\n\ncolor('black');disp('\\fontsize{20}\\}','texmode','on');\nfprin" "tf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Constant3" SID "562" Ports [0, 1] Position [445, 345, 465, 365] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "1" gui_display_data_type "Boolean" arith_type "Boolean" n_bits "5" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period on period "4" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" sg_icon_stat "20,20,0,1,white,blue,0,1c72b5be,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 20 20 0 0 ],[0 0 20 20 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 20 20 0 0 ],[0 0 20 20 0 ]);\npatch([5.55 8.44 10.44 12.44 14.44 10.44 7.55 5.55 ],[12.22 12.22 14." "22 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([7.55 10.44 8.44 5.55 7.55 ],[10.22 10.22 12.22 12.22 10.22 ]" ",[0.931 0.946 0.973 ]);\npatch([5.55 8.44 10.44 7.55 5.55 ],[8.22 8.22 10.22 10.22 8.22 ],[1 1 1 ]);\npatch([7.55 " "14.44 12.44 10.44 8.44 5.55 7.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.931 0.946 0.973 ]);\nfprintf('','COMME" "NT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'1');\nfpr" "intf('','COMMENT: end icon text');" } Block { BlockType Reference Name "FIFO" SID "563" Ports [3, 3] Position [505, 258, 585, 372] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/FIFO" SourceType "Xilinx FIFO Block Block" mem_type "Block RAM" performance_options "Standard_FIFO" infoedit1 "Available only for V4, V5, V6, V7, K7, A7 and Zynq devices." embedded_registers off depth "64" percent_nbits "1" rst off en off use_dcount off use_percent_full_port off use_almost_empty off almost_empty_thresh "2" use_almost_full off almost_full_thresh "14" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" explicit_period "off" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "fifo" sg_icon_stat "80,114,3,3,white,blue,0,375ec951,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 80 80 0 0 ],[0 0 114 114 0 ],[0.77 0.82 0" ".91 ]);\nplot([0 80 80 0 0 ],[0 0 114 114 0 ]);\npatch([15.525 31.42 42.42 53.42 64.42 42.42 26.525 15.525 ],[69.2" "1 69.21 80.21 69.21 80.21 80.21 80.21 69.21 ],[1 1 1 ]);\npatch([26.525 42.42 31.42 15.525 26.525 ],[58.21 58.21 6" "9.21 69.21 58.21 ],[0.931 0.946 0.973 ]);\npatch([15.525 31.42 42.42 26.525 15.525 ],[47.21 47.21 58.21 58.21 47.2" "1 ],[1 1 1 ]);\npatch([26.525 64.42 53.42 42.42 31.42 15.525 26.525 ],[36.21 36.21 47.21 36.21 47.21 47.21 36.21 ]" ",[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor" "('black');port_label('input',1,'din');\ncolor('black');port_label('input',2,'we');\ncolor('black');port_label('inp" "ut',3,'re');\ncolor('black');port_label('output',1,'dout');\ncolor('black');port_label('output',2,'empty');\ncolor" "('black');port_label('output',3,'full');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Reinterpret" SID "564" Ports [1, 1] Position [310, 255, 340, 275] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Reinterpret" SourceType "Xilinx Type Reinterpreter Block" infoedit "Changes signal type without altering the binary representation. You can change the signal between s" "igned and unsigned, and relocate the binary point.

Hardware notes: In hardware this block costs nothing.
Example: Suppose the input is 6 bits wide, signed, with 2 fractional bits, and the output is forced to unsig" "ned with 0 fractional bits. Then an input of -2.0 (1110.00 in binary 2's complement) becomes an output of 56 (111" "000 in binary)." force_arith_type on arith_type "Unsigned" force_bin_pt on bin_pt "0" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "reinterpret" sg_icon_stat "30,20,1,1,white,blue,0,6b04d0b0,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 20 20 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 30 30 0 0 ],[0 0 20 20 0 ]);\npatch([10.55 13.44 15.44 17.44 19.44 15.44 12.55 10.55 ],[12.22 12.22" " 14.22 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([12.55 15.44 13.44 10.55 12.55 ],[10.22 10.22 12.22 12.22" " 10.22 ],[0.931 0.946 0.973 ]);\npatch([10.55 13.44 15.44 12.55 10.55 ],[8.22 8.22 10.22 10.22 8.22 ],[1 1 1 ]);\n" "patch([12.55 19.44 17.44 15.44 13.44 10.55 12.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.931 0.946 0.973 ]);\nf" "printf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');disp('reinte" "rpret');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Reinterpret1" SID "565" Ports [1, 1] Position [310, 280, 340, 300] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Reinterpret" SourceType "Xilinx Type Reinterpreter Block" infoedit "Changes signal type without altering the binary representation. You can change the signal between s" "igned and unsigned, and relocate the binary point.

Hardware notes: In hardware this block costs nothing.
Example: Suppose the input is 6 bits wide, signed, with 2 fractional bits, and the output is forced to unsig" "ned with 0 fractional bits. Then an input of -2.0 (1110.00 in binary 2's complement) becomes an output of 56 (111" "000 in binary)." force_arith_type on arith_type "Unsigned" force_bin_pt on bin_pt "0" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "reinterpret" sg_icon_stat "30,20,1,1,white,blue,0,6b04d0b0,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 20 20 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 30 30 0 0 ],[0 0 20 20 0 ]);\npatch([10.55 13.44 15.44 17.44 19.44 15.44 12.55 10.55 ],[12.22 12.22" " 14.22 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([12.55 15.44 13.44 10.55 12.55 ],[10.22 10.22 12.22 12.22" " 10.22 ],[0.931 0.946 0.973 ]);\npatch([10.55 13.44 15.44 12.55 10.55 ],[8.22 8.22 10.22 10.22 8.22 ],[1 1 1 ]);\n" "patch([12.55 19.44 17.44 15.44 13.44 10.55 12.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.931 0.946 0.973 ]);\nf" "printf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');disp('reinte" "rpret');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Reinterpret2" SID "566" Ports [1, 1] Position [730, 240, 760, 260] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Reinterpret" SourceType "Xilinx Type Reinterpreter Block" infoedit "Changes signal type without altering the binary representation. You can change the signal between s" "igned and unsigned, and relocate the binary point.

Hardware notes: In hardware this block costs nothing.
Example: Suppose the input is 6 bits wide, signed, with 2 fractional bits, and the output is forced to unsig" "ned with 0 fractional bits. Then an input of -2.0 (1110.00 in binary 2's complement) becomes an output of 56 (111" "000 in binary)." force_arith_type on arith_type "Signed (2's comp)" force_bin_pt on bin_pt "13" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "reinterpret" sg_icon_stat "30,20,1,1,white,blue,0,6b04d0b0,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 20 20 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 30 30 0 0 ],[0 0 20 20 0 ]);\npatch([10.55 13.44 15.44 17.44 19.44 15.44 12.55 10.55 ],[12.22 12.22" " 14.22 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([12.55 15.44 13.44 10.55 12.55 ],[10.22 10.22 12.22 12.22" " 10.22 ],[0.931 0.946 0.973 ]);\npatch([10.55 13.44 15.44 12.55 10.55 ],[8.22 8.22 10.22 10.22 8.22 ],[1 1 1 ]);\n" "patch([12.55 19.44 17.44 15.44 13.44 10.55 12.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.931 0.946 0.973 ]);\nf" "printf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');disp('reinte" "rpret');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Reinterpret3" SID "567" Ports [1, 1] Position [730, 265, 760, 285] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Reinterpret" SourceType "Xilinx Type Reinterpreter Block" infoedit "Changes signal type without altering the binary representation. You can change the signal between s" "igned and unsigned, and relocate the binary point.

Hardware notes: In hardware this block costs nothing.
Example: Suppose the input is 6 bits wide, signed, with 2 fractional bits, and the output is forced to unsig" "ned with 0 fractional bits. Then an input of -2.0 (1110.00 in binary 2's complement) becomes an output of 56 (111" "000 in binary)." force_arith_type on arith_type "Signed (2's comp)" force_bin_pt on bin_pt "13" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "reinterpret" sg_icon_stat "30,20,1,1,white,blue,0,6b04d0b0,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 20 20 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 30 30 0 0 ],[0 0 20 20 0 ]);\npatch([10.55 13.44 15.44 17.44 19.44 15.44 12.55 10.55 ],[12.22 12.22" " 14.22 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([12.55 15.44 13.44 10.55 12.55 ],[10.22 10.22 12.22 12.22" " 10.22 ],[0.931 0.946 0.973 ]);\npatch([10.55 13.44 15.44 12.55 10.55 ],[8.22 8.22 10.22 10.22 8.22 ],[1 1 1 ]);\n" "patch([12.55 19.44 17.44 15.44 13.44 10.55 12.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.931 0.946 0.973 ]);\nf" "printf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');disp('reinte" "rpret');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Up Sample" SID "568" Ports [1, 1] Position [815, 237, 840, 263] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Up Sample" SourceType "Xilinx Up Sampler Block" infoedit "Up samples input data. Inserted values can be zeros or copies of the most recent input sample.
<" "br>Hardware notes: No hardware is needed if inserted values are copies of the input sample; otherwise, a mux and s" "ingle bit flip-flop are used." sample_ratio "4" copy_samples on en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "usamp" sg_icon_stat "25,26,1,1,white,blue,0,a300b05e,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 26 26 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 25 25 0 0 ],[0 0 26 26 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[16.33 16.33 " "19.33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[13.33 13.33 16.33 16.33 1" "3.33 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[10.33 10.33 13.33 13.33 10.33 ],[1 1 1 ]);\n" "patch([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[7.33 7.33 10.33 7.33 10.33 10.33 7.33 ],[0.931 0.946 0.973 ]);\n" "fprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');disp('{\\fo" "ntsize{14pt}\\bf\\uparrow}4','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Up Sample1" SID "569" Ports [1, 1] Position [815, 262, 840, 288] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Up Sample" SourceType "Xilinx Up Sampler Block" infoedit "Up samples input data. Inserted values can be zeros or copies of the most recent input sample.
<" "br>Hardware notes: No hardware is needed if inserted values are copies of the input sample; otherwise, a mux and s" "ingle bit flip-flop are used." sample_ratio "4" copy_samples on en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "usamp" sg_icon_stat "25,26,1,1,white,blue,0,a300b05e,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 26 26 0 ],[0.77 0.82 0.9" "1 ]);\nplot([0 25 25 0 0 ],[0 0 26 26 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[16.33 16.33 " "19.33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[13.33 13.33 16.33 16.33 1" "3.33 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[10.33 10.33 13.33 13.33 10.33 ],[1 1 1 ]);\n" "patch([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[7.33 7.33 10.33 7.33 10.33 10.33 7.33 ],[0.931 0.946 0.973 ]);\n" "fprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');disp('{\\fo" "ntsize{14pt}\\bf\\uparrow}4','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Outport Name " I" SID "570" Position [875, 243, 905, 257] NamePlacement "alternate" IconDisplay "Port number" } Block { BlockType Outport Name " Q" SID "571" Position [875, 268, 905, 282] Port "2" IconDisplay "Port number" } Block { BlockType Outport Name "#Vout" SID "572" Position [875, 308, 905, 322] Port "3" IconDisplay "Port number" } Line { SrcBlock "Constant3" SrcPort 1 DstBlock "FIFO" DstPort 3 } Line { SrcBlock "Concat" SrcPort 1 DstBlock "FIFO" DstPort 1 } Line { SrcBlock "I" SrcPort 1 DstBlock "Reinterpret" DstPort 1 } Line { SrcBlock "14MSB" SrcPort 1 DstBlock "Reinterpret2" DstPort 1 } Line { SrcBlock "Q" SrcPort 1 DstBlock "Reinterpret1" DstPort 1 } Line { SrcBlock "14LSB" SrcPort 1 DstBlock "Reinterpret3" DstPort 1 } Line { SrcBlock "Vin" SrcPort 1 DstBlock "FIFO" DstPort 2 } Line { SrcBlock "FIFO" SrcPort 2 DstBlock "#Vout" DstPort 1 } Line { SrcBlock "Reinterpret" SrcPort 1 DstBlock "Concat" DstPort 1 } Line { SrcBlock "Reinterpret1" SrcPort 1 DstBlock "Concat" DstPort 2 } Line { SrcBlock "Reinterpret2" SrcPort 1 DstBlock "Up Sample" DstPort 1 } Line { SrcBlock "Reinterpret3" SrcPort 1 DstBlock "Up Sample1" DstPort 1 } Line { SrcBlock "Up Sample" SrcPort 1 DstBlock " I" DstPort 1 } Line { SrcBlock "Up Sample1" SrcPort 1 DstBlock " Q" DstPort 1 } Line { SrcBlock "FIFO" SrcPort 1 Points [35, 0] Branch { DstBlock "14LSB" DstPort 1 } Branch { Points [0, -25] DstBlock "14MSB" DstPort 1 } } } } Block { BlockType Reference Name "Constant" SID "573" Ports [0, 1] Position [465, 597, 495, 623] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "0" gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "1" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" sg_icon_stat "30,26,0,1,white,blue,0,bf4ddd8b,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 26 26 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 26 26 0 ]);\npatch([8.325 12.66 15.66 18.66 21.66 15.66 11.325 8.325 ],[" "16.33 16.33 19.33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([11.325 15.66 12.66 8.325 11.325 ],[13.33 1" "3.33 16.33 16.33 13.33 ],[0.931 0.946 0.973 ]);\npatch([8.325 12.66 15.66 11.325 8.325 ],[10.33 10.33 13.33 13." "33 10.33 ],[1 1 1 ]);\npatch([11.325 21.66 18.66 15.66 12.66 8.325 11.325 ],[7.33 7.33 10.33 7.33 10.33 10.33 7" ".33 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text')" ";\ncolor('black');port_label('output',1,'0');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Constant1" SID "574" Ports [0, 1] Position [465, 677, 495, 703] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "27" gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "5" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" sg_icon_stat "30,26,0,1,white,blue,0,63edda7d,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 26 26 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 26 26 0 ]);\npatch([8.325 12.66 15.66 18.66 21.66 15.66 11.325 8.325 ],[" "16.33 16.33 19.33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([11.325 15.66 12.66 8.325 11.325 ],[13.33 1" "3.33 16.33 16.33 13.33 ],[0.931 0.946 0.973 ]);\npatch([8.325 12.66 15.66 11.325 8.325 ],[10.33 10.33 13.33 13." "33 10.33 ],[1 1 1 ]);\npatch([11.325 21.66 18.66 15.66 12.66 8.325 11.325 ],[7.33 7.33 10.33 7.33 10.33 10.33 7" ".33 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text')" ";\ncolor('black');port_label('output',1,'27');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Constant2" SID "575" Ports [0, 1] Position [465, 742, 495, 768] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "37" gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "6" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" sg_icon_stat "30,26,0,1,white,blue,0,cd6148db,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 26 26 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 26 26 0 ]);\npatch([8.325 12.66 15.66 18.66 21.66 15.66 11.325 8.325 ],[" "16.33 16.33 19.33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([11.325 15.66 12.66 8.325 11.325 ],[13.33 1" "3.33 16.33 16.33 13.33 ],[0.931 0.946 0.973 ]);\npatch([8.325 12.66 15.66 11.325 8.325 ],[10.33 10.33 13.33 13." "33 10.33 ],[1 1 1 ]);\npatch([11.325 21.66 18.66 15.66 12.66 8.325 11.325 ],[7.33 7.33 10.33 7.33 10.33 10.33 7" ".33 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text')" ";\ncolor('black');port_label('output',1,'37');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Constant3" SID "8474" Ports [0, 1] Position [465, 817, 495, 843] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "29" gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "5" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" sg_icon_stat "30,26,0,1,white,blue,0,c108aa3c,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 26 26 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 26 26 0 ]);\npatch([8.325 12.66 15.66 18.66 21.66 15.66 11.325 8.325 ],[" "16.33 16.33 19.33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([11.325 15.66 12.66 8.325 11.325 ],[13.33 1" "3.33 16.33 16.33 13.33 ],[0.931 0.946 0.973 ]);\npatch([8.325 12.66 15.66 11.325 8.325 ],[10.33 10.33 13.33 13." "33 10.33 ],[1 1 1 ]);\npatch([11.325 21.66 18.66 15.66 12.66 8.325 11.325 ],[7.33 7.33 10.33 7.33 10.33 10.33 7" ".33 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text')" ";\ncolor('black');port_label('output',1,'29');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Constant4" SID "8475" Ports [0, 1] Position [465, 882, 495, 908] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "35" gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "6" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" sg_icon_stat "30,26,0,1,white,blue,0,c201f606,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 26 26 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 26 26 0 ]);\npatch([8.325 12.66 15.66 18.66 21.66 15.66 11.325 8.325 ],[" "16.33 16.33 19.33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([11.325 15.66 12.66 8.325 11.325 ],[13.33 1" "3.33 16.33 16.33 13.33 ],[0.931 0.946 0.973 ]);\npatch([8.325 12.66 15.66 11.325 8.325 ],[10.33 10.33 13.33 13." "33 10.33 ],[1 1 1 ]);\npatch([11.325 21.66 18.66 15.66 12.66 8.325 11.325 ],[7.33 7.33 10.33 7.33 10.33 10.33 7" ".33 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text')" ";\ncolor('black');port_label('output',1,'35');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Scope Name "Debug EQ IQ" SID "576" Ports [7] Position [1750, 613, 1790, 787] ZOrder -3 Floating off Location [5, 430, 2480, 1588] Open off NumInputPorts "7" ZoomMode "xonly" List { ListType AxesTitles axes1 "%" axes2 "%" axes3 "%" axes4 "%" axes5 "%" axes6 "%" axes7 "%" } List { ListType ScopeGraphics FigureColor "[0.5 0.5 0.5]" AxesColor "[0 0 0]" AxesTickColor "[1 1 1]" LineColors "[1 1 0;1 0 1;0 1 1;1 0 0;0 1 0;0 0 1]" LineStyles "-|-|-|-|-|-" LineWidths "[0.5 0.5 0.5 0.5 0.5 0.5]" MarkerStyles "none|none|none|none|none|none" } YMin "-1.1~-1~-1.1~-1~-5~-5~-5" YMax "1.1~1~1.2~1~5~5~5" SaveName "ScopeData13" DataFormat "StructureWithTime" LimitDataPoints off SampleTime "0" } Block { BlockType Reference Name "Delay" SID "577" Ports [1, 1] Position [1150, 668, 1180, 692] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flo" "p." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en off latency "1" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" sg_icon_stat "30,24,1,1,white,blue,0,07b98262,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 24 24 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 24 24 0 ]);\npatch([8.325 12.66 15.66 18.66 21.66 15.66 11.325 8.325 ],[" "15.33 15.33 18.33 15.33 18.33 18.33 18.33 15.33 ],[1 1 1 ]);\npatch([11.325 15.66 12.66 8.325 11.325 ],[12.33 1" "2.33 15.33 15.33 12.33 ],[0.931 0.946 0.973 ]);\npatch([8.325 12.66 15.66 11.325 8.325 ],[9.33 9.33 12.33 12.33" " 9.33 ],[1 1 1 ]);\npatch([11.325 21.66 18.66 15.66 12.66 8.325 11.325 ],[6.33 6.33 9.33 6.33 9.33 9.33 6.33 ]," "[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n" "color('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Delay1" SID "578" Ports [1, 1] Position [465, 528, 495, 552] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flo" "p." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en off latency "1" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" sg_icon_stat "30,24,1,1,white,blue,0,07b98262,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 24 24 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 24 24 0 ]);\npatch([8.325 12.66 15.66 18.66 21.66 15.66 11.325 8.325 ],[" "15.33 15.33 18.33 15.33 18.33 18.33 18.33 15.33 ],[1 1 1 ]);\npatch([11.325 15.66 12.66 8.325 11.325 ],[12.33 1" "2.33 15.33 15.33 12.33 ],[0.931 0.946 0.973 ]);\npatch([8.325 12.66 15.66 11.325 8.325 ],[9.33 9.33 12.33 12.33" " 9.33 ],[1 1 1 ]);\npatch([11.325 21.66 18.66 15.66 12.66 8.325 11.325 ],[6.33 6.33 9.33 6.33 9.33 9.33 6.33 ]," "[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n" "color('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType From Name "From" SID "8479" Position [615, 613, 780, 637] ZOrder -9 ShowName off GotoTag "RX_PHY_MODE_11N_AC" TagVisibility "global" } Block { BlockType Reference Name "Gateway Out12" SID "579" Ports [1, 1] Position [1645, 1004, 1680, 1016] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of t" "ype Simulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become t" "op level output ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0" ".88 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ]" ",[7.11 7.11 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7." "11 7.11 6.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1" " 1 1 ]);\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0." "964 0.964 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black" "');port_label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nf" "printf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out13" SID "580" Ports [1, 1] Position [1645, 1019, 1680, 1031] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of t" "ype Simulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become t" "op level output ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0" ".88 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ]" ",[7.11 7.11 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7." "11 7.11 6.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1" " 1 1 ]);\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0." "964 0.964 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black" "');port_label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nf" "printf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out8" SID "581" Ports [1, 1] Position [1645, 934, 1680, 946] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of t" "ype Simulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become t" "op level output ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "35,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 12 12 0 ],[0.88 0" ".88 0.88 ]);\nplot([0 35 35 0 0 ],[0 0 12 12 0 ]);\npatch([14.775 16.22 17.22 18.22 19.22 17.22 15.775 14.775 ]" ",[7.11 7.11 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([15.775 17.22 16.22 14.775 15.775 ],[6.11 6.11 7." "11 7.11 6.11 ],[0.964 0.964 0.964 ]);\npatch([14.775 16.22 17.22 15.775 14.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1" " 1 1 ]);\npatch([15.775 19.22 18.22 17.22 16.22 14.775 15.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0." "964 0.964 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black" "');port_label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nf" "printf('','COMMENT: end icon text');" } Block { BlockType Goto Name "Goto" SID "582" Position [1475, 571, 1545, 589] ZOrder -10 ShowName off GotoTag "CS_EQ_I" TagVisibility "global" } Block { BlockType Goto Name "Goto1" SID "583" Position [1475, 621, 1545, 639] ZOrder -10 ShowName off GotoTag "CS_EQ_Q" TagVisibility "global" } Block { BlockType Goto Name "Goto2" SID "584" Position [1475, 671, 1545, 689] ZOrder -10 ShowName off GotoTag "CS_EQ_Valid" TagVisibility "global" } Block { BlockType Reference Name "Inverter1" SID "585" Ports [1, 1] Position [1065, 576, 1100, 594] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Inverter" SourceType "Xilinx Inverter Block" infoedit "Bitwise logical negation (one's complement) operator." en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "inv" sg_icon_stat "35,18,1,1,white,blue,0,267846e5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 18 18 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 18 18 0 ]);\npatch([12.55 15.44 17.44 19.44 21.44 17.44 14.55 12.55 ],[1" "1.22 11.22 13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([14.55 17.44 15.44 12.55 14.55 ],[9.22 9.22 " "11.22 11.22 9.22 ],[0.931 0.946 0.973 ]);\npatch([12.55 15.44 17.44 14.55 12.55 ],[7.22 7.22 9.22 9.22 7.22 ],[" "1 1 1 ]);\npatch([14.55 21.44 19.44 17.44 15.44 12.55 14.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.94" "6 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('bla" "ck');disp('not');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical" SID "586" Ports [3, 1] Position [875, 555, 930, 615] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "AND" inputs "3" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" sg_icon_stat "55,60,3,1,white,blue,0,98d76266,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 55 55 0 0 ],[0 0 60 60 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 55 55 0 0 ],[0 0 60 60 0 ]);\npatch([11.425 21.54 28.54 35.54 42.54 28.54 18.425 11.425 ]" ",[37.77 37.77 44.77 37.77 44.77 44.77 44.77 37.77 ],[1 1 1 ]);\npatch([18.425 28.54 21.54 11.425 18.425 ],[30.7" "7 30.77 37.77 37.77 30.77 ],[0.931 0.946 0.973 ]);\npatch([11.425 21.54 28.54 18.425 11.425 ],[23.77 23.77 30.7" "7 30.77 23.77 ],[1 1 1 ]);\npatch([18.425 42.54 35.54 28.54 21.54 11.425 18.425 ],[16.77 16.77 23.77 16.77 23.7" "7 23.77 16.77 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin i" "con text');\n\n\n\n\ncolor('black');disp('and');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical1" SID "587" Ports [2, 1] Position [630, 647, 660, 778] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "OR" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" sg_icon_stat "30,131,2,1,white,blue,0,7ede7d88,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 131 131 0 ],[0.77" " 0.82 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 131 131 0 ]);\npatch([6.1 11.88 15.88 19.88 23.88 15.88 10.1 6.1 ],[69" ".44 69.44 73.44 69.44 73.44 73.44 73.44 69.44 ],[1 1 1 ]);\npatch([10.1 15.88 11.88 6.1 10.1 ],[65.44 65.44 69." "44 69.44 65.44 ],[0.931 0.946 0.973 ]);\npatch([6.1 11.88 15.88 10.1 6.1 ],[61.44 61.44 65.44 65.44 61.44 ],[1 " "1 1 ]);\npatch([10.1 23.88 19.88 15.88 11.88 6.1 10.1 ],[57.44 57.44 61.44 57.44 61.44 61.44 57.44 ],[0.931 0.9" "46 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\ncolor('" "black');disp('or');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical2" SID "8476" Ports [2, 1] Position [630, 787, 660, 918] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "OR" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" sg_icon_stat "30,131,2,1,white,blue,0,7ede7d88,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 131 131 0 ],[0.77" " 0.82 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 131 131 0 ]);\npatch([6.1 11.88 15.88 19.88 23.88 15.88 10.1 6.1 ],[69" ".44 69.44 73.44 69.44 73.44 73.44 73.44 69.44 ],[1 1 1 ]);\npatch([10.1 15.88 11.88 6.1 10.1 ],[65.44 65.44 69." "44 69.44 65.44 ],[0.931 0.946 0.973 ]);\npatch([6.1 11.88 15.88 10.1 6.1 ],[61.44 61.44 65.44 65.44 61.44 ],[1 " "1 1 ]);\npatch([10.1 23.88 19.88 15.88 11.88 6.1 10.1 ],[57.44 57.44 61.44 57.44 61.44 61.44 57.44 ],[0.931 0.9" "46 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\ncolor('" "black');disp('or');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Mux" SID "8480" Ports [3, 1] Position [815, 678, 845, 812] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Mux" SourceType "Xilinx Bus Multiplexer Block" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "14" quantization "Truncate" overflow "Wrap" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "mux" sg_icon_stat "30,134,3,1,white,blue,3,eb98d690,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 19.1429 114.857 134" " 0 ],[0.77 0.82 0.91 ]);\nplot([0 30 30 0 0 ],[0 19.1429 114.857 134 0 ]);\npatch([6.1 11.88 15.88 19.88 23.88 " "15.88 10.1 6.1 ],[71.44 71.44 75.44 71.44 75.44 75.44 75.44 71.44 ],[1 1 1 ]);\npatch([10.1 15.88 11.88 6.1 10." "1 ],[67.44 67.44 71.44 71.44 67.44 ],[0.931 0.946 0.973 ]);\npatch([6.1 11.88 15.88 10.1 6.1 ],[63.44 63.44 67." "44 67.44 63.44 ],[1 1 1 ]);\npatch([10.1 23.88 19.88 15.88 11.88 6.1 10.1 ],[59.44 59.44 63.44 59.44 63.44 63.4" "4 59.44 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon te" "xt');\ncolor('black');port_label('input',1,'sel');\ncolor('black');port_label('input',2,'d0');\ncolor('black');" "port_label('input',3,'d1');\n\ncolor('black');disp('\\bf{}','texmode','on');\nfprintf('','COMMENT: end icon tex" "t');" } Block { BlockType RealImagToComplex Name "Real-Imag to\nComplex" SID "588" Ports [2, 1] Position [1720, 1003, 1750, 1032] ZOrder -21 Input "Real and imag" } Block { BlockType Reference Name "Register" SID "589" Ports [1, 1] Position [465, 565, 495, 595] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "30,30,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 30 30 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 30 30 0 ]);\npatch([6.1 11.88 15.88 19.88 23.88 15.88 10.1 6.1 ],[19.44 " "19.44 23.44 19.44 23.44 23.44 23.44 19.44 ],[1 1 1 ]);\npatch([10.1 15.88 11.88 6.1 10.1 ],[15.44 15.44 19.44 1" "9.44 15.44 ],[0.931 0.946 0.973 ]);\npatch([6.1 11.88 15.88 10.1 6.1 ],[11.44 11.44 15.44 15.44 11.44 ],[1 1 1 " "]);\npatch([10.1 23.88 19.88 15.88 11.88 6.1 10.1 ],[7.44 7.44 11.44 7.44 11.44 11.44 7.44 ],[0.931 0.946 0.973" " ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_l" "abel('input',1,'d');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');" "\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register1" SID "590" Ports [1, 1] Position [465, 415, 495, 445] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "30,30,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 30 30 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 30 30 0 ]);\npatch([6.1 11.88 15.88 19.88 23.88 15.88 10.1 6.1 ],[19.44 " "19.44 23.44 19.44 23.44 23.44 23.44 19.44 ],[1 1 1 ]);\npatch([10.1 15.88 11.88 6.1 10.1 ],[15.44 15.44 19.44 1" "9.44 15.44 ],[0.931 0.946 0.973 ]);\npatch([6.1 11.88 15.88 10.1 6.1 ],[11.44 11.44 15.44 15.44 11.44 ],[1 1 1 " "]);\npatch([10.1 23.88 19.88 15.88 11.88 6.1 10.1 ],[7.44 7.44 11.44 7.44 11.44 11.44 7.44 ],[0.931 0.946 0.973" " ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_l" "abel('input',1,'d');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');" "\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register2" SID "591" Ports [1, 1] Position [465, 450, 495, 480] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "30,30,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 30 30 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 30 30 0 ]);\npatch([6.1 11.88 15.88 19.88 23.88 15.88 10.1 6.1 ],[19.44 " "19.44 23.44 19.44 23.44 23.44 23.44 19.44 ],[1 1 1 ]);\npatch([10.1 15.88 11.88 6.1 10.1 ],[15.44 15.44 19.44 1" "9.44 15.44 ],[0.931 0.946 0.973 ]);\npatch([6.1 11.88 15.88 10.1 6.1 ],[11.44 11.44 15.44 15.44 11.44 ],[1 1 1 " "]);\npatch([10.1 23.88 19.88 15.88 11.88 6.1 10.1 ],[7.44 7.44 11.44 7.44 11.44 11.44 7.44 ],[0.931 0.946 0.973" " ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_l" "abel('input',1,'d');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');" "\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register3" SID "592" Ports [2, 1] Position [1145, 562, 1190, 593] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst on en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "45,31,2,1,white,blue,0,140cc11c,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 31 31 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 45 45 0 0 ],[0 0 31 31 0 ]);\npatch([13.1 18.88 22.88 26.88 30.88 22.88 17.1 13.1 ],[19.4" "4 19.44 23.44 19.44 23.44 23.44 23.44 19.44 ],[1 1 1 ]);\npatch([17.1 22.88 18.88 13.1 17.1 ],[15.44 15.44 19.4" "4 19.44 15.44 ],[0.931 0.946 0.973 ]);\npatch([13.1 18.88 22.88 17.1 13.1 ],[11.44 11.44 15.44 15.44 11.44 ],[1" " 1 1 ]);\npatch([17.1 30.88 26.88 22.88 18.88 13.1 17.1 ],[7.44 7.44 11.44 7.44 11.44 11.44 7.44 ],[0.931 0.946" " 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');" "port_label('input',1,'d');\ncolor('black');port_label('input',2,'rst');\ncolor('black');port_label('output',1,'" "q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register4" SID "593" Ports [2, 1] Position [1385, 422, 1430, 453] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst on en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "45,31,2,1,white,blue,0,140cc11c,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 31 31 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 45 45 0 0 ],[0 0 31 31 0 ]);\npatch([13.1 18.88 22.88 26.88 30.88 22.88 17.1 13.1 ],[19.4" "4 19.44 23.44 19.44 23.44 23.44 23.44 19.44 ],[1 1 1 ]);\npatch([17.1 22.88 18.88 13.1 17.1 ],[15.44 15.44 19.4" "4 19.44 15.44 ],[0.931 0.946 0.973 ]);\npatch([13.1 18.88 22.88 17.1 13.1 ],[11.44 11.44 15.44 15.44 11.44 ],[1" " 1 1 ]);\npatch([17.1 30.88 26.88 22.88 18.88 13.1 17.1 ],[7.44 7.44 11.44 7.44 11.44 11.44 7.44 ],[0.931 0.946" " 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');" "port_label('input',1,'d');\ncolor('black');port_label('input',2,'rst');\ncolor('black');port_label('output',1,'" "q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register5" SID "594" Ports [2, 1] Position [1385, 457, 1430, 488] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst on en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "45,31,2,1,white,blue,0,140cc11c,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 31 31 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 45 45 0 0 ],[0 0 31 31 0 ]);\npatch([13.1 18.88 22.88 26.88 30.88 22.88 17.1 13.1 ],[19.4" "4 19.44 23.44 19.44 23.44 23.44 23.44 19.44 ],[1 1 1 ]);\npatch([17.1 22.88 18.88 13.1 17.1 ],[15.44 15.44 19.4" "4 19.44 15.44 ],[0.931 0.946 0.973 ]);\npatch([13.1 18.88 22.88 17.1 13.1 ],[11.44 11.44 15.44 15.44 11.44 ],[1" " 1 1 ]);\npatch([17.1 30.88 26.88 22.88 18.88 13.1 17.1 ],[7.44 7.44 11.44 7.44 11.44 11.44 7.44 ],[0.931 0.946" " 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');" "port_label('input',1,'d');\ncolor('black');port_label('input',2,'rst');\ncolor('black');port_label('output',1,'" "q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register6" SID "595" Ports [2, 1] Position [1145, 612, 1190, 643] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst on en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "45,31,2,1,white,blue,0,140cc11c,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 31 31 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 45 45 0 0 ],[0 0 31 31 0 ]);\npatch([13.1 18.88 22.88 26.88 30.88 22.88 17.1 13.1 ],[19.4" "4 19.44 23.44 19.44 23.44 23.44 23.44 19.44 ],[1 1 1 ]);\npatch([17.1 22.88 18.88 13.1 17.1 ],[15.44 15.44 19.4" "4 19.44 15.44 ],[0.931 0.946 0.973 ]);\npatch([13.1 18.88 22.88 17.1 13.1 ],[11.44 11.44 15.44 15.44 11.44 ],[1" " 1 1 ]);\npatch([17.1 30.88 26.88 22.88 18.88 13.1 17.1 ],[7.44 7.44 11.44 7.44 11.44 11.44 7.44 ],[0.931 0.946" " 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');" "port_label('input',1,'d');\ncolor('black');port_label('input',2,'rst');\ncolor('black');port_label('output',1,'" "q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register7" SID "596" Ports [1, 1] Position [1495, 425, 1525, 455] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "30,30,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 30 30 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 30 30 0 ]);\npatch([6.1 11.88 15.88 19.88 23.88 15.88 10.1 6.1 ],[19.44 " "19.44 23.44 19.44 23.44 23.44 23.44 19.44 ],[1 1 1 ]);\npatch([10.1 15.88 11.88 6.1 10.1 ],[15.44 15.44 19.44 1" "9.44 15.44 ],[0.931 0.946 0.973 ]);\npatch([6.1 11.88 15.88 10.1 6.1 ],[11.44 11.44 15.44 15.44 11.44 ],[1 1 1 " "]);\npatch([10.1 23.88 19.88 15.88 11.88 6.1 10.1 ],[7.44 7.44 11.44 7.44 11.44 11.44 7.44 ],[0.931 0.946 0.973" " ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_l" "abel('input',1,'d');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');" "\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register8" SID "597" Ports [1, 1] Position [1495, 460, 1525, 490] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" sg_icon_stat "30,30,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 30 30 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 30 30 0 ]);\npatch([6.1 11.88 15.88 19.88 23.88 15.88 10.1 6.1 ],[19.44 " "19.44 23.44 19.44 23.44 23.44 23.44 19.44 ],[1 1 1 ]);\npatch([10.1 15.88 11.88 6.1 10.1 ],[15.44 15.44 19.44 1" "9.44 15.44 ],[0.931 0.946 0.973 ]);\npatch([6.1 11.88 15.88 10.1 6.1 ],[11.44 11.44 15.44 15.44 11.44 ],[1 1 1 " "]);\npatch([10.1 23.88 19.88 15.88 11.88 6.1 10.1 ],[7.44 7.44 11.44 7.44 11.44 11.44 7.44 ],[0.931 0.946 0.973" " ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_l" "abel('input',1,'d');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');" "\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Relational" SID "598" Ports [2, 1] Position [565, 567, 600, 623] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Relational" SourceType "Xilinx Arithmetic Relational Operator Block" mode "a!=b" en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "relational" sg_icon_stat "35,56,2,1,white,blue,0,850de6e7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 56 56 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 56 56 0 ]);\npatch([5.875 13.1 18.1 23.1 28.1 18.1 10.875 5.875 ],[33.55" " 33.55 38.55 33.55 38.55 38.55 38.55 33.55 ],[1 1 1 ]);\npatch([10.875 18.1 13.1 5.875 10.875 ],[28.55 28.55 33" ".55 33.55 28.55 ],[0.931 0.946 0.973 ]);\npatch([5.875 13.1 18.1 10.875 5.875 ],[23.55 23.55 28.55 28.55 23.55 " "],[1 1 1 ]);\npatch([10.875 28.1 23.1 18.1 13.1 5.875 10.875 ],[18.55 18.55 23.55 18.55 23.55 23.55 18.55 ],[0." "931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor(" "'black');port_label('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('outp" "ut',1,'\\bfa \\neq b','texmode','on');\ncolor('black');disp(' ');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Relational1" SID "599" Ports [2, 1] Position [565, 650, 600, 705] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Relational" SourceType "Xilinx Arithmetic Relational Operator Block" mode "ab" en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "relational" sg_icon_stat "35,55,2,1,white,blue,0,b5131c97,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 55 55 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 55 55 0 ]);\npatch([5.875 13.1 18.1 23.1 28.1 18.1 10.875 5.875 ],[32.55" " 32.55 37.55 32.55 37.55 37.55 37.55 32.55 ],[1 1 1 ]);\npatch([10.875 18.1 13.1 5.875 10.875 ],[27.55 27.55 32" ".55 32.55 27.55 ],[0.931 0.946 0.973 ]);\npatch([5.875 13.1 18.1 10.875 5.875 ],[22.55 22.55 27.55 27.55 22.55 " "],[1 1 1 ]);\npatch([10.875 28.1 23.1 18.1 13.1 5.875 10.875 ],[17.55 17.55 22.55 17.55 22.55 22.55 17.55 ],[0." "931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor(" "'black');port_label('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('outp" "ut',1,'\\bfa > b','texmode','on');\ncolor('black');disp(' ');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Relational3" SID "8477" Ports [2, 1] Position [565, 790, 600, 845] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Relational" SourceType "Xilinx Arithmetic Relational Operator Block" mode "ab" en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "relational" sg_icon_stat "35,55,2,1,white,blue,0,b5131c97,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 55 55 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 55 55 0 ]);\npatch([5.875 13.1 18.1 23.1 28.1 18.1 10.875 5.875 ],[32.55" " 32.55 37.55 32.55 37.55 37.55 37.55 32.55 ],[1 1 1 ]);\npatch([10.875 18.1 13.1 5.875 10.875 ],[27.55 27.55 32" ".55 32.55 27.55 ],[0.931 0.946 0.973 ]);\npatch([5.875 13.1 18.1 10.875 5.875 ],[22.55 22.55 27.55 27.55 22.55 " "],[1 1 1 ]);\npatch([10.875 28.1 23.1 18.1 13.1 5.875 10.875 ],[17.55 17.55 22.55 17.55 22.55 22.55 17.55 ],[0." "931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor(" "'black');port_label('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('outp" "ut',1,'\\bfa > b','texmode','on');\ncolor('black');disp(' ');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "To FP1" SID "601" Ports [1, 1] Position [1030, 458, 1060, 472] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do" " not." gui_display_data_type "Fixed-point" arith_type "Signed (2's comp)" n_bits "14" bin_pt "13" float_type "Single" exp_bits "8" fraction_bits "24" quantization "Truncate" overflow "Saturate" en off latency "0" dbl_ovrd off pipeline off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "convert" sg_icon_stat "30,14,1,1,white,blue,0,edca21da,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 14 14 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 14 14 0 ]);\npatch([10.55 13.44 15.44 17.44 19.44 15.44 12.55 10.55 ],[9" ".22 9.22 11.22 9.22 11.22 11.22 11.22 9.22 ],[1 1 1 ]);\npatch([12.55 15.44 13.44 10.55 12.55 ],[7.22 7.22 9.22" " 9.22 7.22 ],[0.931 0.946 0.973 ]);\npatch([10.55 13.44 15.44 12.55 10.55 ],[5.22 5.22 7.22 7.22 5.22 ],[1 1 1 " "]);\npatch([12.55 19.44 17.44 15.44 13.44 10.55 12.55 ],[3.22 3.22 5.22 3.22 5.22 5.22 3.22 ],[0.931 0.946 0.97" "3 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');por" "t_label('output',1,'cast');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "To FP4" SID "602" Ports [1, 1] Position [1030, 423, 1060, 437] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do" " not." gui_display_data_type "Fixed-point" arith_type "Signed (2's comp)" n_bits "14" bin_pt "13" float_type "Single" exp_bits "8" fraction_bits "24" quantization "Truncate" overflow "Saturate" en off latency "0" dbl_ovrd off pipeline off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "convert" sg_icon_stat "30,14,1,1,white,blue,0,edca21da,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 14 14 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 14 14 0 ]);\npatch([10.55 13.44 15.44 17.44 19.44 15.44 12.55 10.55 ],[9" ".22 9.22 11.22 9.22 11.22 11.22 11.22 9.22 ],[1 1 1 ]);\npatch([12.55 15.44 13.44 10.55 12.55 ],[7.22 7.22 9.22" " 9.22 7.22 ],[0.931 0.946 0.973 ]);\npatch([10.55 13.44 15.44 12.55 10.55 ],[5.22 5.22 7.22 7.22 5.22 ],[1 1 1 " "]);\npatch([12.55 19.44 17.44 15.44 13.44 10.55 12.55 ],[3.22 3.22 5.22 3.22 5.22 5.22 3.22 ],[0.931 0.946 0.97" "3 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');por" "t_label('output',1,'cast');\nfprintf('','COMMENT: end icon text');" } Block { BlockType ToWorkspace Name "To Workspace" SID "603" Ports [1] Position [1785, 1005, 1845, 1035] ZOrder -7 VariableName "eq_out" MaxDataPoints "inf" SampleTime "-1" SaveFormat "Array" } Block { BlockType ToWorkspace Name "To Workspace1" SID "604" Ports [1] Position [1785, 925, 1845, 955] ZOrder -7 VariableName "eq_out_valid" MaxDataPoints "inf" SampleTime "-1" SaveFormat "Array" } Block { BlockType Reference Name "dbg_EQ_I" SID "606" Ports [1, 1] Position [1570, 430, 1630, 450] NamePlacement "alternate" LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of t" "ype Simulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become t" "op level output ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port on timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "60,20,1,1,white,yellow,1,cc31b7ac,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 0 ],[0 0 20 20 0 ],[0.95 0" ".93 0.65 ]);\nplot([0 60 60 0 0 ],[0 0 20 20 0 ]);\npatch([25.55 28.44 30.44 32.44 34.44 30.44 27.55 25.55 ],[1" "2.22 12.22 14.22 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([27.55 30.44 28.44 25.55 27.55 ],[10.22 10.2" "2 12.22 12.22 10.22 ],[0.985 0.979 0.895 ]);\npatch([25.55 28.44 30.44 27.55 25.55 ],[8.22 8.22 10.22 10.22 8.2" "2 ],[1 1 1 ]);\npatch([27.55 34.44 32.44 30.44 28.44 25.55 27.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.985" " 0.979 0.895 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('bl" "ack');port_label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt}\\bf Out ','texmode','o" "n');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "dbg_EQ_Q" SID "607" Ports [1, 1] Position [1570, 465, 1630, 485] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of t" "ype Simulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become t" "op level output ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port on timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "60,20,1,1,white,yellow,1,cc31b7ac,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 0 ],[0 0 20 20 0 ],[0.95 0" ".93 0.65 ]);\nplot([0 60 60 0 0 ],[0 0 20 20 0 ]);\npatch([25.55 28.44 30.44 32.44 34.44 30.44 27.55 25.55 ],[1" "2.22 12.22 14.22 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([27.55 30.44 28.44 25.55 27.55 ],[10.22 10.2" "2 12.22 12.22 10.22 ],[0.985 0.979 0.895 ]);\npatch([25.55 28.44 30.44 27.55 25.55 ],[8.22 8.22 10.22 10.22 8.2" "2 ],[1 1 1 ]);\npatch([27.55 34.44 32.44 30.44 28.44 25.55 27.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.985" " 0.979 0.895 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('bl" "ack');port_label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt}\\bf Out ','texmode','o" "n');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "dbg_EQ_Q1" SID "608" Ports [1, 1] Position [1670, 743, 1700, 757] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of t" "ype Simulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become t" "op level output ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "30,14,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 14 14 0 ],[0.88 0" ".88 0.88 ]);\nplot([0 30 30 0 0 ],[0 0 14 14 0 ]);\npatch([10.55 13.44 15.44 17.44 19.44 15.44 12.55 10.55 ],[9" ".22 9.22 11.22 9.22 11.22 11.22 11.22 9.22 ],[1 1 1 ]);\npatch([12.55 15.44 13.44 10.55 12.55 ],[7.22 7.22 9.22" " 9.22 7.22 ],[0.964 0.964 0.964 ]);\npatch([10.55 13.44 15.44 12.55 10.55 ],[5.22 5.22 7.22 7.22 5.22 ],[1 1 1 " "]);\npatch([12.55 19.44 17.44 15.44 13.44 10.55 12.55 ],[3.22 3.22 5.22 3.22 5.22 5.22 3.22 ],[0.964 0.964 0.96" "4 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf('" "','COMMENT: end icon text');" } Block { BlockType Reference Name "dbg_EQ_Q2" SID "609" Ports [1, 1] Position [1670, 768, 1700, 782] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of t" "ype Simulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become t" "op level output ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "30,14,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 14 14 0 ],[0.88 0" ".88 0.88 ]);\nplot([0 30 30 0 0 ],[0 0 14 14 0 ]);\npatch([10.55 13.44 15.44 17.44 19.44 15.44 12.55 10.55 ],[9" ".22 9.22 11.22 9.22 11.22 11.22 11.22 9.22 ],[1 1 1 ]);\npatch([12.55 15.44 13.44 10.55 12.55 ],[7.22 7.22 9.22" " 9.22 7.22 ],[0.964 0.964 0.964 ]);\npatch([10.55 13.44 15.44 12.55 10.55 ],[5.22 5.22 7.22 7.22 5.22 ],[1 1 1 " "]);\npatch([12.55 19.44 17.44 15.44 13.44 10.55 12.55 ],[3.22 3.22 5.22 3.22 5.22 5.22 3.22 ],[0.964 0.964 0.96" "4 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf('" "','COMMENT: end icon text');" } Block { BlockType Reference Name "dbg_EQ_Q3" SID "610" Ports [1, 1] Position [1670, 718, 1700, 732] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of t" "ype Simulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become t" "op level output ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "30,14,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 14 14 0 ],[0.88 0" ".88 0.88 ]);\nplot([0 30 30 0 0 ],[0 0 14 14 0 ]);\npatch([10.55 13.44 15.44 17.44 19.44 15.44 12.55 10.55 ],[9" ".22 9.22 11.22 9.22 11.22 11.22 11.22 9.22 ],[1 1 1 ]);\npatch([12.55 15.44 13.44 10.55 12.55 ],[7.22 7.22 9.22" " 9.22 7.22 ],[0.964 0.964 0.964 ]);\npatch([10.55 13.44 15.44 12.55 10.55 ],[5.22 5.22 7.22 7.22 5.22 ],[1 1 1 " "]);\npatch([12.55 19.44 17.44 15.44 13.44 10.55 12.55 ],[3.22 3.22 5.22 3.22 5.22 5.22 3.22 ],[0.964 0.964 0.96" "4 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf('" "','COMMENT: end icon text');" } Block { BlockType Reference Name "dbg_EQ_Q4" SID "611" Ports [1, 1] Position [1625, 643, 1655, 657] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of t" "ype Simulink integer, single, double, or fixed-point.

Hardware notes: In hardware these blocks become t" "op level output ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" UseAsDAC off DACChannel "'1'" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "30,14,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 14 14 0 ],[0.88 0" ".88 0.88 ]);\nplot([0 30 30 0 0 ],[0 0 14 14 0 ]);\npatch([10.55 13.44 15.44 17.44 19.44 15.44 12.55 10.55 ],[9" ".22 9.22 11.22 9.22 11.22 11.22 11.22 9.22 ],[1 1 1 ]);\npatch([12.55 15.44 13.44 10.55 12.55 ],[7.22 7.22 9.22" " 9.22 7.22 ],[0.964 0.964 0.964 ]);\npatch([10.55 13.44 15.44 12.55 10.55 ],[5.22 5.22 7.22 7.22 5.22 ],[1 1 1 " "]);\npatch([12.55 19.44 17.44 15.44 13.44 10.55 12.55 ],[3.22 3.22 5.22 3.22 5.22 5.22 3.22 ],[0.964 0.964 0.96" "4 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf('" "','COMMENT: end icon text');" } Line { SrcBlock "Inverter1" SrcPort 1 Points [15, 0] Branch { DstBlock "Register3" DstPort 2 } Branch { Points [0, 50] DstBlock "Register6" DstPort 2 } } Line { SrcBlock "Logical" SrcPort 1 Points [35, 0] Branch { DstBlock "Inverter1" DstPort 1 } Branch { Points [0, 95] Branch { DstBlock "Delay" DstPort 1 } Branch { Points [0, 260] DstBlock "Gateway Out8" DstPort 1 } } Branch { Points [0, -85] DstBlock "4x Buffer" DstPort 3 } } Line { SrcBlock "Register2" SrcPort 1 Points [500, 0] Branch { DstBlock "To FP1" DstPort 1 } Branch { Points [0, 155] Branch { DstBlock "Register6" DstPort 1 } Branch { Points [0, 405] DstBlock "Gateway Out13" DstPort 1 } } } Line { SrcBlock "Register1" SrcPort 1 Points [505, 0] Branch { DstBlock "To FP4" DstPort 1 } Branch { Points [0, 140] Branch { DstBlock "Register3" DstPort 1 } Branch { Points [0, 440] DstBlock "Gateway Out12" DstPort 1 } } } Line { SrcBlock "x_ind" SrcPort 1 DstBlock "Register" DstPort 1 } Line { SrcBlock "Constant" SrcPort 1 DstBlock "Relational" DstPort 2 } Line { SrcBlock "Relational" SrcPort 1 Points [0, -10] DstBlock "Logical" DstPort 2 } Line { SrcBlock "I" SrcPort 1 DstBlock "Register1" DstPort 1 } Line { SrcBlock "Q" SrcPort 1 DstBlock "Register2" DstPort 1 } Line { SrcBlock "Constant1" SrcPort 1 DstBlock "Relational1" DstPort 2 } Line { SrcBlock "Constant2" SrcPort 1 DstBlock "Relational2" DstPort 2 } Line { SrcBlock "Relational1" SrcPort 1 DstBlock "Logical1" DstPort 1 } Line { SrcBlock "Relational2" SrcPort 1 DstBlock "Logical1" DstPort 2 } Line { SrcBlock "Register3" SrcPort 1 Points [40, 0] Branch { DstBlock "Goto" DstPort 1 } Branch { Points [0, 145] DstBlock "dbg_EQ_Q3" DstPort 1 } } Line { SrcBlock "Register6" SrcPort 1 Points [30, 0] Branch { DstBlock "Goto1" DstPort 1 } Branch { Points [0, 120] DstBlock "dbg_EQ_Q1" DstPort 1 } } Line { SrcBlock "Delay" SrcPort 1 Points [30, 0] Branch { DstBlock "Goto2" DstPort 1 } Branch { Points [0, 95] DstBlock "dbg_EQ_Q2" DstPort 1 } } Line { SrcBlock "valid" SrcPort 1 DstBlock "Delay1" DstPort 1 } Line { SrcBlock "Delay1" SrcPort 1 Points [255, 0; 0, 25] DstBlock "Logical" DstPort 1 } Line { SrcBlock "Register7" SrcPort 1 DstBlock "dbg_EQ_I" DstPort 1 } Line { SrcBlock "Register8" SrcPort 1 DstBlock "dbg_EQ_Q" DstPort 1 } Line { SrcBlock "dbg_EQ_I" SrcPort 1 Points [50, 0; 0, 240; 40, 0] Branch { Points [0, 175; 25, 0] } Branch { DstBlock "Debug EQ IQ" DstPort 3 } } Line { SrcBlock "dbg_EQ_Q" SrcPort 1 Points [25, 0; 0, 230; 55, 0] Branch { Points [0, 165; 35, 0] } Branch { DstBlock "Debug EQ IQ" DstPort 4 } } Line { SrcBlock "dbg_EQ_Q3" SrcPort 1 DstBlock "Debug EQ IQ" DstPort 5 } Line { SrcBlock "dbg_EQ_Q1" SrcPort 1 DstBlock "Debug EQ IQ" DstPort 6 } Line { SrcBlock "dbg_EQ_Q2" SrcPort 1 DstBlock "Debug EQ IQ" DstPort 7 } Line { SrcBlock "Gateway Out12" SrcPort 1 DstBlock "Real-Imag to\nComplex" DstPort 1 } Line { SrcBlock "Gateway Out13" SrcPort 1 DstBlock "Real-Imag to\nComplex" DstPort 2 } Line { SrcBlock "Real-Imag to\nComplex" SrcPort 1 DstBlock "To Workspace" DstPort 1 } Line { SrcBlock "Gateway Out8" SrcPort 1 DstBlock "To Workspace1" DstPort 1 } Line { SrcBlock "To FP4" SrcPort 1 DstBlock "4x Buffer" DstPort 1 } Line { SrcBlock "To FP1" SrcPort 1 DstBlock "4x Buffer" DstPort 2 } Line { SrcBlock "Register4" SrcPort 1 DstBlock "Register7" DstPort 1 } Line { SrcBlock "4x Buffer" SrcPort 1 DstBlock "Register4" DstPort 1 } Line { SrcBlock "4x Buffer" SrcPort 3 Points [55, 0] Branch { Points [0, -20] Branch { Points [0, -35] DstBlock "Register4" DstPort 2 } Branch { DstBlock "Register5" DstPort 2 } } Branch { Points [220, 0; 0, 150] DstBlock "dbg_EQ_Q4" DstPort 1 } } Line { SrcBlock "4x Buffer" SrcPort 2 DstBlock "Register5" DstPort 1 } Line { SrcBlock "Register5" SrcPort 1 DstBlock "Register8" DstPort 1 } Line { SrcBlock "dbg_EQ_Q4" SrcPort 1 DstBlock "Debug EQ IQ" DstPort 2 } Line { SrcBlock "Constant3" SrcPort 1 DstBlock "Relational3" DstPort 2 } Line { SrcBlock "Constant4" SrcPort 1 DstBlock "Relational4" DstPort 2 } Line { SrcBlock "Relational3" SrcPort 1 DstBlock "Logical2" DstPort 1 } Line { SrcBlock "Relational4" SrcPort 1 DstBlock "Logical2" DstPort 2 } Line { SrcBlock "Register" SrcPort 1 Points [35, 0] Branch { DstBlock "Relational" DstPort 1 } Branch { Points [0, 85] Branch { DstBlock "Relational1" DstPort 1 } Branch { Points [0, 65] Branch { DstBlock "Relational2" DstPort 1 } Branch { Points [0, 75] Branch { DstBlock "Relational3" DstPort 1 } Branch { Points [0, 65] DstBlock "Relational4" DstPort 1 } } } } } Line { SrcBlock "Mux" SrcPort 1 Points [5, 0; 0, -140] DstBlock "Logical" DstPort 3 } Line { SrcBlock "From" SrcPort 1 Points [5, 0; 0, 75] DstBlock "Mux" DstPort 1 } Line { SrcBlock "Logical2" SrcPort 1 Points [65, 0; 0, -65] DstBlock "Mux" DstPort 3 } Line { SrcBlock "Logical1" SrcPort 1 Points [65, 0; 0, 30] DstBlock "Mux" DstPort 2 } Annotation { Name "Only capture data and pilot subcarriers\nfor debug outputs and chipscope" Position [1035, 370] } } } Block { BlockType SubSystem Name "Equalizer,\nPilot Processing\n& PHY Mode Det" SID "612" Ports [7, 7] Position [465, 239, 560, 441] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "Equalizer,\nPilot Processing\n& PHY Mode Det" Location [61, 101, 2263, 1443] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "88" Block { BlockType Inport Name "x_I" SID "613" Position [230, 338, 260, 352] NamePlacement "alternate" IconDisplay "Port number" } Block { BlockType Inport Name "x_Q" SID "614" Position [230, 368, 260, 382] Port "2" IconDisplay "Port number" } Block { BlockType Inport Name "H_I" SID "615" Position [370, 398, 400, 412] NamePlacement "alternate" Port "3" IconDisplay "Port number" } Block { BlockType Inport Name "H_Q" SID "616" Position [370, 428, 400, 442] Port "4" IconDisplay "Port number" } Block { BlockType Inport Name "x_valid" SID "617" Position [230, 493, 260, 507] NamePlacement "alternate" Port "5" IconDisplay "Port number" } Block { BlockType Inport Name "x_ind" SID "618" Position [230, 513, 260, 527] Port "6" IconDisplay "Port number" } Block { BlockType Inport Name "Sym ind" SID "619" Position [275, 533, 305, 547] Port "7" IconDisplay "Port number" } Block { BlockType Reference Name "Constant" SID "9510" Ports [0, 1] Position [590, 832, 645, 858] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "0.034" gui_display_data_type "Fixed-point" arith_type "Signed (2's comp)" n_bits "16" bin_pt "13" preci_type "Single" exp_width "8" frac_width "24" explicit_period on period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" sg_icon_stat "55,26,0,1,white,blue,0,3f77ca8a,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 55 55 0 0 ],[0 0 26 26 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 55 55 0 0 ],[0 0 26 26 0 ]);\npatch([20.325 24.66 27.66 30.66 33.66 27.66 23.325 20.325 ]" ",[16.33 16.33 19.33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([23.325 27.66 24.66 20.325 23.325 ],[13.3" "3 13.33 16.33 16.33 13.33 ],[0.931 0.946 0.973 ]);\npatch([20.325 24.66 27.66 23.325 20.325 ],[10.33 10.33 13.3" "3 13.33 10.33 ],[1 1 1 ]);\npatch([23.325 33.66 30.66 27.66 24.66 20.325 23.325 ],[7.33 7.33 10.33 7.33 10.33 1" "0.33 7.33 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon " "text');\ncolor('black');port_label('output',1,'0.0340576171875');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Constant1" SID "9603" Ports [0, 1] Position [590, 877, 645, 903] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "0" gui_display_data_type "Fixed-point" arith_type "Signed (2's comp)" n_bits "16" bin_pt "13" preci_type "Single" exp_width "8" frac_width "24" explicit_period on period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" sg_icon_stat "55,26,0,1,white,blue,0,bf4ddd8b,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 55 55 0 0 ],[0 0 26 26 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 55 55 0 0 ],[0 0 26 26 0 ]);\npatch([20.325 24.66 27.66 30.66 33.66 27.66 23.325 20.325 ]" ",[16.33 16.33 19.33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([23.325 27.66 24.66 20.325 23.325 ],[13.3" "3 13.33 16.33 16.33 13.33 ],[0.931 0.946 0.973 ]);\npatch([20.325 24.66 27.66 23.325 20.325 ],[10.33 10.33 13.3" "3 13.33 10.33 ],[1 1 1 ]);\npatch([23.325 33.66 30.66 27.66 24.66 20.325 23.325 ],[7.33 7.33 10.33 7.33 10.33 1" "0.33 7.33 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon " "text');\ncolor('black');port_label('output',1,'0');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Convert" SID "620" Ports [1, 1] Position [880, 358, 915, 382] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do" " not." gui_display_data_type "Fixed-point" arith_type "Signed (2's comp)" n_bits "16" bin_pt "14" float_type "Single" exp_bits "8" fraction_bits "24" quantization "Round (unbiased: +/- Inf)" overflow "Saturate" en off latency "1" dbl_ovrd off pipeline on xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "convert" sg_icon_stat "35,24,1,1,white,blue,0,0c6bad53,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 24 24 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 24 24 0 ]);\npatch([10.325 14.66 17.66 20.66 23.66 17.66 13.325 10.325 ]" ",[15.33 15.33 18.33 15.33 18.33 18.33 18.33 15.33 ],[1 1 1 ]);\npatch([13.325 17.66 14.66 10.325 13.325 ],[12.3" "3 12.33 15.33 15.33 12.33 ],[0.931 0.946 0.973 ]);\npatch([10.325 14.66 17.66 13.325 10.325 ],[9.33 9.33 12.33 " "12.33 9.33 ],[1 1 1 ]);\npatch([13.325 23.66 20.66 17.66 14.66 10.325 13.325 ],[6.33 6.33 9.33 6.33 9.33 9.33 6" ".33 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text')" ";\n\ncolor('black');port_label('output',1,'cast');\ncolor('black');disp('z^{-1}\\newline ','texmode','on');\nco" "lor('black');disp(' \\n ');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Convert1" SID "621" Ports [1, 1] Position [880, 423, 915, 447] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do" " not." gui_display_data_type "Fixed-point" arith_type "Signed (2's comp)" n_bits "16" bin_pt "14" float_type "Single" exp_bits "8" fraction_bits "24" quantization "Round (unbiased: +/- Inf)" overflow "Saturate" en off latency "1" dbl_ovrd off pipeline on xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "convert" sg_icon_stat "35,24,1,1,white,blue,0,0c6bad53,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 24 24 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 24 24 0 ]);\npatch([10.325 14.66 17.66 20.66 23.66 17.66 13.325 10.325 ]" ",[15.33 15.33 18.33 15.33 18.33 18.33 18.33 15.33 ],[1 1 1 ]);\npatch([13.325 17.66 14.66 10.325 13.325 ],[12.3" "3 12.33 15.33 15.33 12.33 ],[0.931 0.946 0.973 ]);\npatch([10.325 14.66 17.66 13.325 10.325 ],[9.33 9.33 12.33 " "12.33 9.33 ],[1 1 1 ]);\npatch([13.325 23.66 20.66 17.66 14.66 10.325 13.325 ],[6.33 6.33 9.33 6.33 9.33 9.33 6" ".33 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text')" ";\n\ncolor('black');port_label('output',1,'cast');\ncolor('black');disp('z^{-1}\\newline ','texmode','on');\nco" "lor('black');disp(' \\n ');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Convert2" SID "10108" Ports [1, 1] Position [880, 308, 915, 332] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do" " not." gui_display_data_type "Fixed-point" arith_type "Signed (2's comp)" n_bits "20" bin_pt "14" float_type "Single" exp_bits "8" fraction_bits "24" quantization "Round (unbiased: +/- Inf)" overflow "Saturate" en off latency "1" dbl_ovrd off pipeline off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "convert" sg_icon_stat "35,24,1,1,white,blue,0,0c6bad53,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 24 24 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 24 24 0 ]);\npatch([10.325 14.66 17.66 20.66 23.66 17.66 13.325 10.325 ]" ",[15.33 15.33 18.33 15.33 18.33 18.33 18.33 15.33 ],[1 1 1 ]);\npatch([13.325 17.66 14.66 10.325 13.325 ],[12.3" "3 12.33 15.33 15.33 12.33 ],[0.931 0.946 0.973 ]);\npatch([10.325 14.66 17.66 13.325 10.325 ],[9.33 9.33 12.33 " "12.33 9.33 ],[1 1 1 ]);\npatch([13.325 23.66 20.66 17.66 14.66 10.325 13.325 ],[6.33 6.33 9.33 6.33 9.33 9.33 6" ".33 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text')" ";\n\ncolor('black');port_label('output',1,'cast');\ncolor('black');disp('z^{-1}\\newline ','texmode','on');\nco" "lor('black');disp(' \\n ');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Convert4" SID "10110" Ports [1, 1] Position [880, 273, 915, 297] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do" " not." gui_display_data_type "Fixed-point" arith_type "Signed (2's comp)" n_bits "20" bin_pt "14" float_type "Single" exp_bits "8" fraction_bits "24" quantization "Round (unbiased: +/- Inf)" overflow "Saturate" en off latency "1" dbl_ovrd off pipeline off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "convert" sg_icon_stat "35,24,1,1,white,blue,0,0c6bad53,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 24 24 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 24 24 0 ]);\npatch([10.325 14.66 17.66 20.66 23.66 17.66 13.325 10.325 ]" ",[15.33 15.33 18.33 15.33 18.33 18.33 18.33 15.33 ],[1 1 1 ]);\npatch([13.325 17.66 14.66 10.325 13.325 ],[12.3" "3 12.33 15.33 15.33 12.33 ],[0.931 0.946 0.973 ]);\npatch([10.325 14.66 17.66 13.325 10.325 ],[9.33 9.33 12.33 " "12.33 9.33 ],[1 1 1 ]);\npatch([13.325 23.66 20.66 17.66 14.66 10.325 13.325 ],[6.33 6.33 9.33 6.33 9.33 9.33 6" ".33 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text')" ";\n\ncolor('black');port_label('output',1,'cast');\ncolor('black');disp('z^{-1}\\newline ','texmode','on');\nco" "lor('black');disp(' \\n ');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Delay1" SID "622" Ports [1, 1] Position [1030, 668, 1065, 692] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flo" "p." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en off latency "62" dbl_ovrd off reg_retiming off xl_use_area