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      SourceOfInitialOutputValue "Dialog"
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      TickLabels	      "OneTimeTick"
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      Grid		      "on"
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      SaveName		      "ScopeData"
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      MaxDataPoints	      "5000"
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      PermitHierarchicalResolution "All"
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      RTWMemSecFuncExecute    "Inherit from model"
      RTWMemSecDataConstants  "Inherit from model"
      RTWMemSecDataInternal   "Inherit from model"
      RTWMemSecDataParameters "Inherit from model"
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      SFBlockType	      "NONE"
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    Block {
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      Inputs		      "++"
      CollapseMode	      "All dimensions"
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      InputSameDT	      on
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  System {
    Name		    "wlan_mac_time_hw"
    Location		    [272, 219, 2188, 1344]
    Open		    on
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      SID		      "1"
      Tag		      "genX"
      Ports		      []
      Position		      [105, 393, 149, 440]
      ShowName		      off
      AttributesFormatString  "System\\nGenerator"
      LibraryVersion	      "1.2"
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      SourceBlock	      "xbsIndex_r4/ System Generator"
      SourceType	      "Xilinx System Generator Block"
      infoedit		      " System Generator"
      xilinxfamily	      "virtex6"
      part		      "xc6vlx240t"
      speed		      "-2"
      package		      "ff1156"
      synthesis_tool	      "XST"
      clock_wrapper	      "Clock Enables"
      directory		      "./wlan_mac_time_v1"
      proj_type		      "Project Navigator"
      Synth_file	      "XST Defaults"
      Impl_file		      "ISE Defaults"
      testbench		      off
      simulink_period	      "1"
      sysclk_period	      "10"
      dcm_input_clock_period  "10"
      incr_netlist	      off
      trim_vbits	      "Everywhere in SubSystem"
      dbl_ovrd		      "According to Block Masks"
      core_generation	      "According to Block Masks"
      run_coregen	      off
      deprecated_control      off
      eval_field	      "0"
      has_advanced_control    "0"
      sggui_pos		      "326,241,464,470"
      block_type	      "sysgen"
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      sg_mask_display	      "fprintf('','COMMENT: begin icon graphics');\npatch([0 44 44 0 0 ],[0 0 47 47 0 ],[1 1 1 ]"
      ");\npatch([1.975 14.98 23.98 32.98 41.98 23.98 10.975 1.975 ],[32.99 32.99 41.99 32.99 41.99 41.99 41.99 32.99 ]"
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      " 0.203922 0.141176 ]);\npatch([10.975 41.98 32.98 23.98 14.98 1.975 10.975 ],[5.99 5.99 14.99 5.99 14.99 14.99 5"
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      "on text');\nfprintf('','COMMENT: end icon text');"
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      SourceBlock	      "xbsIndex_r4/Slice"
      SourceType	      "Xilinx Bit Slice Extractor Block"
      infoedit		      "Extracts a given range of bits from each input sample and presents it at the output.  The outpu"
      "t type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.<br><"
      "br>Hardware notes: In hardware this block costs nothing."
      nbits		      "32"
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      bit1		      "0"
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      base0		      "LSB of Input"
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      sg_icon_stat	      "40,14,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]"
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      "fprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label("
      "'output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');"
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      SID		      "131"
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      Position		      [805, 513, 845, 527]
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      SourceBlock	      "xbsIndex_r4/Slice"
      SourceType	      "Xilinx Bit Slice Extractor Block"
      infoedit		      "Extracts a given range of bits from each input sample and presents it at the output.  The outpu"
      "t type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.<br><"
      "br>Hardware notes: In hardware this block costs nothing."
      nbits		      "32"
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      mode		      "Lower Bit Location + Width"
      bit1		      "0"
      base1		      "MSB of Input"
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      block_type	      "slice"
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      sg_icon_stat	      "40,14,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]"
      sg_mask_display	      "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 14 14 0 ],[0.77 0."
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      "fprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label("
      "'output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');"
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    Block {
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      SID		      "4"
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      Position		      [805, 453, 845, 467]
      LibraryVersion	      "1.2"
      SourceBlock	      "xbsIndex_r4/Slice"
      SourceType	      "Xilinx Bit Slice Extractor Block"
      infoedit		      "Extracts a given range of bits from each input sample and presents it at the output.  The outpu"
      "t type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.<br><"
      "br>Hardware notes: In hardware this block costs nothing."
      nbits		      "32"
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      bit1		      "0"
      base1		      "MSB of Input"
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      sg_icon_stat	      "40,14,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]"
      sg_mask_display	      "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 14 14 0 ],[0.77 0."
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      "fprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label("
      "'output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');"
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    Block {
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      SID		      "132"
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      Position		      [805, 553, 845, 567]
      LibraryVersion	      "1.2"
      SourceBlock	      "xbsIndex_r4/Slice"
      SourceType	      "Xilinx Bit Slice Extractor Block"
      infoedit		      "Extracts a given range of bits from each input sample and presents it at the output.  The outpu"
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      sg_icon_stat	      "40,14,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]"
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      "fprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label("
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	  Name			  "1.00.a:\nNew wlan_mac_time_hw core, with separate MAC and System usec counters\n\n1.00.b:\nFixed default "
	  "value of control register\n\n1.00.c:\nAdded TIME_USEC_FRAC output, copy of count-to-160 counter that defines\n  mic"
	  "rosecond boundary\n\n1.00.d:\nAligned latencies for integer and fractional parts of time outputs"
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      LibraryVersion	      "1.2"
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      DestroyFcn	      "xlDestroyGui(gcbh);"
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      MaskInitialization      "try\n  tmp_gcb = gcb;\n  tmp_gcbh = gcbh;\n  if (strcmp('SysGenIndex',get_param(bdroot("
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      MaskSelfModifiable      on
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      "|0|-1,-1,-1,-1|edkprocessor|2.7|46,46,-1,-1,white,blue,0,07734,right,,[ ],[ ]|fprintf('','COMMENT: begin icon gr"
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      "patch([15.65 24.32 18.32 9.65 15.65 ],[23.66 23.66 29.66 29.66 23.66 ],[0.931 0.946 0.973 ]);\npatch([9.65 18.32"
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      " ],[11.66 11.66 17.66 11.66 17.66 17.66 11.66 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics')"
      ";\nfprintf('','COMMENT: begin icon text');\nfprintf('','COMMENT: end icon text');|{'table'=>{'AvailableMemories'"
      "=>'popup(<empty>)'}}|"
      System {
	Name			"EDK Processor"
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	Block {
	  BlockType		  Reference
	  Name			  "AXI_ARESETN"
	  SID			  "215:211"
	  Ports			  [1, 1]
	  Position		  [145, 50, 210, 70]
	  LibraryVersion	  "1.2"
	  SourceBlock		  "xbsIndex_r4/Gateway In"
	  SourceType		  "Xilinx Gateway In Block"
	  infoedit		  "Gateway in block.  Converts inputs of type Simulink integer, single, double and fixed-point to  Xilinx"
	  " fixed-point or floating-point data type.<br><br>Hardware notes:  In hardware these blocks become top level input p"
	  "orts."
	  gui_display_data_type	  "Fixed-point"
	  arith_type		  "Boolean"
	  n_bits		  "16"
	  bin_pt		  "14"
	  preci_type		  "Single"
	  exp_width		  "8"
	  frac_width		  "24"
	  quantization		  "Round  (unbiased: +/- Inf)"
	  overflow		  "Saturate"
	  period		  "xlGetNormalizedPeriod()"
	  dbl_ovrd		  off
	  timing_constraint	  "None"
	  locs_specified	  off
	  LOCs			  "{}"
	  UseAsADC		  off
	  ADCChannel		  "'1'"
	  xl_use_area		  off
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	  block_type		  "gatewayin"
	  sg_icon_stat		  "65,20,1,1,white,yellow,1,00d3666e,right,,[ ],[ ]"
	  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 65 65 0 0 ],[0 0 20 20 0 ],[0.95 0.93 0.65"
	  " ]);\nplot([0 65 65 0 0 ],[0 0 20 20 0 ]);\npatch([27.55 30.44 32.44 34.44 36.44 32.44 29.55 27.55 ],[12.22 12.22 1"
	  "4.22 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([29.55 32.44 30.44 27.55 29.55 ],[10.22 10.22 12.22 12.22 10"
	  ".22 ],[0.985 0.979 0.895 ]);\npatch([27.55 30.44 32.44 29.55 27.55 ],[8.22 8.22 10.22 10.22 8.22 ],[1 1 1 ]);\npatc"
	  "h([29.55 36.44 34.44 32.44 30.44 27.55 29.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.985 0.979 0.895 ]);\nfprint"
	  "f('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'"
	  "\\fontsize{11pt}\\bf In ','texmode','on');\ncolor('black');port_label('output',1,' ');\nfprintf('','COMMENT: end ic"
	  "on text');"
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	Block {
	  BlockType		  Constant
	  Name			  "Constant"
	  SID			  "215:210"
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	Block {
	  BlockType		  Constant
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	  SID			  "215:212"
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	  ShowName		  off
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	Block {
	  BlockType		  Constant
	  Name			  "Constant10"
	  SID			  "215:230"
	  Position		  [20, 730, 40, 750]
	  ShowName		  off
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	  MaskIconRotate	  "none"
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	Block {
	  BlockType		  Constant
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	  SID			  "215:232"
	  Position		  [20, 795, 40, 815]
	  ShowName		  off
	  MaskIconFrame		  on
	  MaskIconOpaque	  on
	  MaskIconRotate	  "none"
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	  MaskIconUnits		  "autoscale"
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	Block {
	  BlockType		  Constant
	  Name			  "Constant12"
	  SID			  "215:234"
	  Position		  [20, 865, 40, 885]
	  ShowName		  off
	  MaskIconFrame		  on
	  MaskIconOpaque	  on
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	  MaskIconUnits		  "autoscale"
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	Block {
	  BlockType		  Constant
	  Name			  "Constant13"
	  SID			  "215:236"
	  Position		  [20, 935, 40, 955]
	  ShowName		  off
	  MaskIconFrame		  on
	  MaskIconOpaque	  on
	  MaskIconRotate	  "none"
	  MaskPortRotate	  "default"
	  MaskIconUnits		  "autoscale"
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	Block {
	  BlockType		  Constant
	  Name			  "Constant14"
	  SID			  "215:238"
	  Position		  [20, 1000, 40, 1020]
	  ShowName		  off
	  MaskIconFrame		  on
	  MaskIconOpaque	  on
	  MaskIconRotate	  "none"
	  MaskPortRotate	  "default"
	  MaskIconUnits		  "autoscale"
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	Block {
	  BlockType		  Constant
	  Name			  "Constant15"
	  SID			  "215:240"
	  Position		  [20, 1070, 40, 1090]
	  ShowName		  off
	  MaskIconFrame		  on
	  MaskIconOpaque	  on
	  MaskIconRotate	  "none"
	  MaskPortRotate	  "default"
	  MaskIconUnits		  "autoscale"
	}
	Block {
	  BlockType		  Constant
	  Name			  "Constant16"
	  SID			  "215:242"
	  Position		  [20, 1135, 40, 1155]
	  ShowName		  off
	  MaskIconFrame		  on
	  MaskIconOpaque	  on
	  MaskIconRotate	  "none"
	  MaskPortRotate	  "default"
	  MaskIconUnits		  "autoscale"
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	Block {
	  BlockType		  Constant
	  Name			  "Constant17"
	  SID			  "215:244"
	  Position		  [20, 1205, 40, 1225]
	  ShowName		  off
	  MaskIconFrame		  on
	  MaskIconOpaque	  on
	  MaskIconRotate	  "none"
	  MaskPortRotate	  "default"
	  MaskIconUnits		  "autoscale"
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	Block {
	  BlockType		  Constant
	  Name			  "Constant18"
	  SID			  "215:246"
	  Position		  [20, 1275, 40, 1295]
	  ShowName		  off
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	  MaskIconOpaque	  on
	  MaskIconRotate	  "none"
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	Block {
	  BlockType		  Constant
	  Name			  "Constant19"
	  SID			  "215:248"
	  Position		  [20, 1340, 40, 1360]
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	  MaskIconOpaque	  on
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	  MaskIconUnits		  "autoscale"
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	Block {
	  BlockType		  Constant
	  Name			  "Constant2"
	  SID			  "215:214"
	  Position		  [20, 185, 40, 205]
	  ShowName		  off
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	  MaskIconOpaque	  on
	  MaskIconRotate	  "none"
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	Block {
	  BlockType		  Constant
	  Name			  "Constant20"
	  SID			  "215:250"
	  Position		  [20, 1410, 40, 1430]
	  ShowName		  off
	  MaskIconFrame		  on
	  MaskIconOpaque	  on
	  MaskIconRotate	  "none"
	  MaskPortRotate	  "default"
	  MaskIconUnits		  "autoscale"
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	Block {
	  BlockType		  Constant
	  Name			  "Constant21"
	  SID			  "215:252"
	  Position		  [20, 1475, 40, 1495]
	  ShowName		  off
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	  MaskIconOpaque	  on
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	  MaskPortRotate	  "default"
	  MaskIconUnits		  "autoscale"
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	Block {
	  BlockType		  Constant
	  Name			  "Constant22"
	  SID			  "215:254"
	  Position		  [20, 1545, 40, 1565]
	  ShowName		  off
	  MaskIconFrame		  on
	  MaskIconOpaque	  on
	  MaskIconRotate	  "none"
	  MaskPortRotate	  "default"
	  MaskIconUnits		  "autoscale"
	}
	Block {
	  BlockType		  Constant
	  Name			  "Constant23"
	  SID			  "215:256"
	  Position		  [20, 1615, 40, 1635]
	  ShowName		  off
	  MaskIconFrame		  on
	  MaskIconOpaque	  on
	  MaskIconRotate	  "none"
	  MaskPortRotate	  "default"
	  MaskIconUnits		  "autoscale"
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	Block {
	  BlockType		  Constant
	  Name			  "Constant24"
	  SID			  "215:258"
	  Position		  [20, 1680, 40, 1700]
	  ShowName		  off
	  MaskIconFrame		  on
	  MaskIconOpaque	  on
	  MaskIconRotate	  "none"
	  MaskPortRotate	  "default"
	  MaskIconUnits		  "autoscale"
	}
	Block {
	  BlockType		  Constant
	  Name			  "Constant3"
	  SID			  "215:216"
	  Position		  [20, 255, 40, 275]
	  ShowName		  off
	  MaskIconFrame		  on
	  MaskIconOpaque	  on
	  MaskIconRotate	  "none"
	  MaskPortRotate	  "default"
	  MaskIconUnits		  "autoscale"
	}
	Block {
	  BlockType		  Constant
	  Name			  "Constant4"
	  SID			  "215:218"
	  Position		  [20, 320, 40, 340]
	  ShowName		  off
	  MaskIconFrame		  on
	  MaskIconOpaque	  on
	  MaskIconRotate	  "none"
	  MaskPortRotate	  "default"
	  MaskIconUnits		  "autoscale"
	}
	Block {
	  BlockType		  Constant
	  Name			  "Constant5"
	  SID			  "215:220"
	  Position		  [20, 390, 40, 410]
	  ShowName		  off
	  MaskIconFrame		  on
	  MaskIconOpaque	  on
	  MaskIconRotate	  "none"
	  MaskPortRotate	  "default"
	  MaskIconUnits		  "autoscale"
	}
	Block {
	  BlockType		  Constant
	  Name			  "Constant6"
	  SID			  "215:222"
	  Position		  [20, 455, 40, 475]
	  ShowName		  off
	  MaskIconFrame		  on
	  MaskIconOpaque	  on
	  MaskIconRotate	  "none"
	  MaskPortRotate	  "default"
	  MaskIconUnits		  "autoscale"
	}
	Block {
	  BlockType		  Constant
	  Name			  "Constant7"
	  SID			  "215:224"
	  Position		  [20, 525, 40, 545]
	  ShowName		  off
	  MaskIconFrame		  on
	  MaskIconOpaque	  on
	  MaskIconRotate	  "none"
	  MaskPortRotate	  "default"
	  MaskIconUnits		  "autoscale"
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	Block {
	  BlockType		  Constant
	  Name			  "Constant8"
	  SID			  "215:226"
	  Position		  [20, 595, 40, 615]
	  ShowName		  off
	  MaskIconFrame		  on
	  MaskIconOpaque	  on
	  MaskIconRotate	  "none"
	  MaskPortRotate	  "default"
	  MaskIconUnits		  "autoscale"
	}
	Block {
	  BlockType		  Constant
	  Name			  "Constant9"
	  SID			  "215:228"
	  Position		  [20, 660, 40, 680]
	  ShowName		  off
	  MaskIconFrame		  on
	  MaskIconOpaque	  on
	  MaskIconRotate	  "none"
	  MaskPortRotate	  "default"
	  MaskIconUnits		  "autoscale"
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	Block {
	  BlockType		  Reference
	  Name			  "From Register"
	  SID			  "215:203"
	  Ports			  [0, 1]
	  Position		  [145, 1752, 205, 1808]
	  AttributesFormatString  "<< %<shared_memory_name> >>"
	  LibraryVersion	  "1.2"
	  SourceBlock		  "xbsIndex_r4/From Register"
	  SourceType		  "Xilinx Shared Memory Based From Register Block"
	  infoedit		  "Register block that reads data to a shared memory register.  Delay of one sample period."
	  shared_memory_name	  "'SYSTEM_TIME_USEC_MSB'"
	  init			  "0"
	  period		  "xlGetNormalizedPeriod()"
	  ownership		  "Owned and initialized elsewhere"
	  gui_display_data_type	  "Fixed-point"
	  arith_type		  "Unsigned"
	  n_bits		  "32"
	  bin_pt		  "0"
	  preci_type		  "Single"
	  dbl_ovrd		  off
	  xl_use_area		  off
	  xl_area		  "[0,0,0,0,0,0,0]"
	  has_advanced_control	  "0"
	  sggui_pos		  "-1,-1,-1,-1"
	  block_type		  "fromreg"
	  sg_icon_stat		  "60,56,0,1,white,blue,0,b27a07ff,right,,[ ],[ ]"
	  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 0 ],[0 0 56 56 0 ],[0.77 0.82 0.91"
	  " ]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\npatch([12.2 23.76 31.76 39.76 47.76 31.76 20.2 12.2 ],[36.88 36.88 44.8"
	  "8 36.88 44.88 44.88 44.88 36.88 ],[1 1 1 ]);\npatch([20.2 31.76 23.76 12.2 20.2 ],[28.88 28.88 36.88 36.88 28.88 ],"
	  "[0.931 0.946 0.973 ]);\npatch([12.2 23.76 31.76 20.2 12.2 ],[20.88 20.88 28.88 28.88 20.88 ],[1 1 1 ]);\npatch([20."
	  "2 47.76 39.76 31.76 23.76 12.2 20.2 ],[12.88 12.88 20.88 12.88 20.88 20.88 12.88 ],[0.931 0.946 0.973 ]);\nfprintf("
	  "'','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'d"
	  "out');\nfprintf('','COMMENT: end icon text');"
	}
	Block {
	  BlockType		  Reference
	  Name			  "From Register1"
	  SID			  "215:204"
	  Ports			  [0, 1]
	  Position		  [145, 1857, 205, 1913]
	  AttributesFormatString  "<< %<shared_memory_name> >>"
	  LibraryVersion	  "1.2"
	  SourceBlock		  "xbsIndex_r4/From Register"
	  SourceType		  "Xilinx Shared Memory Based From Register Block"
	  infoedit		  "Register block that reads data to a shared memory register.  Delay of one sample period."
	  shared_memory_name	  "'SYSTEM_TIME_USEC_LSB'"
	  init			  "0"
	  period		  "xlGetNormalizedPeriod()"
	  ownership		  "Owned and initialized elsewhere"
	  gui_display_data_type	  "Fixed-point"
	  arith_type		  "Unsigned"
	  n_bits		  "32"
	  bin_pt		  "0"
	  preci_type		  "Single"
	  dbl_ovrd		  off
	  xl_use_area		  off
	  xl_area		  "[0,0,0,0,0,0,0]"
	  has_advanced_control	  "0"
	  sggui_pos		  "-1,-1,-1,-1"
	  block_type		  "fromreg"
	  sg_icon_stat		  "60,56,0,1,white,blue,0,b27a07ff,right,,[ ],[ ]"
	  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 0 ],[0 0 56 56 0 ],[0.77 0.82 0.91"
	  " ]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\npatch([12.2 23.76 31.76 39.76 47.76 31.76 20.2 12.2 ],[36.88 36.88 44.8"
	  "8 36.88 44.88 44.88 44.88 36.88 ],[1 1 1 ]);\npatch([20.2 31.76 23.76 12.2 20.2 ],[28.88 28.88 36.88 36.88 28.88 ],"
	  "[0.931 0.946 0.973 ]);\npatch([12.2 23.76 31.76 20.2 12.2 ],[20.88 20.88 28.88 28.88 20.88 ],[1 1 1 ]);\npatch([20."
	  "2 47.76 39.76 31.76 23.76 12.2 20.2 ],[12.88 12.88 20.88 12.88 20.88 20.88 12.88 ],[0.931 0.946 0.973 ]);\nfprintf("
	  "'','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'d"
	  "out');\nfprintf('','COMMENT: end icon text');"
	}
	Block {
	  BlockType		  Reference
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	  SID			  "215:205"
	  Ports			  [0, 1]
	  Position		  [145, 1962, 205, 2018]
	  AttributesFormatString  "<< %<shared_memory_name> >>"
	  LibraryVersion	  "1.2"
	  SourceBlock		  "xbsIndex_r4/From Register"
	  SourceType		  "Xilinx Shared Memory Based From Register Block"
	  infoedit		  "Register block that reads data to a shared memory register.  Delay of one sample period."
	  shared_memory_name	  "'MAC_TIME_USEC_MSB'"
	  init			  "0"
	  period		  "xlGetNormalizedPeriod()"
	  ownership		  "Owned and initialized elsewhere"
	  gui_display_data_type	  "Fixed-point"
	  arith_type		  "Unsigned"
	  n_bits		  "32"
	  bin_pt		  "0"
	  preci_type		  "Single"
	  dbl_ovrd		  off
	  xl_use_area		  off
	  xl_area		  "[0,0,0,0,0,0,0]"
	  has_advanced_control	  "0"
	  sggui_pos		  "-1,-1,-1,-1"
	  block_type		  "fromreg"
	  sg_icon_stat		  "60,56,0,1,white,blue,0,b27a07ff,right,,[ ],[ ]"
	  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 0 ],[0 0 56 56 0 ],[0.77 0.82 0.91"
	  " ]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\npatch([12.2 23.76 31.76 39.76 47.76 31.76 20.2 12.2 ],[36.88 36.88 44.8"
	  "8 36.88 44.88 44.88 44.88 36.88 ],[1 1 1 ]);\npatch([20.2 31.76 23.76 12.2 20.2 ],[28.88 28.88 36.88 36.88 28.88 ],"
	  "[0.931 0.946 0.973 ]);\npatch([12.2 23.76 31.76 20.2 12.2 ],[20.88 20.88 28.88 28.88 20.88 ],[1 1 1 ]);\npatch([20."
	  "2 47.76 39.76 31.76 23.76 12.2 20.2 ],[12.88 12.88 20.88 12.88 20.88 20.88 12.88 ],[0.931 0.946 0.973 ]);\nfprintf("
	  "'','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'d"
	  "out');\nfprintf('','COMMENT: end icon text');"
	}
	Block {
	  BlockType		  Reference
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	  SID			  "215:206"
	  Ports			  [0, 1]
	  Position		  [145, 2067, 205, 2123]
	  AttributesFormatString  "<< %<shared_memory_name> >>"
	  LibraryVersion	  "1.2"
	  SourceBlock		  "xbsIndex_r4/From Register"
	  SourceType		  "Xilinx Shared Memory Based From Register Block"
	  infoedit		  "Register block that reads data to a shared memory register.  Delay of one sample period."
	  shared_memory_name	  "'MAC_TIME_USEC_LSB'"
	  init			  "0"
	  period		  "xlGetNormalizedPeriod()"
	  ownership		  "Owned and initialized elsewhere"
	  gui_display_data_type	  "Fixed-point"
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	  "'','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'d"
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	  LibraryVersion	  "1.2"
	  SourceBlock		  "xbsIndex_r4/Gateway In"
	  SourceType		  "Xilinx Gateway In Block"
	  infoedit		  "Gateway in block.  Converts inputs of type Simulink integer, single, double and fixed-point to  Xilinx"
	  " fixed-point or floating-point data type.<br><br>Hardware notes:  In hardware these blocks become top level input p"
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	  gui_display_data_type	  "Fixed-point"
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	  quantization		  "Round  (unbiased: +/- Inf)"
	  overflow		  "Saturate"
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	  LibraryVersion	  "1.2"
	  SourceBlock		  "xbsIndex_r4/Gateway In"
	  SourceType		  "Xilinx Gateway In Block"
	  infoedit		  "Gateway in block.  Converts inputs of type Simulink integer, single, double and fixed-point to  Xilinx"
	  " fixed-point or floating-point data type.<br><br>Hardware notes:  In hardware these blocks become top level input p"
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	  gui_display_data_type	  "Fixed-point"
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	  overflow		  "Saturate"
	  period		  "xlGetNormalizedPeriod()"
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	  SID			  "215:217"
	  Ports			  [1, 1]
	  Position		  [145, 255, 210, 275]
	  LibraryVersion	  "1.2"
	  SourceBlock		  "xbsIndex_r4/Gateway In"
	  SourceType		  "Xilinx Gateway In Block"
	  infoedit		  "Gateway in block.  Converts inputs of type Simulink integer, single, double and fixed-point to  Xilinx"
	  " fixed-point or floating-point data type.<br><br>Hardware notes:  In hardware these blocks become top level input p"
	  "orts."
	  gui_display_data_type	  "Fixed-point"
	  arith_type		  "Unsigned"
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	  bin_pt		  "0"
	  preci_type		  "Single"
	  exp_width		  "8"
	  frac_width		  "24"
	  quantization		  "Round  (unbiased: +/- Inf)"
	  overflow		  "Saturate"
	  period		  "xlGetNormalizedPeriod()"
	  dbl_ovrd		  off
	  timing_constraint	  "None"
	  locs_specified	  off
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	  LibraryVersion	  "1.2"
	  SourceBlock		  "xbsIndex_r4/Gateway In"
	  SourceType		  "Xilinx Gateway In Block"
	  infoedit		  "Gateway in block.  Converts inputs of type Simulink integer, single, double and fixed-point to  Xilinx"
	  " fixed-point or floating-point data type.<br><br>Hardware notes:  In hardware these blocks become top level input p"
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	  gui_display_data_type	  "Fixed-point"
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	  frac_width		  "24"
	  quantization		  "Round  (unbiased: +/- Inf)"
	  overflow		  "Saturate"
	  period		  "xlGetNormalizedPeriod()"
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	  SID			  "215:221"
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	  Position		  [145, 390, 210, 410]
	  LibraryVersion	  "1.2"
	  SourceBlock		  "xbsIndex_r4/Gateway In"
	  SourceType		  "Xilinx Gateway In Block"
	  infoedit		  "Gateway in block.  Converts inputs of type Simulink integer, single, double and fixed-point to  Xilinx"
	  " fixed-point or floating-point data type.<br><br>Hardware notes:  In hardware these blocks become top level input p"
	  "orts."
	  gui_display_data_type	  "Fixed-point"
	  arith_type		  "Unsigned"
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	  preci_type		  "Single"
	  exp_width		  "8"
	  frac_width		  "24"
	  quantization		  "Round  (unbiased: +/- Inf)"
	  overflow		  "Saturate"
	  period		  "xlGetNormalizedPeriod()"
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	  LibraryVersion	  "1.2"
	  SourceBlock		  "xbsIndex_r4/Gateway In"
	  SourceType		  "Xilinx Gateway In Block"
	  infoedit		  "Gateway in block.  Converts inputs of type Simulink integer, single, double and fixed-point to  Xilinx"
	  " fixed-point or floating-point data type.<br><br>Hardware notes:  In hardware these blocks become top level input p"
	  "orts."
	  gui_display_data_type	  "Fixed-point"
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	  preci_type		  "Single"
	  exp_width		  "8"
	  frac_width		  "24"
	  quantization		  "Round  (unbiased: +/- Inf)"
	  overflow		  "Saturate"
	  period		  "xlGetNormalizedPeriod()"
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	  timing_constraint	  "None"
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	  SourceBlock		  "xbsIndex_r4/Gateway In"
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	  infoedit		  "Gateway in block.  Converts inputs of type Simulink integer, single, double and fixed-point to  Xilinx"
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	  gui_display_data_type	  "Fixed-point"
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	  period		  "xlGetNormalizedPeriod()"
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	  SourceBlock		  "xbsIndex_r4/Gateway Out"
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	  "link integer, single, double, or fixed-point.<br><br>Hardware notes:  In hardware these blocks become top level out"
	  "put ports or are discarded, depending on how they are configured."
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	  infoedit		  "Gateway in block.  Converts inputs of type Simulink integer, single, double and fixed-point to  Xilinx"
	  " fixed-point or floating-point data type.<br><br>Hardware notes:  In hardware these blocks become top level input p"
	  "orts."
	  gui_display_data_type	  "Fixed-point"
	  arith_type		  "Unsigned"
	  n_bits		  "3"
	  bin_pt		  "0"
	  preci_type		  "Single"
	  exp_width		  "8"
	  frac_width		  "24"
	  quantization		  "Round  (unbiased: +/- Inf)"
	  overflow		  "Saturate"
	  period		  "xlGetNormalizedPeriod()"
	  dbl_ovrd		  off
	  timing_constraint	  "None"
	  locs_specified	  off
	  LOCs			  "{}"
	  UseAsADC		  off
	  ADCChannel		  "'1'"
	  xl_use_area		  off
	  xl_area		  "[0,0,0,0,0,0,0]"
	  inherit_from_input	  off
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	  sggui_pos		  "-1,-1,-1,-1"
	  block_type		  "gatewayin"
	  sg_icon_stat		  "65,20,1,1,white,yellow,1,00d3666e,right,,[ ],[ ]"
	  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 65 65 0 0 ],[0 0 20 20 0 ],[0.95 0.93 0.65"
	  " ]);\nplot([0 65 65 0 0 ],[0 0 20 20 0 ]);\npatch([27.55 30.44 32.44 34.44 36.44 32.44 29.55 27.55 ],[12.22 12.22 1"
	  "4.22 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([29.55 32.44 30.44 27.55 29.55 ],[10.22 10.22 12.22 12.22 10"
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	  "h([29.55 36.44 34.44 32.44 30.44 27.55 29.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.985 0.979 0.895 ]);\nfprint"
	  "f('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'"
	  "\\fontsize{11pt}\\bf In ','texmode','on');\ncolor('black');port_label('output',1,' ');\nfprintf('','COMMENT: end ic"
	  "on text');"
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	  LibraryVersion	  "1.2"
	  SourceBlock		  "xbsIndex_r4/Gateway Out"
	  SourceType		  "Xilinx Gateway Out Block"
	  infoedit		  "Gateway out block.  Converts Xilinx fixed-point or floating-point type inputs into ouputs of type Simu"
	  "link integer, single, double, or fixed-point.<br><br>Hardware notes:  In hardware these blocks become top level out"
	  "put ports or are discarded, depending on how they are configured."
	  inherit_from_input	  off
	  hdl_port		  on
	  timing_constraint	  "None"
	  locs_specified	  off
	  LOCs			  "{}"
	  UseAsDAC		  off
	  DACChannel		  "'1'"
	  xl_use_area		  off
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	  has_advanced_control	  "0"
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	  block_type		  "gatewayout"
	  sg_icon_stat		  "60,20,1,1,white,yellow,1,cc31b7ac,right,,[ ],[ ]"
	  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 0 ],[0 0 20 20 0 ],[0.95 0.93 0.65"
	  " ]);\nplot([0 60 60 0 0 ],[0 0 20 20 0 ]);\npatch([25.55 28.44 30.44 32.44 34.44 30.44 27.55 25.55 ],[12.22 12.22 1"
	  "4.22 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([27.55 30.44 28.44 25.55 27.55 ],[10.22 10.22 12.22 12.22 10"
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	  "f('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'"
	  " ');\ncolor('black');port_label('output',1,'\\fontsize{11pt}\\bf Out ','texmode','on');\nfprintf('','COMMENT: end i"
	  "con text');"
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	  SID			  "215:245"
	  Ports			  [1, 1]
	  Position		  [145, 1205, 210, 1225]
	  LibraryVersion	  "1.2"
	  SourceBlock		  "xbsIndex_r4/Gateway In"
	  SourceType		  "Xilinx Gateway In Block"
	  infoedit		  "Gateway in block.  Converts inputs of type Simulink integer, single, double and fixed-point to  Xilinx"
	  " fixed-point or floating-point data type.<br><br>Hardware notes:  In hardware these blocks become top level input p"
	  "orts."
	  gui_display_data_type	  "Fixed-point"
	  arith_type		  "Unsigned"
	  n_bits		  "3"
	  bin_pt		  "0"
	  preci_type		  "Single"
	  exp_width		  "8"
	  frac_width		  "24"
	  quantization		  "Round  (unbiased: +/- Inf)"
	  overflow		  "Saturate"
	  period		  "xlGetNormalizedPeriod()"
	  dbl_ovrd		  off
	  timing_constraint	  "None"
	  locs_specified	  off
	  LOCs			  "{}"
	  UseAsADC		  off
	  ADCChannel		  "'1'"
	  xl_use_area		  off
	  xl_area		  "[0,0,0,0,0,0,0]"
	  inherit_from_input	  off
	  hdl_port		  "on"
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	  sggui_pos		  "-1,-1,-1,-1"
	  block_type		  "gatewayin"
	  sg_icon_stat		  "65,20,1,1,white,yellow,1,00d3666e,right,,[ ],[ ]"
	  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 65 65 0 0 ],[0 0 20 20 0 ],[0.95 0.93 0.65"
	  " ]);\nplot([0 65 65 0 0 ],[0 0 20 20 0 ]);\npatch([27.55 30.44 32.44 34.44 36.44 32.44 29.55 27.55 ],[12.22 12.22 1"
	  "4.22 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([29.55 32.44 30.44 27.55 29.55 ],[10.22 10.22 12.22 12.22 10"
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	  "f('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'"
	  "\\fontsize{11pt}\\bf In ','texmode','on');\ncolor('black');port_label('output',1,' ');\nfprintf('','COMMENT: end ic"
	  "on text');"
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	Block {
	  BlockType		  Reference
	  Name			  "S_AXI_AWVALID"
	  SID			  "215:247"
	  Ports			  [1, 1]
	  Position		  [145, 1275, 210, 1295]
	  LibraryVersion	  "1.2"
	  SourceBlock		  "xbsIndex_r4/Gateway In"
	  SourceType		  "Xilinx Gateway In Block"
	  infoedit		  "Gateway in block.  Converts inputs of type Simulink integer, single, double and fixed-point to  Xilinx"
	  " fixed-point or floating-point data type.<br><br>Hardware notes:  In hardware these blocks become top level input p"
	  "orts."
	  gui_display_data_type	  "Fixed-point"
	  arith_type		  "Boolean"
	  n_bits		  "16"
	  bin_pt		  "14"
	  preci_type		  "Single"
	  exp_width		  "8"
	  frac_width		  "24"
	  quantization		  "Round  (unbiased: +/- Inf)"
	  overflow		  "Saturate"
	  period		  "xlGetNormalizedPeriod()"
	  dbl_ovrd		  off
	  timing_constraint	  "None"
	  locs_specified	  off
	  LOCs			  "{}"
	  UseAsADC		  off
	  ADCChannel		  "'1'"
	  xl_use_area		  off
	  xl_area		  "[0,0,0,0,0,0,0]"
	  inherit_from_input	  off
	  hdl_port		  "on"
	  has_advanced_control	  "0"
	  sggui_pos		  "-1,-1,-1,-1"
	  block_type		  "gatewayin"
	  sg_icon_stat		  "65,20,1,1,white,yellow,1,00d3666e,right,,[ ],[ ]"
	  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 65 65 0 0 ],[0 0 20 20 0 ],[0.95 0.93 0.65"
	  " ]);\nplot([0 65 65 0 0 ],[0 0 20 20 0 ]);\npatch([27.55 30.44 32.44 34.44 36.44 32.44 29.55 27.55 ],[12.22 12.22 1"
	  "4.22 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([29.55 32.44 30.44 27.55 29.55 ],[10.22 10.22 12.22 12.22 10"
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	  "f('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'"
	  "\\fontsize{11pt}\\bf In ','texmode','on');\ncolor('black');port_label('output',1,' ');\nfprintf('','COMMENT: end ic"
	  "on text');"
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	  LibraryVersion	  "1.2"
	  SourceBlock		  "xbsIndex_r4/Gateway Out"
	  SourceType		  "Xilinx Gateway Out Block"
	  infoedit		  "Gateway out block.  Converts Xilinx fixed-point or floating-point type inputs into ouputs of type Simu"
	  "link integer, single, double, or fixed-point.<br><br>Hardware notes:  In hardware these blocks become top level out"
	  "put ports or are discarded, depending on how they are configured."
	  inherit_from_input	  off
	  hdl_port		  on
	  timing_constraint	  "None"
	  locs_specified	  off
	  LOCs			  "{}"
	  UseAsDAC		  off
	  DACChannel		  "'1'"
	  xl_use_area		  off
	  xl_area		  "[0,0,0,0,0,0,0]"
	  has_advanced_control	  "0"
	  sggui_pos		  "-1,-1,-1,-1"
	  block_type		  "gatewayout"
	  sg_icon_stat		  "60,20,1,1,white,yellow,1,cc31b7ac,right,,[ ],[ ]"
	  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 0 ],[0 0 20 20 0 ],[0.95 0.93 0.65"
	  " ]);\nplot([0 60 60 0 0 ],[0 0 20 20 0 ]);\npatch([25.55 28.44 30.44 32.44 34.44 30.44 27.55 25.55 ],[12.22 12.22 1"
	  "4.22 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([27.55 30.44 28.44 25.55 27.55 ],[10.22 10.22 12.22 12.22 10"
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	  "f('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'"
	  " ');\ncolor('black');port_label('output',1,'\\fontsize{11pt}\\bf Out ','texmode','on');\nfprintf('','COMMENT: end i"
	  "con text');"
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	Block {
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	  Name			  "S_AXI_BREADY"
	  SID			  "215:249"
	  Ports			  [1, 1]
	  Position		  [145, 1340, 210, 1360]
	  LibraryVersion	  "1.2"
	  SourceBlock		  "xbsIndex_r4/Gateway In"
	  SourceType		  "Xilinx Gateway In Block"
	  infoedit		  "Gateway in block.  Converts inputs of type Simulink integer, single, double and fixed-point to  Xilinx"
	  " fixed-point or floating-point data type.<br><br>Hardware notes:  In hardware these blocks become top level input p"
	  "orts."
	  gui_display_data_type	  "Fixed-point"
	  arith_type		  "Boolean"
	  n_bits		  "16"
	  bin_pt		  "14"
	  preci_type		  "Single"
	  exp_width		  "8"
	  frac_width		  "24"
	  quantization		  "Round  (unbiased: +/- Inf)"
	  overflow		  "Saturate"
	  period		  "xlGetNormalizedPeriod()"
	  dbl_ovrd		  off
	  timing_constraint	  "None"
	  locs_specified	  off
	  LOCs			  "{}"
	  UseAsADC		  off
	  ADCChannel		  "'1'"
	  xl_use_area		  off
	  xl_area		  "[0,0,0,0,0,0,0]"
	  inherit_from_input	  off
	  hdl_port		  "on"
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	  sggui_pos		  "-1,-1,-1,-1"
	  block_type		  "gatewayin"
	  sg_icon_stat		  "65,20,1,1,white,yellow,1,00d3666e,right,,[ ],[ ]"
	  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 65 65 0 0 ],[0 0 20 20 0 ],[0.95 0.93 0.65"
	  " ]);\nplot([0 65 65 0 0 ],[0 0 20 20 0 ]);\npatch([27.55 30.44 32.44 34.44 36.44 32.44 29.55 27.55 ],[12.22 12.22 1"
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	  "f('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'"
	  "\\fontsize{11pt}\\bf In ','texmode','on');\ncolor('black');port_label('output',1,' ');\nfprintf('','COMMENT: end ic"
	  "on text');"
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	Block {
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	  Name			  "S_AXI_BRESP"
	  SID			  "215:267"
	  Ports			  [1, 1]
	  Position		  [660, 725, 720, 745]
	  LibraryVersion	  "1.2"
	  SourceBlock		  "xbsIndex_r4/Gateway Out"
	  SourceType		  "Xilinx Gateway Out Block"
	  infoedit		  "Gateway out block.  Converts Xilinx fixed-point or floating-point type inputs into ouputs of type Simu"
	  "link integer, single, double, or fixed-point.<br><br>Hardware notes:  In hardware these blocks become top level out"
	  "put ports or are discarded, depending on how they are configured."
	  inherit_from_input	  off
	  hdl_port		  on
	  timing_constraint	  "None"
	  locs_specified	  off
	  LOCs			  "{}"
	  UseAsDAC		  off
	  DACChannel		  "'1'"
	  xl_use_area		  off
	  xl_area		  "[0,0,0,0,0,0,0]"
	  has_advanced_control	  "0"
	  sggui_pos		  "-1,-1,-1,-1"
	  block_type		  "gatewayout"
	  sg_icon_stat		  "60,20,1,1,white,yellow,1,cc31b7ac,right,,[ ],[ ]"
	  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 0 ],[0 0 20 20 0 ],[0.95 0.93 0.65"
	  " ]);\nplot([0 60 60 0 0 ],[0 0 20 20 0 ]);\npatch([25.55 28.44 30.44 32.44 34.44 30.44 27.55 25.55 ],[12.22 12.22 1"
	  "4.22 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([27.55 30.44 28.44 25.55 27.55 ],[10.22 10.22 12.22 12.22 10"
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	  "f('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'"
	  " ');\ncolor('black');port_label('output',1,'\\fontsize{11pt}\\bf Out ','texmode','on');\nfprintf('','COMMENT: end i"
	  "con text');"
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	Block {
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	  SID			  "215:269"
	  Ports			  [1, 1]
	  Position		  [660, 790, 720, 810]
	  LibraryVersion	  "1.2"
	  SourceBlock		  "xbsIndex_r4/Gateway Out"
	  SourceType		  "Xilinx Gateway Out Block"
	  infoedit		  "Gateway out block.  Converts Xilinx fixed-point or floating-point type inputs into ouputs of type Simu"
	  "link integer, single, double, or fixed-point.<br><br>Hardware notes:  In hardware these blocks become top level out"
	  "put ports or are discarded, depending on how they are configured."
	  inherit_from_input	  off
	  hdl_port		  on
	  timing_constraint	  "None"
	  locs_specified	  off
	  LOCs			  "{}"
	  UseAsDAC		  off
	  DACChannel		  "'1'"
	  xl_use_area		  off
	  xl_area		  "[0,0,0,0,0,0,0]"
	  has_advanced_control	  "0"
	  sggui_pos		  "-1,-1,-1,-1"
	  block_type		  "gatewayout"
	  sg_icon_stat		  "60,20,1,1,white,yellow,1,cc31b7ac,right,,[ ],[ ]"
	  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 0 ],[0 0 20 20 0 ],[0.95 0.93 0.65"
	  " ]);\nplot([0 60 60 0 0 ],[0 0 20 20 0 ]);\npatch([25.55 28.44 30.44 32.44 34.44 30.44 27.55 25.55 ],[12.22 12.22 1"
	  "4.22 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([27.55 30.44 28.44 25.55 27.55 ],[10.22 10.22 12.22 12.22 10"
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	  "f('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'"
	  " ');\ncolor('black');port_label('output',1,'\\fontsize{11pt}\\bf Out ','texmode','on');\nfprintf('','COMMENT: end i"
	  "con text');"
	}
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	  Name			  "S_AXI_RDATA"
	  SID			  "215:271"
	  Ports			  [1, 1]
	  Position		  [660, 860, 720, 880]
	  LibraryVersion	  "1.2"
	  SourceBlock		  "xbsIndex_r4/Gateway Out"
	  SourceType		  "Xilinx Gateway Out Block"
	  infoedit		  "Gateway out block.  Converts Xilinx fixed-point or floating-point type inputs into ouputs of type Simu"
	  "link integer, single, double, or fixed-point.<br><br>Hardware notes:  In hardware these blocks become top level out"
	  "put ports or are discarded, depending on how they are configured."
	  inherit_from_input	  off
	  hdl_port		  on
	  timing_constraint	  "None"
	  locs_specified	  off
	  LOCs			  "{}"
	  UseAsDAC		  off
	  DACChannel		  "'1'"
	  xl_use_area		  off
	  xl_area		  "[0,0,0,0,0,0,0]"
	  has_advanced_control	  "0"
	  sggui_pos		  "-1,-1,-1,-1"
	  block_type		  "gatewayout"
	  sg_icon_stat		  "60,20,1,1,white,yellow,1,cc31b7ac,right,,[ ],[ ]"
	  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 0 ],[0 0 20 20 0 ],[0.95 0.93 0.65"
	  " ]);\nplot([0 60 60 0 0 ],[0 0 20 20 0 ]);\npatch([25.55 28.44 30.44 32.44 34.44 30.44 27.55 25.55 ],[12.22 12.22 1"
	  "4.22 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([27.55 30.44 28.44 25.55 27.55 ],[10.22 10.22 12.22 12.22 10"
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	  "f('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'"
	  " ');\ncolor('black');port_label('output',1,'\\fontsize{11pt}\\bf Out ','texmode','on');\nfprintf('','COMMENT: end i"
	  "con text');"
	}
	Block {
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	  Name			  "S_AXI_RID"
	  SID			  "215:273"
	  Ports			  [1, 1]
	  Position		  [660, 925, 720, 945]
	  LibraryVersion	  "1.2"
	  SourceBlock		  "xbsIndex_r4/Gateway Out"
	  SourceType		  "Xilinx Gateway Out Block"
	  infoedit		  "Gateway out block.  Converts Xilinx fixed-point or floating-point type inputs into ouputs of type Simu"
	  "link integer, single, double, or fixed-point.<br><br>Hardware notes:  In hardware these blocks become top level out"
	  "put ports or are discarded, depending on how they are configured."
	  inherit_from_input	  off
	  hdl_port		  on
	  timing_constraint	  "None"
	  locs_specified	  off
	  LOCs			  "{}"
	  UseAsDAC		  off
	  DACChannel		  "'1'"
	  xl_use_area		  off
	  xl_area		  "[0,0,0,0,0,0,0]"
	  has_advanced_control	  "0"
	  sggui_pos		  "-1,-1,-1,-1"
	  block_type		  "gatewayout"
	  sg_icon_stat		  "60,20,1,1,white,yellow,1,cc31b7ac,right,,[ ],[ ]"
	  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 0 ],[0 0 20 20 0 ],[0.95 0.93 0.65"
	  " ]);\nplot([0 60 60 0 0 ],[0 0 20 20 0 ]);\npatch([25.55 28.44 30.44 32.44 34.44 30.44 27.55 25.55 ],[12.22 12.22 1"
	  "4.22 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([27.55 30.44 28.44 25.55 27.55 ],[10.22 10.22 12.22 12.22 10"
	  ".22 ],[0.985 0.979 0.895 ]);\npatch([25.55 28.44 30.44 27.55 25.55 ],[8.22 8.22 10.22 10.22 8.22 ],[1 1 1 ]);\npatc"
	  "h([27.55 34.44 32.44 30.44 28.44 25.55 27.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.985 0.979 0.895 ]);\nfprint"
	  "f('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'"
	  " ');\ncolor('black');port_label('output',1,'\\fontsize{11pt}\\bf Out ','texmode','on');\nfprintf('','COMMENT: end i"
	  "con text');"
	}
	Block {
	  BlockType		  Reference
	  Name			  "S_AXI_RLAST"
	  SID			  "215:275"
	  Ports			  [1, 1]
	  Position		  [660, 995, 720, 1015]
	  LibraryVersion	  "1.2"
	  SourceBlock		  "xbsIndex_r4/Gateway Out"
	  SourceType		  "Xilinx Gateway Out Block"
	  infoedit		  "Gateway out block.  Converts Xilinx fixed-point or floating-point type inputs into ouputs of type Simu"
	  "link integer, single, double, or fixed-point.<br><br>Hardware notes:  In hardware these blocks become top level out"
	  "put ports or are discarded, depending on how they are configured."
	  inherit_from_input	  off
	  hdl_port		  on
	  timing_constraint	  "None"
	  locs_specified	  off
	  LOCs			  "{}"
	  UseAsDAC		  off
	  DACChannel		  "'1'"
	  xl_use_area		  off
	  xl_area		  "[0,0,0,0,0,0,0]"
	  has_advanced_control	  "0"
	  sggui_pos		  "-1,-1,-1,-1"
	  block_type		  "gatewayout"
	  sg_icon_stat		  "60,20,1,1,white,yellow,1,cc31b7ac,right,,[ ],[ ]"
	  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 0 ],[0 0 20 20 0 ],[0.95 0.93 0.65"
	  " ]);\nplot([0 60 60 0 0 ],[0 0 20 20 0 ]);\npatch([25.55 28.44 30.44 32.44 34.44 30.44 27.55 25.55 ],[12.22 12.22 1"
	  "4.22 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([27.55 30.44 28.44 25.55 27.55 ],[10.22 10.22 12.22 12.22 10"
	  ".22 ],[0.985 0.979 0.895 ]);\npatch([25.55 28.44 30.44 27.55 25.55 ],[8.22 8.22 10.22 10.22 8.22 ],[1 1 1 ]);\npatc"
	  "h([27.55 34.44 32.44 30.44 28.44 25.55 27.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.985 0.979 0.895 ]);\nfprint"
	  "f('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'"
	  " ');\ncolor('black');port_label('output',1,'\\fontsize{11pt}\\bf Out ','texmode','on');\nfprintf('','COMMENT: end i"
	  "con text');"
	}
	Block {
	  BlockType		  Reference
	  Name			  "S_AXI_RREADY"
	  SID			  "215:251"
	  Ports			  [1, 1]
	  Position		  [145, 1410, 210, 1430]
	  LibraryVersion	  "1.2"
	  SourceBlock		  "xbsIndex_r4/Gateway In"
	  SourceType		  "Xilinx Gateway In Block"
	  infoedit		  "Gateway in block.  Converts inputs of type Simulink integer, single, double and fixed-point to  Xilinx"
	  " fixed-point or floating-point data type.<br><br>Hardware notes:  In hardware these blocks become top level input p"
	  "orts."
	  gui_display_data_type	  "Fixed-point"
	  arith_type		  "Boolean"
	  n_bits		  "16"
	  bin_pt		  "14"
	  preci_type		  "Single"
	  exp_width		  "8"
	  frac_width		  "24"
	  quantization		  "Round  (unbiased: +/- Inf)"
	  overflow		  "Saturate"
	  period		  "xlGetNormalizedPeriod()"
	  dbl_ovrd		  off
	  timing_constraint	  "None"
	  locs_specified	  off
	  LOCs			  "{}"
	  UseAsADC		  off
	  ADCChannel		  "'1'"
	  xl_use_area		  off
	  xl_area		  "[0,0,0,0,0,0,0]"
	  inherit_from_input	  off
	  hdl_port		  "on"
	  has_advanced_control	  "0"
	  sggui_pos		  "-1,-1,-1,-1"
	  block_type		  "gatewayin"
	  sg_icon_stat		  "65,20,1,1,white,yellow,1,00d3666e,right,,[ ],[ ]"
	  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 65 65 0 0 ],[0 0 20 20 0 ],[0.95 0.93 0.65"
	  " ]);\nplot([0 65 65 0 0 ],[0 0 20 20 0 ]);\npatch([27.55 30.44 32.44 34.44 36.44 32.44 29.55 27.55 ],[12.22 12.22 1"
	  "4.22 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([29.55 32.44 30.44 27.55 29.55 ],[10.22 10.22 12.22 12.22 10"
	  ".22 ],[0.985 0.979 0.895 ]);\npatch([27.55 30.44 32.44 29.55 27.55 ],[8.22 8.22 10.22 10.22 8.22 ],[1 1 1 ]);\npatc"
	  "h([29.55 36.44 34.44 32.44 30.44 27.55 29.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.985 0.979 0.895 ]);\nfprint"
	  "f('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'"
	  "\\fontsize{11pt}\\bf In ','texmode','on');\ncolor('black');port_label('output',1,' ');\nfprintf('','COMMENT: end ic"
	  "on text');"
	}
	Block {
	  BlockType		  Reference
	  Name			  "S_AXI_RRESP"
	  SID			  "215:277"
	  Ports			  [1, 1]
	  Position		  [660, 1065, 720, 1085]
	  LibraryVersion	  "1.2"
	  SourceBlock		  "xbsIndex_r4/Gateway Out"
	  SourceType		  "Xilinx Gateway Out Block"
	  infoedit		  "Gateway out block.  Converts Xilinx fixed-point or floating-point type inputs into ouputs of type Simu"
	  "link integer, single, double, or fixed-point.<br><br>Hardware notes:  In hardware these blocks become top level out"
	  "put ports or are discarded, depending on how they are configured."
	  inherit_from_input	  off
	  hdl_port		  on
	  timing_constraint	  "None"
	  locs_specified	  off
	  LOCs			  "{}"
	  UseAsDAC		  off
	  DACChannel		  "'1'"
	  xl_use_area		  off
	  xl_area		  "[0,0,0,0,0,0,0]"
	  has_advanced_control	  "0"
	  sggui_pos		  "-1,-1,-1,-1"
	  block_type		  "gatewayout"
	  sg_icon_stat		  "60,20,1,1,white,yellow,1,cc31b7ac,right,,[ ],[ ]"
	  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 0 ],[0 0 20 20 0 ],[0.95 0.93 0.65"
	  " ]);\nplot([0 60 60 0 0 ],[0 0 20 20 0 ]);\npatch([25.55 28.44 30.44 32.44 34.44 30.44 27.55 25.55 ],[12.22 12.22 1"
	  "4.22 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([27.55 30.44 28.44 25.55 27.55 ],[10.22 10.22 12.22 12.22 10"
	  ".22 ],[0.985 0.979 0.895 ]);\npatch([25.55 28.44 30.44 27.55 25.55 ],[8.22 8.22 10.22 10.22 8.22 ],[1 1 1 ]);\npatc"
	  "h([27.55 34.44 32.44 30.44 28.44 25.55 27.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.985 0.979 0.895 ]);\nfprint"
	  "f('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'"
	  " ');\ncolor('black');port_label('output',1,'\\fontsize{11pt}\\bf Out ','texmode','on');\nfprintf('','COMMENT: end i"
	  "con text');"
	}
	Block {
	  BlockType		  Reference
	  Name			  "S_AXI_RVALID"
	  SID			  "215:279"
	  Ports			  [1, 1]
	  Position		  [660, 1130, 720, 1150]
	  LibraryVersion	  "1.2"
	  SourceBlock		  "xbsIndex_r4/Gateway Out"
	  SourceType		  "Xilinx Gateway Out Block"
	  infoedit		  "Gateway out block.  Converts Xilinx fixed-point or floating-point type inputs into ouputs of type Simu"
	  "link integer, single, double, or fixed-point.<br><br>Hardware notes:  In hardware these blocks become top level out"
	  "put ports or are discarded, depending on how they are configured."
	  inherit_from_input	  off
	  hdl_port		  on
	  timing_constraint	  "None"
	  locs_specified	  off
	  LOCs			  "{}"
	  UseAsDAC		  off
	  DACChannel		  "'1'"
	  xl_use_area		  off
	  xl_area		  "[0,0,0,0,0,0,0]"
	  has_advanced_control	  "0"
	  sggui_pos		  "-1,-1,-1,-1"
	  block_type		  "gatewayout"
	  sg_icon_stat		  "60,20,1,1,white,yellow,1,cc31b7ac,right,,[ ],[ ]"
	  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 0 ],[0 0 20 20 0 ],[0.95 0.93 0.65"
	  " ]);\nplot([0 60 60 0 0 ],[0 0 20 20 0 ]);\npatch([25.55 28.44 30.44 32.44 34.44 30.44 27.55 25.55 ],[12.22 12.22 1"
	  "4.22 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([27.55 30.44 28.44 25.55 27.55 ],[10.22 10.22 12.22 12.22 10"
	  ".22 ],[0.985 0.979 0.895 ]);\npatch([25.55 28.44 30.44 27.55 25.55 ],[8.22 8.22 10.22 10.22 8.22 ],[1 1 1 ]);\npatc"
	  "h([27.55 34.44 32.44 30.44 28.44 25.55 27.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.985 0.979 0.895 ]);\nfprint"
	  "f('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'"
	  " ');\ncolor('black');port_label('output',1,'\\fontsize{11pt}\\bf Out ','texmode','on');\nfprintf('','COMMENT: end i"
	  "con text');"
	}
	Block {
	  BlockType		  Reference
	  Name			  "S_AXI_WDATA"
	  SID			  "215:253"
	  Ports			  [1, 1]
	  Position		  [145, 1475, 210, 1495]
	  LibraryVersion	  "1.2"
	  SourceBlock		  "xbsIndex_r4/Gateway In"
	  SourceType		  "Xilinx Gateway In Block"
	  infoedit		  "Gateway in block.  Converts inputs of type Simulink integer, single, double and fixed-point to  Xilinx"
	  " fixed-point or floating-point data type.<br><br>Hardware notes:  In hardware these blocks become top level input p"
	  "orts."
	  gui_display_data_type	  "Fixed-point"
	  arith_type		  "Unsigned"
	  n_bits		  "32"
	  bin_pt		  "0"
	  preci_type		  "Single"
	  exp_width		  "8"
	  frac_width		  "24"
	  quantization		  "Round  (unbiased: +/- Inf)"
	  overflow		  "Saturate"
	  period		  "xlGetNormalizedPeriod()"
	  dbl_ovrd		  off
	  timing_constraint	  "None"
	  locs_specified	  off
	  LOCs			  "{}"
	  UseAsADC		  off
	  ADCChannel		  "'1'"
	  xl_use_area		  off
	  xl_area		  "[0,0,0,0,0,0,0]"
	  inherit_from_input	  off
	  hdl_port		  "on"
	  has_advanced_control	  "0"
	  sggui_pos		  "-1,-1,-1,-1"
	  block_type		  "gatewayin"
	  sg_icon_stat		  "65,20,1,1,white,yellow,1,00d3666e,right,,[ ],[ ]"
	  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 65 65 0 0 ],[0 0 20 20 0 ],[0.95 0.93 0.65"
	  " ]);\nplot([0 65 65 0 0 ],[0 0 20 20 0 ]);\npatch([27.55 30.44 32.44 34.44 36.44 32.44 29.55 27.55 ],[12.22 12.22 1"
	  "4.22 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([29.55 32.44 30.44 27.55 29.55 ],[10.22 10.22 12.22 12.22 10"
	  ".22 ],[0.985 0.979 0.895 ]);\npatch([27.55 30.44 32.44 29.55 27.55 ],[8.22 8.22 10.22 10.22 8.22 ],[1 1 1 ]);\npatc"
	  "h([29.55 36.44 34.44 32.44 30.44 27.55 29.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.985 0.979 0.895 ]);\nfprint"
	  "f('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'"
	  "\\fontsize{11pt}\\bf In ','texmode','on');\ncolor('black');port_label('output',1,' ');\nfprintf('','COMMENT: end ic"
	  "on text');"
	}
	Block {
	  BlockType		  Reference
	  Name			  "S_AXI_WLAST"
	  SID			  "215:255"
	  Ports			  [1, 1]
	  Position		  [145, 1545, 210, 1565]
	  LibraryVersion	  "1.2"
	  SourceBlock		  "xbsIndex_r4/Gateway In"
	  SourceType		  "Xilinx Gateway In Block"
	  infoedit		  "Gateway in block.  Converts inputs of type Simulink integer, single, double and fixed-point to  Xilinx"
	  " fixed-point or floating-point data type.<br><br>Hardware notes:  In hardware these blocks become top level input p"
	  "orts."
	  gui_display_data_type	  "Fixed-point"
	  arith_type		  "Boolean"
	  n_bits		  "16"
	  bin_pt		  "14"
	  preci_type		  "Single"
	  exp_width		  "8"
	  frac_width		  "24"
	  quantization		  "Round  (unbiased: +/- Inf)"
	  overflow		  "Saturate"
	  period		  "xlGetNormalizedPeriod()"
	  dbl_ovrd		  off
	  timing_constraint	  "None"
	  locs_specified	  off
	  LOCs			  "{}"
	  UseAsADC		  off
	  ADCChannel		  "'1'"
	  xl_use_area		  off
	  xl_area		  "[0,0,0,0,0,0,0]"
	  inherit_from_input	  off
	  hdl_port		  "on"
	  has_advanced_control	  "0"
	  sggui_pos		  "-1,-1,-1,-1"
	  block_type		  "gatewayin"
	  sg_icon_stat		  "65,20,1,1,white,yellow,1,00d3666e,right,,[ ],[ ]"
	  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 65 65 0 0 ],[0 0 20 20 0 ],[0.95 0.93 0.65"
	  " ]);\nplot([0 65 65 0 0 ],[0 0 20 20 0 ]);\npatch([27.55 30.44 32.44 34.44 36.44 32.44 29.55 27.55 ],[12.22 12.22 1"
	  "4.22 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([29.55 32.44 30.44 27.55 29.55 ],[10.22 10.22 12.22 12.22 10"
	  ".22 ],[0.985 0.979 0.895 ]);\npatch([27.55 30.44 32.44 29.55 27.55 ],[8.22 8.22 10.22 10.22 8.22 ],[1 1 1 ]);\npatc"
	  "h([29.55 36.44 34.44 32.44 30.44 27.55 29.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.985 0.979 0.895 ]);\nfprint"
	  "f('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'"
	  "\\fontsize{11pt}\\bf In ','texmode','on');\ncolor('black');port_label('output',1,' ');\nfprintf('','COMMENT: end ic"
	  "on text');"
	}
	Block {
	  BlockType		  Reference
	  Name			  "S_AXI_WREADY"
	  SID			  "215:281"
	  Ports			  [1, 1]
	  Position		  [660, 1200, 720, 1220]
	  LibraryVersion	  "1.2"
	  SourceBlock		  "xbsIndex_r4/Gateway Out"
	  SourceType		  "Xilinx Gateway Out Block"
	  infoedit		  "Gateway out block.  Converts Xilinx fixed-point or floating-point type inputs into ouputs of type Simu"
	  "link integer, single, double, or fixed-point.<br><br>Hardware notes:  In hardware these blocks become top level out"
	  "put ports or are discarded, depending on how they are configured."
	  inherit_from_input	  off
	  hdl_port		  on
	  timing_constraint	  "None"
	  locs_specified	  off
	  LOCs			  "{}"
	  UseAsDAC		  off
	  DACChannel		  "'1'"
	  xl_use_area		  off
	  xl_area		  "[0,0,0,0,0,0,0]"
	  has_advanced_control	  "0"
	  sggui_pos		  "-1,-1,-1,-1"
	  block_type		  "gatewayout"
	  sg_icon_stat		  "60,20,1,1,white,yellow,1,cc31b7ac,right,,[ ],[ ]"
	  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 0 ],[0 0 20 20 0 ],[0.95 0.93 0.65"
	  " ]);\nplot([0 60 60 0 0 ],[0 0 20 20 0 ]);\npatch([25.55 28.44 30.44 32.44 34.44 30.44 27.55 25.55 ],[12.22 12.22 1"
	  "4.22 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([27.55 30.44 28.44 25.55 27.55 ],[10.22 10.22 12.22 12.22 10"
	  ".22 ],[0.985 0.979 0.895 ]);\npatch([25.55 28.44 30.44 27.55 25.55 ],[8.22 8.22 10.22 10.22 8.22 ],[1 1 1 ]);\npatc"
	  "h([27.55 34.44 32.44 30.44 28.44 25.55 27.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.985 0.979 0.895 ]);\nfprint"
	  "f('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'"
	  " ');\ncolor('black');port_label('output',1,'\\fontsize{11pt}\\bf Out ','texmode','on');\nfprintf('','COMMENT: end i"
	  "con text');"
	}
	Block {
	  BlockType		  Reference
	  Name			  "S_AXI_WSTRB"
	  SID			  "215:257"
	  Ports			  [1, 1]
	  Position		  [145, 1615, 210, 1635]
	  LibraryVersion	  "1.2"
	  SourceBlock		  "xbsIndex_r4/Gateway In"
	  SourceType		  "Xilinx Gateway In Block"
	  infoedit		  "Gateway in block.  Converts inputs of type Simulink integer, single, double and fixed-point to  Xilinx"
	  " fixed-point or floating-point data type.<br><br>Hardware notes:  In hardware these blocks become top level input p"
	  "orts."
	  gui_display_data_type	  "Fixed-point"
	  arith_type		  "Unsigned"
	  n_bits		  "4"
	  bin_pt		  "0"
	  preci_type		  "Single"
	  exp_width		  "8"
	  frac_width		  "24"
	  quantization		  "Round  (unbiased: +/- Inf)"
	  overflow		  "Saturate"
	  period		  "xlGetNormalizedPeriod()"
	  dbl_ovrd		  off
	  timing_constraint	  "None"
	  locs_specified	  off
	  LOCs			  "{}"
	  UseAsADC		  off
	  ADCChannel		  "'1'"
	  xl_use_area		  off
	  xl_area		  "[0,0,0,0,0,0,0]"
	  inherit_from_input	  off
	  hdl_port		  "on"
	  has_advanced_control	  "0"
	  sggui_pos		  "-1,-1,-1,-1"
	  block_type		  "gatewayin"
	  sg_icon_stat		  "65,20,1,1,white,yellow,1,00d3666e,right,,[ ],[ ]"
	  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 65 65 0 0 ],[0 0 20 20 0 ],[0.95 0.93 0.65"
	  " ]);\nplot([0 65 65 0 0 ],[0 0 20 20 0 ]);\npatch([27.55 30.44 32.44 34.44 36.44 32.44 29.55 27.55 ],[12.22 12.22 1"
	  "4.22 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([29.55 32.44 30.44 27.55 29.55 ],[10.22 10.22 12.22 12.22 10"
	  ".22 ],[0.985 0.979 0.895 ]);\npatch([27.55 30.44 32.44 29.55 27.55 ],[8.22 8.22 10.22 10.22 8.22 ],[1 1 1 ]);\npatc"
	  "h([29.55 36.44 34.44 32.44 30.44 27.55 29.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.985 0.979 0.895 ]);\nfprint"
	  "f('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'"
	  "\\fontsize{11pt}\\bf In ','texmode','on');\ncolor('black');port_label('output',1,' ');\nfprintf('','COMMENT: end ic"
	  "on text');"
	}
	Block {
	  BlockType		  Reference
	  Name			  "S_AXI_WVALID"
	  SID			  "215:259"
	  Ports			  [1, 1]
	  Position		  [145, 1680, 210, 1700]
	  LibraryVersion	  "1.2"
	  SourceBlock		  "xbsIndex_r4/Gateway In"
	  SourceType		  "Xilinx Gateway In Block"
	  infoedit		  "Gateway in block.  Converts inputs of type Simulink integer, single, double and fixed-point to  Xilinx"
	  " fixed-point or floating-point data type.<br><br>Hardware notes:  In hardware these blocks become top level input p"
	  "orts."
	  gui_display_data_type	  "Fixed-point"
	  arith_type		  "Boolean"
	  n_bits		  "16"
	  bin_pt		  "14"
	  preci_type		  "Single"
	  exp_width		  "8"
	  frac_width		  "24"
	  quantization		  "Round  (unbiased: +/- Inf)"
	  overflow		  "Saturate"
	  period		  "xlGetNormalizedPeriod()"
	  dbl_ovrd		  off
	  timing_constraint	  "None"
	  locs_specified	  off
	  LOCs			  "{}"
	  UseAsADC		  off
	  ADCChannel		  "'1'"
	  xl_use_area		  off
	  xl_area		  "[0,0,0,0,0,0,0]"
	  inherit_from_input	  off
	  hdl_port		  "on"
	  has_advanced_control	  "0"
	  sggui_pos		  "-1,-1,-1,-1"
	  block_type		  "gatewayin"
	  sg_icon_stat		  "65,20,1,1,white,yellow,1,00d3666e,right,,[ ],[ ]"
	  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 65 65 0 0 ],[0 0 20 20 0 ],[0.95 0.93 0.65"
	  " ]);\nplot([0 65 65 0 0 ],[0 0 20 20 0 ]);\npatch([27.55 30.44 32.44 34.44 36.44 32.44 29.55 27.55 ],[12.22 12.22 1"
	  "4.22 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([29.55 32.44 30.44 27.55 29.55 ],[10.22 10.22 12.22 12.22 10"
	  ".22 ],[0.985 0.979 0.895 ]);\npatch([27.55 30.44 32.44 29.55 27.55 ],[8.22 8.22 10.22 10.22 8.22 ],[1 1 1 ]);\npatc"
	  "h([29.55 36.44 34.44 32.44 30.44 27.55 29.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.985 0.979 0.895 ]);\nfprint"
	  "f('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'"
	  "\\fontsize{11pt}\\bf In ','texmode','on');\ncolor('black');port_label('output',1,' ');\nfprintf('','COMMENT: end ic"
	  "on text');"
	}
	Block {
	  BlockType		  Terminator
	  Name			  "Terminator"
	  SID			  "215:260"
	  Position		  [820, 520, 840, 540]
	  ShowName		  off
	  MaskIconFrame		  on
	  MaskIconOpaque	  on
	  MaskIconRotate	  "none"
	  MaskPortRotate	  "default"
	  MaskIconUnits		  "autoscale"
	}
	Block {
	  BlockType		  Terminator
	  Name			  "Terminator1"
	  SID			  "215:262"
	  Position		  [820, 585, 840, 605]
	  ShowName		  off
	  MaskIconFrame		  on
	  MaskIconOpaque	  on
	  MaskIconRotate	  "none"
	  MaskPortRotate	  "default"
	  MaskIconUnits		  "autoscale"
	}
	Block {
	  BlockType		  Terminator
	  Name			  "Terminator10"
	  SID			  "215:280"
	  Position		  [820, 1200, 840, 1220]
	  ShowName		  off
	  MaskIconFrame		  on
	  MaskIconOpaque	  on
	  MaskIconRotate	  "none"
	  MaskPortRotate	  "default"
	  MaskIconUnits		  "autoscale"
	}
	Block {
	  BlockType		  Terminator
	  Name			  "Terminator2"
	  SID			  "215:264"
	  Position		  [820, 655, 840, 675]
	  ShowName		  off
	  MaskIconFrame		  on
	  MaskIconOpaque	  on
	  MaskIconRotate	  "none"
	  MaskPortRotate	  "default"
	  MaskIconUnits		  "autoscale"
	}
	Block {
	  BlockType		  Terminator
	  Name			  "Terminator3"
	  SID			  "215:266"
	  Position		  [820, 725, 840, 745]
	  ShowName		  off
	  MaskIconFrame		  on
	  MaskIconOpaque	  on
	  MaskIconRotate	  "none"
	  MaskPortRotate	  "default"
	  MaskIconUnits		  "autoscale"
	}
	Block {
	  BlockType		  Terminator
	  Name			  "Terminator4"
	  SID			  "215:268"
	  Position		  [820, 790, 840, 810]
	  ShowName		  off
	  MaskIconFrame		  on
	  MaskIconOpaque	  on
	  MaskIconRotate	  "none"
	  MaskPortRotate	  "default"
	  MaskIconUnits		  "autoscale"
	}
	Block {
	  BlockType		  Terminator
	  Name			  "Terminator5"
	  SID			  "215:270"
	  Position		  [820, 860, 840, 880]
	  ShowName		  off
	  MaskIconFrame		  on
	  MaskIconOpaque	  on
	  MaskIconRotate	  "none"
	  MaskPortRotate	  "default"
	  MaskIconUnits		  "autoscale"
	}
	Block {
	  BlockType		  Terminator
	  Name			  "Terminator6"
	  SID			  "215:272"
	  Position		  [820, 925, 840, 945]
	  ShowName		  off
	  MaskIconFrame		  on
	  MaskIconOpaque	  on
	  MaskIconRotate	  "none"
	  MaskPortRotate	  "default"
	  MaskIconUnits		  "autoscale"
	}
	Block {
	  BlockType		  Terminator
	  Name			  "Terminator7"
	  SID			  "215:274"
	  Position		  [820, 995, 840, 1015]
	  ShowName		  off
	  MaskIconFrame		  on
	  MaskIconOpaque	  on
	  MaskIconRotate	  "none"
	  MaskPortRotate	  "default"
	  MaskIconUnits		  "autoscale"
	}
	Block {
	  BlockType		  Terminator
	  Name			  "Terminator8"
	  SID			  "215:276"
	  Position		  [820, 1065, 840, 1085]
	  ShowName		  off
	  MaskIconFrame		  on
	  MaskIconOpaque	  on
	  MaskIconRotate	  "none"
	  MaskPortRotate	  "default"
	  MaskIconUnits		  "autoscale"
	}
	Block {
	  BlockType		  Terminator
	  Name			  "Terminator9"
	  SID			  "215:278"
	  Position		  [820, 1130, 840, 1150]
	  ShowName		  off
	  MaskIconFrame		  on
	  MaskIconOpaque	  on
	  MaskIconRotate	  "none"
	  MaskPortRotate	  "default"
	  MaskIconUnits		  "autoscale"
	}
	Block {
	  BlockType		  Reference
	  Name			  "To Register"
	  SID			  "215:207"
	  Ports			  [2, 1]
	  Position		  [660, 1267, 720, 1323]
	  AttributesFormatString  "<< %<shared_memory_name> >>"
	  LibraryVersion	  "1.2"
	  SourceBlock		  "xbsIndex_r4/To Register"
	  SourceType		  "Xilinx Shared Memory Based To Register Block"
	  infoedit		  "Register block that writes data to a shared memory register.  Delay of one sample period."
	  shared_memory_name	  "'NEW_MAC_TIME_MSB'"
	  init			  "0"
	  ownership		  "Owned and initialized elsewhere"
	  explicit_data_type	  on
	  gui_display_data_type	  "Fixed-point"
	  arith_type		  "Unsigned"
	  n_bits		  "32"
	  bin_pt		  "0"
	  preci_type		  "Single"
	  dbl_ovrd		  off
	  xl_use_area		  off
	  xl_area		  "[0,0,0,0,0,0,0]"
	  has_advanced_control	  "0"
	  sggui_pos		  "-1,-1,-1,-1"
	  block_type		  "toreg"
	  sg_icon_stat		  "60,56,2,1,white,blue,0,10ab453e,right,,[ ],[ ]"
	  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 0 ],[0 0 56 56 0 ],[0.77 0.82 0.91"
	  " ]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\npatch([12.2 23.76 31.76 39.76 47.76 31.76 20.2 12.2 ],[36.88 36.88 44.8"
	  "8 36.88 44.88 44.88 44.88 36.88 ],[1 1 1 ]);\npatch([20.2 31.76 23.76 12.2 20.2 ],[28.88 28.88 36.88 36.88 28.88 ],"
	  "[0.931 0.946 0.973 ]);\npatch([12.2 23.76 31.76 20.2 12.2 ],[20.88 20.88 28.88 28.88 20.88 ],[1 1 1 ]);\npatch([20."
	  "2 47.76 39.76 31.76 23.76 12.2 20.2 ],[12.88 12.88 20.88 12.88 20.88 20.88 12.88 ],[0.931 0.946 0.973 ]);\nfprintf("
	  "'','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'di"
	  "n');\ncolor('black');port_label('input',2,'en');\ncolor('black');port_label('output',1,'dout');\nfprintf('','COMMEN"
	  "T: end icon text');"
	}
	Block {
	  BlockType		  Reference
	  Name			  "To Register1"
	  SID			  "215:208"
	  Ports			  [2, 1]
	  Position		  [660, 1372, 720, 1428]
	  AttributesFormatString  "<< %<shared_memory_name> >>"
	  LibraryVersion	  "1.2"
	  SourceBlock		  "xbsIndex_r4/To Register"
	  SourceType		  "Xilinx Shared Memory Based To Register Block"
	  infoedit		  "Register block that writes data to a shared memory register.  Delay of one sample period."
	  shared_memory_name	  "'NEW_MAC_TIME_LSB'"
	  init			  "0"
	  ownership		  "Owned and initialized elsewhere"
	  explicit_data_type	  on
	  gui_display_data_type	  "Fixed-point"
	  arith_type		  "Unsigned"
	  n_bits		  "32"
	  bin_pt		  "0"
	  preci_type		  "Single"
	  dbl_ovrd		  off
	  xl_use_area		  off
	  xl_area		  "[0,0,0,0,0,0,0]"
	  has_advanced_control	  "0"
	  sggui_pos		  "-1,-1,-1,-1"
	  block_type		  "toreg"
	  sg_icon_stat		  "60,56,2,1,white,blue,0,10ab453e,right,,[ ],[ ]"
	  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 0 ],[0 0 56 56 0 ],[0.77 0.82 0.91"
	  " ]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\npatch([12.2 23.76 31.76 39.76 47.76 31.76 20.2 12.2 ],[36.88 36.88 44.8"
	  "8 36.88 44.88 44.88 44.88 36.88 ],[1 1 1 ]);\npatch([20.2 31.76 23.76 12.2 20.2 ],[28.88 28.88 36.88 36.88 28.88 ],"
	  "[0.931 0.946 0.973 ]);\npatch([12.2 23.76 31.76 20.2 12.2 ],[20.88 20.88 28.88 28.88 20.88 ],[1 1 1 ]);\npatch([20."
	  "2 47.76 39.76 31.76 23.76 12.2 20.2 ],[12.88 12.88 20.88 12.88 20.88 20.88 12.88 ],[0.931 0.946 0.973 ]);\nfprintf("
	  "'','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'di"
	  "n');\ncolor('black');port_label('input',2,'en');\ncolor('black');port_label('output',1,'dout');\nfprintf('','COMMEN"
	  "T: end icon text');"
	}
	Block {
	  BlockType		  Reference
	  Name			  "To Register2"
	  SID			  "215:209"
	  Ports			  [2, 1]
	  Position		  [660, 1477, 720, 1533]
	  AttributesFormatString  "<< %<shared_memory_name> >>"
	  LibraryVersion	  "1.2"
	  SourceBlock		  "xbsIndex_r4/To Register"
	  SourceType		  "Xilinx Shared Memory Based To Register Block"
	  infoedit		  "Register block that writes data to a shared memory register.  Delay of one sample period."
	  shared_memory_name	  "'Control'"
	  init			  "0"
	  ownership		  "Owned and initialized elsewhere"
	  explicit_data_type	  on
	  gui_display_data_type	  "Fixed-point"
	  arith_type		  "Unsigned"
	  n_bits		  "32"
	  bin_pt		  "0"
	  preci_type		  "Single"
	  dbl_ovrd		  off
	  xl_use_area		  off
	  xl_area		  "[0,0,0,0,0,0,0]"
	  has_advanced_control	  "0"
	  sggui_pos		  "-1,-1,-1,-1"
	  block_type		  "toreg"
	  sg_icon_stat		  "60,56,2,1,white,blue,0,10ab453e,right,,[ ],[ ]"
	  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 0 ],[0 0 56 56 0 ],[0.77 0.82 0.91"
	  " ]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\npatch([12.2 23.76 31.76 39.76 47.76 31.76 20.2 12.2 ],[36.88 36.88 44.8"
	  "8 36.88 44.88 44.88 44.88 36.88 ],[1 1 1 ]);\npatch([20.2 31.76 23.76 12.2 20.2 ],[28.88 28.88 36.88 36.88 28.88 ],"
	  "[0.931 0.946 0.973 ]);\npatch([12.2 23.76 31.76 20.2 12.2 ],[20.88 20.88 28.88 28.88 20.88 ],[1 1 1 ]);\npatch([20."
	  "2 47.76 39.76 31.76 23.76 12.2 20.2 ],[12.88 12.88 20.88 12.88 20.88 20.88 12.88 ],[0.931 0.946 0.973 ]);\nfprintf("
	  "'','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'di"
	  "n');\ncolor('black');port_label('input',2,'en');\ncolor('black');port_label('output',1,'dout');\nfprintf('','COMMEN"
	  "T: end icon text');"
	}
	Block {
	  BlockType		  Reference
	  Name			  "memmap"
	  SID			  "215:202"
	  Ports			  [32, 17]
	  Position		  [310, 572, 560, 1538]
	  LibraryVersion	  "1.2"
	  SourceBlock		  "xbsEDKLib_r4/EDK Core"
	  SourceType		  "Xilinx EDK Core Block"
	  infoedit		  "For use with EDK Processor block."
	  sim_method		  "Inactive"
	  xl_use_area		  off
	  xl_area		  "[0,0,0,0,0,0,0]"
	  xmp			  "xmp"
	  blockname		  "blockname"
	  dual_clock		  "dual_clock"
	  procinfo		  "procinfo"
	  bus_type		  "bus_type"
	  memxtable		  "memxtable"
	  memmap_hdlcontent	  "library IEEE;\nuse IEEE.std_logic_1164.all;\nuse IEEE.numeric_std.all;\n\nentity axi_sgiface i"
	  "s\n    generic (\n        -- AXI specific.\n        -- TODO: need to figure out a way to pass these generics from o"
	  "utside\n        C_S_AXI_SUPPORT_BURST   : integer := 0;\n        -- TODO: fix the internal ID width to 8\n        C"
	  "_S_AXI_ID_WIDTH        : integer := 8;\n        C_S_AXI_DATA_WIDTH      : integer := 32;\n        C_S_AXI_ADDR_WIDT"
	  "H      : integer := 32;\n        C_S_AXI_TOTAL_ADDR_LEN  : integer := 12;\n        C_S_AXI_LINEAR_ADDR_LEN : intege"
	  "r := 8;\n        C_S_AXI_BANK_ADDR_LEN   : integer := 2;\n        C_S_AXI_AWLEN_WIDTH     : integer := 8;\n        "
	  "C_S_AXI_ARLEN_WIDTH     : integer := 8\n    );\n    port (\n        -- General.\n        AXI_AClk      : in  std_lo"
	  "gic;\n        AXI_AResetN    : in  std_logic;\n        -- not used\n        AXI_Ce        : in  std_logic;\n  \n   "
	  "     -- AXI Port.\n        S_AXI_AWADDR  : in  std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);\n        S_AXI_AWID"
	  "    : in  std_logic_vector(C_S_AXI_ID_WIDTH-1 downto 0);\n        S_AXI_AWLEN   : in  std_logic_vector(C_S_AXI_AWLE"
	  "N_WIDTH-1 downto 0);\n        S_AXI_AWSIZE  : in  std_logic_vector(2 downto 0);\n        S_AXI_AWBURST : in  std_lo"
	  "gic_vector(1 downto 0);\n        S_AXI_AWLOCK  : in  std_logic_vector(1 downto 0);\n        S_AXI_AWCACHE : in  std"
	  "_logic_vector(3 downto 0);\n        S_AXI_AWPROT  : in  std_logic_vector(2 downto 0);\n        S_AXI_AWVALID : in  "
	  "std_logic;\n        S_AXI_AWREADY : out std_logic;\n        \n        S_AXI_WLAST   : in  std_logic;\n        S_AXI"
	  "_WDATA   : in  std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);\n        S_AXI_WSTRB   : in  std_logic_vector((C_S_"
	  "AXI_DATA_WIDTH/8)-1 downto 0);\n        S_AXI_WVALID  : in  std_logic;\n        S_AXI_WREADY  : out std_logic;\n   "
	  "     \n        S_AXI_BRESP   : out std_logic_vector(1 downto 0);\n        S_AXI_BID     : out std_logic_vector(C_S_"
	  "AXI_ID_WIDTH-1 downto 0);\n        S_AXI_BVALID  : out std_logic;\n        S_AXI_BREADY  : in  std_logic;\n        "
	  "\n        S_AXI_ARADDR  : in  std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);\n        S_AXI_ARID    : in  std_log"
	  "ic_vector(C_S_AXI_ID_WIDTH-1 downto 0);\n        S_AXI_ARLEN   : in  std_logic_vector(C_S_AXI_ARLEN_WIDTH-1 downto "
	  "0);\n        S_AXI_ARSIZE  : in  std_logic_vector(2 downto 0);\n        S_AXI_ARBURST : in  std_logic_vector(1 down"
	  "to 0);\n        S_AXI_ARLOCK  : in  std_logic_vector(1 downto 0);\n        S_AXI_ARCACHE : in  std_logic_vector(3 d"
	  "ownto 0);\n        S_AXI_ARPROT  : in  std_logic_vector(2 downto 0);\n        S_AXI_ARVALID : in  std_logic;\n     "
	  "   S_AXI_ARREADY : out std_logic;\n        \n        -- 'From Register'\n        -- 'SYSTEM_TIME_USEC_MSB'\n       "
	  " sm_SYSTEM_TIME_USEC_MSB_dout : in std_logic_vector(32-1 downto 0);\n        -- 'SYSTEM_TIME_USEC_LSB'\n        sm_"
	  "SYSTEM_TIME_USEC_LSB_dout : in std_logic_vector(32-1 downto 0);\n        -- 'MAC_TIME_USEC_MSB'\n        sm_MAC_TIM"
	  "E_USEC_MSB_dout : in std_logic_vector(32-1 downto 0);\n        -- 'MAC_TIME_USEC_LSB'\n        sm_MAC_TIME_USEC_LSB"
	  "_dout : in std_logic_vector(32-1 downto 0);\n        -- 'To Register'\n        -- 'NEW_MAC_TIME_MSB'\n        sm_NE"
	  "W_MAC_TIME_MSB_dout : in std_logic_vector(32-1 downto 0);\n        sm_NEW_MAC_TIME_MSB_din  : out std_logic_vector("
	  "32-1 downto 0);\n        sm_NEW_MAC_TIME_MSB_en   : out std_logic;\n        -- 'NEW_MAC_TIME_LSB'\n        sm_NEW_M"
	  "AC_TIME_LSB_dout : in std_logic_vector(32-1 downto 0);\n        sm_NEW_MAC_TIME_LSB_din  : out std_logic_vector(32-"
	  "1 downto 0);\n        sm_NEW_MAC_TIME_LSB_en   : out std_logic;\n        -- 'Control'\n        sm_Control_dout : in"
	  " std_logic_vector(32-1 downto 0);\n        sm_Control_din  : out std_logic_vector(32-1 downto 0);\n        sm_Contr"
	  "ol_en   : out std_logic;\n        -- 'From FIFO'\n        -- 'To FIFO'\n        -- 'Shared Memory'\n\n        S_AXI"
	  "_RLAST   : out std_logic;\n        S_AXI_RID     : out std_logic_vector(C_S_AXI_ID_WIDTH-1 downto 0);\n        S_AX"
	  "I_RDATA   : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);\n        S_AXI_RRESP   : out std_logic_vector(1 do"
	  "wnto 0);\n        S_AXI_RVALID  : out std_logic;\n        S_AXI_RREADY  : in  std_logic\n    );\nend entity axi_sgi"
	  "face;\n\narchitecture IMP of axi_sgiface is\n\n-- Internal signals for write channel.\nsignal S_AXI_BVALID_i       "
	  ": std_logic;\nsignal S_AXI_BID_i          : std_logic_vector(C_S_AXI_ID_WIDTH-1 downto 0);\nsignal S_AXI_WREADY_i  "
	  "     : std_logic;\n  \n-- Internal signals for read channels.\nsignal S_AXI_ARLEN_i        : std_logic_vector(C_S_A"
	  "XI_ARLEN_WIDTH-1 downto 0);\nsignal S_AXI_RLAST_i        : std_logic;\nsignal S_AXI_RREADY_i       : std_logic;\nsi"
	  "gnal S_AXI_RVALID_i       : std_logic;\nsignal S_AXI_RDATA_i        : std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto "
	  "0);\nsignal S_AXI_RID_i          : std_logic_vector(C_S_AXI_ID_WIDTH-1 downto 0);\n\n-- for read channel\nsignal re"
	  "ad_bank_addr_i     : std_logic_vector(C_S_AXI_BANK_ADDR_LEN-1 downto 0);\nsignal read_linear_addr_i   : std_logic_v"
	  "ector(C_S_AXI_LINEAR_ADDR_LEN-1 downto 0);\n-- for write channel\nsignal write_bank_addr_i    : std_logic_vector(C_"
	  "S_AXI_BANK_ADDR_LEN-1 downto 0);\nsignal write_linear_addr_i  : std_logic_vector(C_S_AXI_LINEAR_ADDR_LEN-1 downto 0"
	  ");\n\nsignal reg_bank_out_i       : std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);\nsignal fifo_bank_out_i      :"
	  " std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);\nsignal shmem_bank_out_i     : std_logic_vector(C_S_AXI_DATA_WIDT"
	  "H-1 downto 0);\n    \n-- 'From Register'\n-- 'SYSTEM_TIME_USEC_MSB'\nsignal sm_SYSTEM_TIME_USEC_MSB_dout_i  : std_l"
	  "ogic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);\n-- 'SYSTEM_TIME_USEC_LSB'\nsignal sm_SYSTEM_TIME_USEC_LSB_dout_i  : st"
	  "d_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);\n-- 'MAC_TIME_USEC_MSB'\nsignal sm_MAC_TIME_USEC_MSB_dout_i  : std_l"
	  "ogic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);\n-- 'MAC_TIME_USEC_LSB'\nsignal sm_MAC_TIME_USEC_LSB_dout_i  : std_logi"
	  "c_vector(C_S_AXI_DATA_WIDTH-1 downto 0);\n-- 'To Register'\n-- 'NEW_MAC_TIME_MSB'\nsignal sm_NEW_MAC_TIME_MSB_din_i"
	  "   : std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);\nsignal sm_NEW_MAC_TIME_MSB_en_i    : std_logic;\nsignal sm_N"
	  "EW_MAC_TIME_MSB_dout_i  : std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);\n-- 'NEW_MAC_TIME_LSB'\nsignal sm_NEW_MA"
	  "C_TIME_LSB_din_i   : std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);\nsignal sm_NEW_MAC_TIME_LSB_en_i    : std_log"
	  "ic;\nsignal sm_NEW_MAC_TIME_LSB_dout_i  : std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);\n-- 'Control'\nsignal sm"
	  "_Control_din_i   : std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);\nsignal sm_Control_en_i    : std_logic;\nsignal"
	  " sm_Control_dout_i  : std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);\n-- 'From FIFO'\n-- 'To FIFO'\n-- 'Shared Me"
	  "mory'\n\ntype t_read_state is (IDLE, READ_PREP, READ_DATA);\nsignal read_state : t_read_state;\n\ntype t_write_stat"
	  "e is (IDLE, WRITE_DATA, WRITE_RESPONSE);\nsignal write_state : t_write_state;\n\ntype t_memmap_state is (READ, WRIT"
	  "E);\nsignal memmap_state : t_memmap_state;\n\nconstant C_READ_PREP_DELAY : std_logic_vector(1 downto 0) := \"11\";\n"
	  "\nsignal read_prep_counter : std_logic_vector(1 downto 0);\nsignal read_addr_counter : std_logic_vector(C_S_AXI_ARL"
	  "EN_WIDTH-1 downto 0);\nsignal read_data_counter : std_logic_vector(C_S_AXI_ARLEN_WIDTH-1 downto 0);\n\n-- enable of"
	  " shared BRAMs\nsignal s_shram_en : std_logic;\n\nsignal write_addr_valid : std_logic;\nsignal write_ready : std_log"
	  "ic;\n\n-- 're' of From/To FIFOs\nsignal s_fifo_re : std_logic;\n-- 'we' of To FIFOs\nsignal s_fifo_we : std_logic;\n"
	  "\nbegin\n\n-- enable for 'Shared Memory' blocks\n\n-- conversion to match with the data bus width\n-- 'From Registe"
	  "r'\n-- 'SYSTEM_TIME_USEC_MSB'\ngen_sm_SYSTEM_TIME_USEC_MSB_dout_i: if (32 < C_S_AXI_DATA_WIDTH) generate\n    sm_SY"
	  "STEM_TIME_USEC_MSB_dout_i(C_S_AXI_DATA_WIDTH-1 downto 32) <= (others => '0');\nend generate gen_sm_SYSTEM_TIME_USEC"
	  "_MSB_dout_i;\nsm_SYSTEM_TIME_USEC_MSB_dout_i(32-1 downto 0) <= sm_SYSTEM_TIME_USEC_MSB_dout;\n-- 'SYSTEM_TIME_USEC_"
	  "LSB'\ngen_sm_SYSTEM_TIME_USEC_LSB_dout_i: if (32 < C_S_AXI_DATA_WIDTH) generate\n    sm_SYSTEM_TIME_USEC_LSB_dout_i"
	  "(C_S_AXI_DATA_WIDTH-1 downto 32) <= (others => '0');\nend generate gen_sm_SYSTEM_TIME_USEC_LSB_dout_i;\nsm_SYSTEM_T"
	  "IME_USEC_LSB_dout_i(32-1 downto 0) <= sm_SYSTEM_TIME_USEC_LSB_dout;\n-- 'MAC_TIME_USEC_MSB'\ngen_sm_MAC_TIME_USEC_M"
	  "SB_dout_i: if (32 < C_S_AXI_DATA_WIDTH) generate\n    sm_MAC_TIME_USEC_MSB_dout_i(C_S_AXI_DATA_WIDTH-1 downto 32) <"
	  "= (others => '0');\nend generate gen_sm_MAC_TIME_USEC_MSB_dout_i;\nsm_MAC_TIME_USEC_MSB_dout_i(32-1 downto 0) <= sm"
	  "_MAC_TIME_USEC_MSB_dout;\n-- 'MAC_TIME_USEC_LSB'\ngen_sm_MAC_TIME_USEC_LSB_dout_i: if (32 < C_S_AXI_DATA_WIDTH) gen"
	  "erate\n    sm_MAC_TIME_USEC_LSB_dout_i(C_S_AXI_DATA_WIDTH-1 downto 32) <= (others => '0');\nend generate gen_sm_MAC"
	  "_TIME_USEC_LSB_dout_i;\nsm_MAC_TIME_USEC_LSB_dout_i(32-1 downto 0) <= sm_MAC_TIME_USEC_LSB_dout;\n-- 'To Register'\n"
	  "-- 'NEW_MAC_TIME_MSB'\nsm_NEW_MAC_TIME_MSB_din     <= sm_NEW_MAC_TIME_MSB_din_i(32-1 downto 0);\nsm_NEW_MAC_TIME_MS"
	  "B_en      <= sm_NEW_MAC_TIME_MSB_en_i;\ngen_sm_NEW_MAC_TIME_MSB_dout_i: if (32 < C_S_AXI_DATA_WIDTH) generate\n    "
	  "sm_NEW_MAC_TIME_MSB_dout_i(C_S_AXI_DATA_WIDTH-1 downto 32) <= (others => '0');\nend generate gen_sm_NEW_MAC_TIME_MS"
	  "B_dout_i;\nsm_NEW_MAC_TIME_MSB_dout_i(32-1 downto 0) <= sm_NEW_MAC_TIME_MSB_dout;\n-- 'NEW_MAC_TIME_LSB'\nsm_NEW_MA"
	  "C_TIME_LSB_din     <= sm_NEW_MAC_TIME_LSB_din_i(32-1 downto 0);\nsm_NEW_MAC_TIME_LSB_en      <= sm_NEW_MAC_TIME_LSB"
	  "_en_i;\ngen_sm_NEW_MAC_TIME_LSB_dout_i: if (32 < C_S_AXI_DATA_WIDTH) generate\n    sm_NEW_MAC_TIME_LSB_dout_i(C_S_A"
	  "XI_DATA_WIDTH-1 downto 32) <= (others => '0');\nend generate gen_sm_NEW_MAC_TIME_LSB_dout_i;\nsm_NEW_MAC_TIME_LSB_d"
	  "out_i(32-1 downto 0) <= sm_NEW_MAC_TIME_LSB_dout;\n-- 'Control'\nsm_Control_din     <= sm_Control_din_i(32-1 downto"
	  " 0);\nsm_Control_en      <= sm_Control_en_i;\ngen_sm_Control_dout_i: if (32 < C_S_AXI_DATA_WIDTH) generate\n    sm_"
	  "Control_dout_i(C_S_AXI_DATA_WIDTH-1 downto 32) <= (others => '0');\nend generate gen_sm_Control_dout_i;\nsm_Control"
	  "_dout_i(32-1 downto 0) <= sm_Control_dout;\n-- 'From FIFO'\n-- 'To FIFO'\n-- 'Shared Memory'\n\nReadWriteSelect: pr"
	  "ocess(memmap_state) is begin\n    if (memmap_state = READ) then\n    else\n    end if;\nend process ReadWriteSelect"
	  ";\n\n-----------------------------------------------------------------------------\n-- address for 'Shared Memory'\n"
	  "-----------------------------------------------------------------------------\nSharedMemory_Addr_ResetN : process(A"
	  "XI_AClk) is begin\n    if (AXI_AClk'event and AXI_AClk = '1') then\n        if (AXI_AResetN = '0') then\n          "
	  "  memmap_state <= READ;\n        else\n            if (S_AXI_AWVALID = '1') then\n                -- write operatio"
	  "n\n                memmap_state <= WRITE;\n            elsif (S_AXI_ARVALID = '1') then\n                -- read op"
	  "eration\n                memmap_state <= READ;\n            end if;\n        end if;\n    end if;\nend process Shar"
	  "edMemory_Addr_ResetN;\n\n-----------------------------------------------------------------------------\n-- WRITE Co"
	  "mmand Control\n-----------------------------------------------------------------------------\nS_AXI_BID     <= S_AX"
	  "I_BID_i;\nS_AXI_BVALID  <= S_AXI_BVALID_i;\nS_AXI_WREADY  <= S_AXI_WREADY_i;\n-- No error checking\nS_AXI_BRESP  <="
	  " (others=>'0');\n\nPROC_AWREADY_ACK: process(read_state, write_state, S_AXI_ARVALID, S_AXI_AWVALID) is begin\n    i"
	  "f (write_state = IDLE and S_AXI_AWVALID = '1' and read_state = IDLE) then\n        S_AXI_AWREADY <= S_AXI_AWVALID;\n"
	  "    else\n        S_AXI_AWREADY <= '0';\n    end if;\nend process PROC_AWREADY_ACK;\n\nCmd_Decode_Write: process(AX"
	  "I_AClk) is begin\n    if (AXI_AClk'event and AXI_AClk = '1') then\n        if (AXI_AResetN = '0') then\n           "
	  " write_addr_valid    <= '0';\n            write_ready         <= '0';\n            s_fifo_we           <= '0';\n   "
	  "         S_AXI_BVALID_i      <= '0';\n            S_AXI_BID_i         <= (others => '0');\n            write_bank_a"
	  "ddr_i   <= (others => '0');\n            write_linear_addr_i <= (others => '0');\n        else\n            if (wri"
	  "te_state = IDLE) then\n                if (S_AXI_AWVALID = '1' and read_state = IDLE) then\n                    -- "
	  "reflect awid\n                    S_AXI_BID_i <= S_AXI_AWID;\n\n                    -- latch bank and linear addres"
	  "ses\n                    write_bank_addr_i   <= S_AXI_AWADDR(C_S_AXI_TOTAL_ADDR_LEN-1 downto C_S_AXI_LINEAR_ADDR_LE"
	  "N+2);\n                    write_linear_addr_i <= S_AXI_AWADDR(C_S_AXI_LINEAR_ADDR_LEN+1 downto 2);\n              "
	  "      write_addr_valid <= '1';\n                    s_fifo_we <= '1';\n\n                    -- write state transit"
	  "ion\n                    write_state <= WRITE_DATA;\n                end if;\n            elsif (write_state = WRIT"
	  "E_DATA) then\n                write_ready <= '1';\n                s_fifo_we <= '0';\n                write_addr_va"
	  "lid <= S_AXI_WVALID;\n                \n                if (S_AXI_WVALID = '1' and write_ready = '1') then\n       "
	  "             write_linear_addr_i <= Std_Logic_Vector(unsigned(write_linear_addr_i) + 1);\n                end if;\n"
	  "\n                if (S_AXI_WLAST = '1' and write_ready = '1') then\n                    -- start responding throug"
	  "h B channel upon the last write data sample\n                    S_AXI_BVALID_i <= '1';\n                    -- wri"
	  "te data is over\n                    write_addr_valid <= '0';\n                    write_ready <= '0';\n           "
	  "         -- write state transition\n                    write_state <= WRITE_RESPONSE;\n                end if;\n  "
	  "          elsif (write_state = WRITE_RESPONSE) then\n\n                if (S_AXI_BREADY = '1') then\n              "
	  "      -- write respond is over\n                    S_AXI_BVALID_i <= '0';\n                    S_AXI_BID_i <= (oth"
	  "ers => '0');\n\n                    -- write state transition\n                    write_state <= IDLE;\n          "
	  "      end if;\n            end if;\n        end if;\n    end if;\nend process Cmd_Decode_Write;\n\nWrite_Linear_Add"
	  "r_Decode : process(AXI_AClk) is \n\nbegin\n    if (AXI_AClk'event and AXI_AClk = '1') then\n        if (AXI_AResetN"
	  " = '0') then\n            -- 'To Register'\n            -- NEW_MAC_TIME_MSB din/en\n            sm_NEW_MAC_TIME_MSB"
	  "_din_i <= (others => '0');\n            sm_NEW_MAC_TIME_MSB_en_i <= '0';\n            -- NEW_MAC_TIME_LSB din/en\n "
	  "           sm_NEW_MAC_TIME_LSB_din_i <= (others => '0');\n            sm_NEW_MAC_TIME_LSB_en_i <= '0';\n           "
	  " -- Control din/en\n            sm_Control_din_i <= (others => '0');\n            sm_Control_en_i <= '0';\n        "
	  "    -- 'To FIFO'\n            -- 'Shared Memory'\n        else\n            -- default assignments\n\n            -"
	  "- 'To Register'\n            if (unsigned(write_bank_addr_i) = 2) then\n                if (unsigned(write_linear_a"
	  "ddr_i) = 0) then\n                    -- NEW_MAC_TIME_MSB din/en\n                    sm_NEW_MAC_TIME_MSB_din_i <= "
	  "S_AXI_WDATA;\n                    sm_NEW_MAC_TIME_MSB_en_i  <= write_addr_valid;\n                elsif (unsigned(w"
	  "rite_linear_addr_i) = 1) then\n                    -- NEW_MAC_TIME_LSB din/en\n                    sm_NEW_MAC_TIME_"
	  "LSB_din_i <= S_AXI_WDATA;\n                    sm_NEW_MAC_TIME_LSB_en_i  <= write_addr_valid;\n                elsi"
	  "f (unsigned(write_linear_addr_i) = 2) then\n                    -- Control din/en\n                    sm_Control_d"
	  "in_i <= S_AXI_WDATA;\n                    sm_Control_en_i  <= write_addr_valid;\n                end if;\n         "
	  "   end if;        \n        \n        \n        end if;\n    end if;\nend process Write_Linear_Addr_Decode;\n \n---"
	  "--------------------------------------------------------------------------\n-- READ Control\n----------------------"
	  "-------------------------------------------------------\n\nS_AXI_RDATA  <= S_AXI_RDATA_i;\nS_AXI_RVALID  <= S_AXI_R"
	  "VALID_i;\nS_AXI_RLAST   <= S_AXI_RLAST_i;\nS_AXI_RID     <= S_AXI_RID_i;\n-- TODO: no error checking\nS_AXI_RRESP <"
	  "= (others=>'0');\n\nPROC_ARREADY_ACK: process(read_state, S_AXI_ARVALID, write_state, S_AXI_AWVALID) is begin\n    "
	  "-- Note: WRITE has higher priority than READ\n    if (read_state = IDLE and S_AXI_ARVALID = '1' and write_state = I"
	  "DLE and S_AXI_AWVALID /= '1') then\n        S_AXI_ARREADY <= S_AXI_ARVALID;\n    else\n        S_AXI_ARREADY <= '0'"
	  ";\n    end if;\nend process PROC_ARREADY_ACK;\n\nS_AXI_WREADY_i <= write_ready;\n\nProcess_Sideband: process(write_"
	  "state, read_state) is begin\n    if (read_state = READ_PREP) then\n        s_shram_en <= '1';\n    elsif (read_stat"
	  "e = READ_DATA) then\n        s_shram_en <= S_AXI_RREADY;\n    elsif (write_state = WRITE_DATA) then\n        s_shra"
	  "m_en <= S_AXI_WVALID;\n    else\n        s_shram_en <= '0';\n    end if;\nend process Process_Sideband;\n\nCmd_Deco"
	  "de_Read: process(AXI_AClk) is begin\n    if (AXI_AClk'event and AXI_AClk = '1') then\n        if (AXI_AResetN = '0'"
	  ") then\n            S_AXI_RVALID_i <= '0';\n            read_bank_addr_i    <= (others => '0');\n            read_l"
	  "inear_addr_i  <= (others => '0');\n            S_AXI_ARLEN_i       <= (others => '0');\n            S_AXI_RLAST_i  "
	  "     <= '0';\n            S_AXI_RID_i         <= (others => '0');\n            read_state          <= IDLE;\n      "
	  "      read_prep_counter   <= (others => '0');\n            read_addr_counter   <= (others => '0');\n            rea"
	  "d_data_counter   <= (others => '0');\n        else\n            -- default assignments\n            s_fifo_re <= '0"
	  "';\n\n            if (read_state = IDLE) then\n                -- Note WRITE has higher priority than READ\n       "
	  "         if (S_AXI_ARVALID = '1' and write_state = IDLE and S_AXI_AWVALID /= '1') then\n                    -- extr"
	  "act bank and linear addresses\n                    read_bank_addr_i    <= S_AXI_ARADDR(C_S_AXI_TOTAL_ADDR_LEN-1 dow"
	  "nto C_S_AXI_LINEAR_ADDR_LEN+2);\n                    read_linear_addr_i  <= S_AXI_ARADDR(C_S_AXI_LINEAR_ADDR_LEN+1 "
	  "downto 2);\n                    s_fifo_re <= '1';\n\n                    -- reflect arid\n                    S_AXI"
	  "_RID_i <= S_AXI_ARID;\n\n                    -- load read liner address and data counter\n                    read_"
	  "addr_counter <= S_AXI_ARLEN;\n                    read_data_counter <= S_AXI_ARLEN;\n\n                    -- load "
	  "read preparation counter\n                    read_prep_counter <= C_READ_PREP_DELAY;\n                    -- read "
	  "state transition\n                    read_state <= READ_PREP;\n                end if;\n            elsif (read_st"
	  "ate = READ_PREP) then\n                if (unsigned(read_prep_counter) = 0) then\n                    if (unsigned("
	  "read_data_counter) = 0) then\n                        -- tag the last data generated by the slave\n                "
	  "        S_AXI_RLAST_i <= '1';\n                    end if;\n                    -- valid data appears\n            "
	  "        S_AXI_RVALID_i <= '1';\n                    -- read state transition\n                    read_state <= REA"
	  "D_DATA;\n                else\n                    -- decrease read preparation counter\n                    read_p"
	  "rep_counter <= Std_Logic_Vector(unsigned(read_prep_counter) - 1);\n                end if;\n\n                if (u"
	  "nsigned(read_prep_counter) /= 3 and unsigned(read_addr_counter) /= 0) then\n                    -- decrease address"
	  " counter\n                    read_addr_counter <= Std_Logic_Vector(unsigned(read_addr_counter) - 1);\n            "
	  "        -- increase linear address (no band crossing)\n                    read_linear_addr_i <= Std_Logic_Vector(u"
	  "nsigned(read_linear_addr_i) + 1);\n                end if;\n            elsif (read_state = READ_DATA) then\n      "
	  "          if (S_AXI_RREADY = '1') then\n                    if (unsigned(read_data_counter) = 1) then\n            "
	  "            -- tag the last data generated by the slave\n                        S_AXI_RLAST_i <= '1';\n           "
	  "         end if;\n\n                    if (unsigned(read_data_counter) = 0) then\n                        -- arid\n"
	  "                        S_AXI_RID_i <= (others => '0');\n                        -- rlast\n                        "
	  "S_AXI_RLAST_i <= '0';\n                        -- no more valid data\n                        S_AXI_RVALID_i <= '0'"
	  ";\n                        -- read state transition\n                        read_state <= IDLE;\n                 "
	  "   else\n                        -- decrease read preparation counter\n                        read_data_counter <="
	  " Std_Logic_Vector(unsigned(read_data_counter) - 1);\n\n                        if (unsigned(read_addr_counter) /= 0"
	  ") then\n                            -- decrease address counter\n                            read_addr_counter <= S"
	  "td_Logic_Vector(unsigned(read_addr_counter) - 1);\n                            -- increase linear address (no band "
	  "crossing)\n                            read_linear_addr_i <= Std_Logic_Vector(unsigned(read_linear_addr_i) + 1);\n "
	  "                       end if;\n                    end if;\n                end if;\n            end if;\n\n      "
	  "  end if;\n    end if;\nend process Cmd_Decode_Read;\n\nRead_Linear_Addr_Decode : process(AXI_AClk) is begin\n    i"
	  "f (AXI_AClk'event and AXI_AClk = '1') then\n        if (AXI_AResetN = '0') then\n            reg_bank_out_i   <= (o"
	  "thers => '0');\n            fifo_bank_out_i  <= (others => '0');\n            shmem_bank_out_i <= (others => '0');\n"
	  "            S_AXI_RDATA_i    <= (others => '0');\n        else\n            if (unsigned(read_bank_addr_i) = 2) the"
	  "n\n                -- 'From Register'\n                if (unsigned(read_linear_addr_i) = 3) then\n                "
	  "    -- 'SYSTEM_TIME_USEC_MSB' dout\n                    reg_bank_out_i <= sm_SYSTEM_TIME_USEC_MSB_dout_i;\n        "
	  "        elsif (unsigned(read_linear_addr_i) = 4) then\n                    -- 'SYSTEM_TIME_USEC_LSB' dout\n        "
	  "            reg_bank_out_i <= sm_SYSTEM_TIME_USEC_LSB_dout_i;\n                elsif (unsigned(read_linear_addr_i) "
	  "= 5) then\n                    -- 'MAC_TIME_USEC_MSB' dout\n                    reg_bank_out_i <= sm_MAC_TIME_USEC_"
	  "MSB_dout_i;\n                elsif (unsigned(read_linear_addr_i) = 6) then\n                    -- 'MAC_TIME_USEC_L"
	  "SB' dout\n                    reg_bank_out_i <= sm_MAC_TIME_USEC_LSB_dout_i;\n                end if;\n            "
	  "    -- 'To Register' (with register readback)\n                if (unsigned(read_linear_addr_i) = 0) then\n        "
	  "            -- 'NEW_MAC_TIME_MSB' dout\n                    reg_bank_out_i <= sm_NEW_MAC_TIME_MSB_dout_i;\n        "
	  "        elsif (unsigned(read_linear_addr_i) = 1) then\n                    -- 'NEW_MAC_TIME_LSB' dout\n            "
	  "        reg_bank_out_i <= sm_NEW_MAC_TIME_LSB_dout_i;\n                elsif (unsigned(read_linear_addr_i) = 2) the"
	  "n\n                    -- 'Control' dout\n                    reg_bank_out_i <= sm_Control_dout_i;\n               "
	  " end if;\n\n                S_AXI_RDATA_i <= reg_bank_out_i;\n            elsif (unsigned(read_bank_addr_i) = 1) th"
	  "en\n                -- 'From FIFO'\n                -- 'To FIFO'\n\n                S_AXI_RDATA_i <= fifo_bank_out_"
	  "i;\n            elsif (unsigned(read_bank_addr_i) = 0 and s_shram_en = '1') then\n                -- 'Shared Memory"
	  "'\n\n                S_AXI_RDATA_i <= shmem_bank_out_i;\n            end if;\n        end if;\n    end if;\nend pro"
	  "cess Read_Linear_Addr_Decode;\n\nend architecture IMP;\n"
	  config		  "{'inports'=>[{'arith_type'=>2.00000000000000000,'bin_pt'=>0.00000000000000000,'name'=>'AXI_ARESETN','wid"
	  "th'=>0},{'arith_type'=>2.00000000000000000,'bin_pt'=>0.00000000000000000,'name'=>'S_AXI_ARADDR','width'=>32},{'arit"
	  "h_type'=>2.00000000000000000,'bin_pt'=>0.00000000000000000,'name'=>'S_AXI_ARBURST','width'=>2},{'arith_type'=>2.000"
	  "00000000000000,'bin_pt'=>0.00000000000000000,'name'=>'S_AXI_ARCACHE','width'=>4},{'arith_type'=>2.00000000000000000"
	  ",'bin_pt'=>0.00000000000000000,'name'=>'S_AXI_ARID','width'=>8},{'arith_type'=>2.00000000000000000,'bin_pt'=>0.0000"
	  "0000000000000,'name'=>'S_AXI_ARLEN','width'=>8},{'arith_type'=>2.00000000000000000,'bin_pt'=>0.00000000000000000,'n"
	  "ame'=>'S_AXI_ARLOCK','width'=>2},{'arith_type'=>2.00000000000000000,'bin_pt'=>0.00000000000000000,'name'=>'S_AXI_AR"
	  "PROT','width'=>3},{'arith_type'=>2.00000000000000000,'bin_pt'=>0.00000000000000000,'name'=>'S_AXI_ARSIZE','width'=>"
	  "3},{'arith_type'=>2.00000000000000000,'bin_pt'=>0.00000000000000000,'name'=>'S_AXI_ARVALID','width'=>0},{'arith_typ"
	  "e'=>2.00000000000000000,'bin_pt'=>0.00000000000000000,'name'=>'S_AXI_AWADDR','width'=>32},{'arith_type'=>2.00000000"
	  "000000000,'bin_pt'=>0.00000000000000000,'name'=>'S_AXI_AWBURST','width'=>2},{'arith_type'=>2.00000000000000000,'bin"
	  "_pt'=>0.00000000000000000,'name'=>'S_AXI_AWCACHE','width'=>4},{'arith_type'=>2.00000000000000000,'bin_pt'=>0.000000"
	  "00000000000,'name'=>'S_AXI_AWID','width'=>8},{'arith_type'=>2.00000000000000000,'bin_pt'=>0.00000000000000000,'name"
	  "'=>'S_AXI_AWLEN','width'=>8},{'arith_type'=>2.00000000000000000,'bin_pt'=>0.00000000000000000,'name'=>'S_AXI_AWLOCK"
	  "','width'=>2},{'arith_type'=>2.00000000000000000,'bin_pt'=>0.00000000000000000,'name'=>'S_AXI_AWPROT','width'=>3},{"
	  "'arith_type'=>2.00000000000000000,'bin_pt'=>0.00000000000000000,'name'=>'S_AXI_AWSIZE','width'=>3},{'arith_type'=>2"
	  ".00000000000000000,'bin_pt'=>0.00000000000000000,'name'=>'S_AXI_AWVALID','width'=>0},{'arith_type'=>2.0000000000000"
	  "0000,'bin_pt'=>0.00000000000000000,'name'=>'S_AXI_BREADY','width'=>0},{'arith_type'=>2.00000000000000000,'bin_pt'=>"
	  "0.00000000000000000,'name'=>'S_AXI_RREADY','width'=>0},{'arith_type'=>2.00000000000000000,'bin_pt'=>0.0000000000000"
	  "0000,'name'=>'S_AXI_WDATA','width'=>32},{'arith_type'=>2.00000000000000000,'bin_pt'=>0.00000000000000000,'name'=>'S"
	  "_AXI_WLAST','width'=>0},{'arith_type'=>2.00000000000000000,'bin_pt'=>0.00000000000000000,'name'=>'S_AXI_WSTRB','wid"
	  "th'=>4},{'arith_type'=>2.00000000000000000,'bin_pt'=>0.00000000000000000,'name'=>'S_AXI_WVALID','width'=>0},{'arith"
	  "_type'=>2,'bin_pt'=>0,'name'=>'sm_SYSTEM_TIME_USEC_MSB_dout','width'=>32},{'arith_type'=>2,'bin_pt'=>0,'name'=>'sm_"
	  "SYSTEM_TIME_USEC_LSB_dout','width'=>32},{'arith_type'=>2,'bin_pt'=>0,'name'=>'sm_MAC_TIME_USEC_MSB_dout','width'=>3"
	  "2},{'arith_type'=>2,'bin_pt'=>0,'name'=>'sm_MAC_TIME_USEC_LSB_dout','width'=>32},{'arith_type'=>2,'bin_pt'=>0,'name"
	  "'=>'sm_NEW_MAC_TIME_MSB_dout','width'=>32},{'arith_type'=>2,'bin_pt'=>0,'name'=>'sm_NEW_MAC_TIME_LSB_dout','width'="
	  ">32},{'arith_type'=>2,'bin_pt'=>0,'name'=>'sm_Control_dout','width'=>32}],'outports'=>[{'arith_type'=>2.00000000000"
	  "000000,'bin_pt'=>0.00000000000000000,'name'=>'S_AXI_ARREADY','width'=>0},{'arith_type'=>2.00000000000000000,'bin_pt"
	  "'=>0.00000000000000000,'name'=>'S_AXI_AWREADY','width'=>0},{'arith_type'=>2.00000000000000000,'bin_pt'=>0.000000000"
	  "00000000,'name'=>'S_AXI_BID','width'=>8},{'arith_type'=>2.00000000000000000,'bin_pt'=>0.00000000000000000,'name'=>'"
	  "S_AXI_BRESP','width'=>2},{'arith_type'=>2.00000000000000000,'bin_pt'=>0.00000000000000000,'name'=>'S_AXI_BVALID','w"
	  "idth'=>0},{'arith_type'=>2.00000000000000000,'bin_pt'=>0.00000000000000000,'name'=>'S_AXI_RDATA','width'=>32},{'ari"
	  "th_type'=>2.00000000000000000,'bin_pt'=>0.00000000000000000,'name'=>'S_AXI_RID','width'=>8},{'arith_type'=>2.000000"
	  "00000000000,'bin_pt'=>0.00000000000000000,'name'=>'S_AXI_RLAST','width'=>0},{'arith_type'=>2.00000000000000000,'bin"
	  "_pt'=>0.00000000000000000,'name'=>'S_AXI_RRESP','width'=>2},{'arith_type'=>2.00000000000000000,'bin_pt'=>0.00000000"
	  "000000000,'name'=>'S_AXI_RVALID','width'=>0},{'arith_type'=>2.00000000000000000,'bin_pt'=>0.00000000000000000,'name"
	  "'=>'S_AXI_WREADY','width'=>0},{'arith_type'=>2,'bin_pt'=>0,'name'=>'sm_NEW_MAC_TIME_MSB_din','width'=>32},{'arith_t"
	  "ype'=>2.00000000000000000,'bin_pt'=>0.00000000000000000,'name'=>'sm_NEW_MAC_TIME_MSB_en','width'=>0.000000000000000"
	  "00},{'arith_type'=>2,'bin_pt'=>0,'name'=>'sm_NEW_MAC_TIME_LSB_din','width'=>32},{'arith_type'=>2.00000000000000000,"
	  "'bin_pt'=>0.00000000000000000,'name'=>'sm_NEW_MAC_TIME_LSB_en','width'=>0.00000000000000000},{'arith_type'=>2,'bin_"
	  "pt'=>0,'name'=>'sm_Control_din','width'=>32},{'arith_type'=>2.00000000000000000,'bin_pt'=>0.00000000000000000,'name"
	  "'=>'sm_Control_en','width'=>0.00000000000000000}]}"
	  inheritDeviceType	  "inheritDeviceType"
	  has_advanced_control	  "0"
	  sggui_pos		  "-1,-1,-1,-1"
	  block_type		  "edkcore"
	  sg_icon_stat		  "250,966,32,17,white,blue,0,14f99c6e,right,,[ ],[ ]"
	  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 250 250 0 0 ],[0 0 966 966 0 ],[0.77 0.82 "
	  "0.91 ]);\nplot([0 250 250 0 0 ],[0 0 966 966 0 ]);\npatch([47.125 97.7 132.7 167.7 202.7 132.7 82.125 47.125 ],[521"
	  ".85 521.85 556.85 521.85 556.85 556.85 556.85 521.85 ],[1 1 1 ]);\npatch([82.125 132.7 97.7 47.125 82.125 ],[486.85"
	  " 486.85 521.85 521.85 486.85 ],[0.931 0.946 0.973 ]);\npatch([47.125 97.7 132.7 82.125 47.125 ],[451.85 451.85 486."
	  "85 486.85 451.85 ],[1 1 1 ]);\npatch([82.125 202.7 167.7 132.7 97.7 47.125 82.125 ],[416.85 416.85 451.85 416.85 45"
	  "1.85 451.85 416.85 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin "
	  "icon text');\ncolor('black');port_label('input',1,'AXI_ARESETN');\ncolor('black');port_label('input',2,'S_AXI_ARADD"
	  "R');\ncolor('black');port_label('input',3,'S_AXI_ARBURST');\ncolor('black');port_label('input',4,'S_AXI_ARCACHE');\n"
	  "color('black');port_label('input',5,'S_AXI_ARID');\ncolor('black');port_label('input',6,'S_AXI_ARLEN');\ncolor('bla"
	  "ck');port_label('input',7,'S_AXI_ARLOCK');\ncolor('black');port_label('input',8,'S_AXI_ARPROT');\ncolor('black');po"
	  "rt_label('input',9,'S_AXI_ARSIZE');\ncolor('black');port_label('input',10,'S_AXI_ARVALID');\ncolor('black');port_la"
	  "bel('input',11,'S_AXI_AWADDR');\ncolor('black');port_label('input',12,'S_AXI_AWBURST');\ncolor('black');port_label("
	  "'input',13,'S_AXI_AWCACHE');\ncolor('black');port_label('input',14,'S_AXI_AWID');\ncolor('black');port_label('input"
	  "',15,'S_AXI_AWLEN');\ncolor('black');port_label('input',16,'S_AXI_AWLOCK');\ncolor('black');port_label('input',17,'"
	  "S_AXI_AWPROT');\ncolor('black');port_label('input',18,'S_AXI_AWSIZE');\ncolor('black');port_label('input',19,'S_AXI"
	  "_AWVALID');\ncolor('black');port_label('input',20,'S_AXI_BREADY');\ncolor('black');port_label('input',21,'S_AXI_RRE"
	  "ADY');\ncolor('black');port_label('input',22,'S_AXI_WDATA');\ncolor('black');port_label('input',23,'S_AXI_WLAST');\n"
	  "color('black');port_label('input',24,'S_AXI_WSTRB');\ncolor('black');port_label('input',25,'S_AXI_WVALID');\ncolor("
	  "'black');port_label('input',26,'sm_SYSTEM_TIME_USEC_MSB_dout');\ncolor('black');port_label('input',27,'sm_SYSTEM_TI"
	  "ME_USEC_LSB_dout');\ncolor('black');port_label('input',28,'sm_MAC_TIME_USEC_MSB_dout');\ncolor('black');port_label("
	  "'input',29,'sm_MAC_TIME_USEC_LSB_dout');\ncolor('black');port_label('input',30,'sm_NEW_MAC_TIME_MSB_dout');\ncolor("
	  "'black');port_label('input',31,'sm_NEW_MAC_TIME_LSB_dout');\ncolor('black');port_label('input',32,'sm_Control_dout'"
	  ");\ncolor('black');port_label('output',1,'S_AXI_ARREADY');\ncolor('black');port_label('output',2,'S_AXI_AWREADY');\n"
	  "color('black');port_label('output',3,'S_AXI_BID');\ncolor('black');port_label('output',4,'S_AXI_BRESP');\ncolor('bl"
	  "ack');port_label('output',5,'S_AXI_BVALID');\ncolor('black');port_label('output',6,'S_AXI_RDATA');\ncolor('black');"
	  "port_label('output',7,'S_AXI_RID');\ncolor('black');port_label('output',8,'S_AXI_RLAST');\ncolor('black');port_labe"
	  "l('output',9,'S_AXI_RRESP');\ncolor('black');port_label('output',10,'S_AXI_RVALID');\ncolor('black');port_label('ou"
	  "tput',11,'S_AXI_WREADY');\ncolor('black');port_label('output',12,'sm_NEW_MAC_TIME_MSB_din');\ncolor('black');port_l"
	  "abel('output',13,'sm_NEW_MAC_TIME_MSB_en');\ncolor('black');port_label('output',14,'sm_NEW_MAC_TIME_LSB_din');\ncol"
	  "or('black');port_label('output',15,'sm_NEW_MAC_TIME_LSB_en');\ncolor('black');port_label('output',16,'sm_Control_di"
	  "n');\ncolor('black');port_label('output',17,'sm_Control_en');\nfprintf('','COMMENT: end icon text');"
	}
	Line {
	  SrcBlock		  "memmap"
	  SrcPort		  13
	  DstBlock		  "To Register"
	  DstPort		  2
	}
	Line {
	  SrcBlock		  "memmap"
	  SrcPort		  12
	  DstBlock		  "To Register"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "memmap"
	  SrcPort		  15
	  DstBlock		  "To Register1"
	  DstPort		  2
	}
	Line {
	  SrcBlock		  "memmap"
	  SrcPort		  14
	  DstBlock		  "To Register1"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "memmap"
	  SrcPort		  17
	  DstBlock		  "To Register2"
	  DstPort		  2
	}
	Line {
	  SrcBlock		  "memmap"
	  SrcPort		  16
	  DstBlock		  "To Register2"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "memmap"
	  SrcPort		  11
	  DstBlock		  "S_AXI_WREADY"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "memmap"
	  SrcPort		  10
	  DstBlock		  "S_AXI_RVALID"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "memmap"
	  SrcPort		  9
	  DstBlock		  "S_AXI_RRESP"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "memmap"
	  SrcPort		  8
	  DstBlock		  "S_AXI_RLAST"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "memmap"
	  SrcPort		  7
	  DstBlock		  "S_AXI_RID"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "memmap"
	  SrcPort		  6
	  DstBlock		  "S_AXI_RDATA"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "memmap"
	  SrcPort		  5
	  DstBlock		  "S_AXI_BVALID"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "memmap"
	  SrcPort		  4
	  DstBlock		  "S_AXI_BRESP"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "memmap"
	  SrcPort		  3
	  DstBlock		  "S_AXI_BID"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "memmap"
	  SrcPort		  2
	  DstBlock		  "S_AXI_AWREADY"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "memmap"
	  SrcPort		  1
	  DstBlock		  "S_AXI_ARREADY"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "S_AXI_WVALID"
	  SrcPort		  1
	  DstBlock		  "memmap"
	  DstPort		  25
	}
	Line {
	  SrcBlock		  "S_AXI_WSTRB"
	  SrcPort		  1
	  DstBlock		  "memmap"
	  DstPort		  24
	}
	Line {
	  SrcBlock		  "S_AXI_WLAST"
	  SrcPort		  1
	  DstBlock		  "memmap"
	  DstPort		  23
	}
	Line {
	  SrcBlock		  "S_AXI_WDATA"
	  SrcPort		  1
	  DstBlock		  "memmap"
	  DstPort		  22
	}
	Line {
	  SrcBlock		  "S_AXI_RREADY"
	  SrcPort		  1
	  DstBlock		  "memmap"
	  DstPort		  21
	}
	Line {
	  SrcBlock		  "S_AXI_BREADY"
	  SrcPort		  1
	  DstBlock		  "memmap"
	  DstPort		  20
	}
	Line {
	  SrcBlock		  "S_AXI_AWVALID"
	  SrcPort		  1
	  DstBlock		  "memmap"
	  DstPort		  19
	}
	Line {
	  SrcBlock		  "S_AXI_AWSIZE"
	  SrcPort		  1
	  DstBlock		  "memmap"
	  DstPort		  18
	}
	Line {
	  SrcBlock		  "S_AXI_AWPROT"
	  SrcPort		  1
	  DstBlock		  "memmap"
	  DstPort		  17
	}
	Line {
	  SrcBlock		  "S_AXI_AWLOCK"
	  SrcPort		  1
	  DstBlock		  "memmap"
	  DstPort		  16
	}
	Line {
	  SrcBlock		  "S_AXI_AWLEN"
	  SrcPort		  1
	  DstBlock		  "memmap"
	  DstPort		  15
	}
	Line {
	  SrcBlock		  "S_AXI_AWID"
	  SrcPort		  1
	  DstBlock		  "memmap"
	  DstPort		  14
	}
	Line {
	  SrcBlock		  "S_AXI_AWCACHE"
	  SrcPort		  1
	  DstBlock		  "memmap"
	  DstPort		  13
	}
	Line {
	  SrcBlock		  "S_AXI_AWBURST"
	  SrcPort		  1
	  DstBlock		  "memmap"
	  DstPort		  12
	}
	Line {
	  SrcBlock		  "S_AXI_AWADDR"
	  SrcPort		  1
	  DstBlock		  "memmap"
	  DstPort		  11
	}
	Line {
	  SrcBlock		  "S_AXI_ARVALID"
	  SrcPort		  1
	  DstBlock		  "memmap"
	  DstPort		  10
	}
	Line {
	  SrcBlock		  "S_AXI_ARSIZE"
	  SrcPort		  1
	  DstBlock		  "memmap"
	  DstPort		  9
	}
	Line {
	  SrcBlock		  "S_AXI_ARPROT"
	  SrcPort		  1
	  DstBlock		  "memmap"
	  DstPort		  8
	}
	Line {
	  SrcBlock		  "S_AXI_ARLOCK"
	  SrcPort		  1
	  DstBlock		  "memmap"
	  DstPort		  7
	}
	Line {
	  SrcBlock		  "S_AXI_ARLEN"
	  SrcPort		  1
	  DstBlock		  "memmap"
	  DstPort		  6
	}
	Line {
	  SrcBlock		  "S_AXI_ARID"
	  SrcPort		  1
	  DstBlock		  "memmap"
	  DstPort		  5
	}
	Line {
	  SrcBlock		  "S_AXI_ARCACHE"
	  SrcPort		  1
	  DstBlock		  "memmap"
	  DstPort		  4
	}
	Line {
	  SrcBlock		  "S_AXI_ARBURST"
	  SrcPort		  1
	  DstBlock		  "memmap"
	  DstPort		  3
	}
	Line {
	  SrcBlock		  "S_AXI_ARADDR"
	  SrcPort		  1
	  DstBlock		  "memmap"
	  DstPort		  2
	}
	Line {
	  SrcBlock		  "AXI_ARESETN"
	  SrcPort		  1
	  DstBlock		  "memmap"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "From Register"
	  SrcPort		  1
	  DstBlock		  "memmap"
	  DstPort		  26
	}
	Line {
	  SrcBlock		  "From Register1"
	  SrcPort		  1
	  DstBlock		  "memmap"
	  DstPort		  27
	}
	Line {
	  SrcBlock		  "To Register"
	  SrcPort		  1
	  DstBlock		  "memmap"
	  DstPort		  30
	}
	Line {
	  SrcBlock		  "To Register1"
	  SrcPort		  1
	  DstBlock		  "memmap"
	  DstPort		  31
	}
	Line {
	  SrcBlock		  "From Register2"
	  SrcPort		  1
	  DstBlock		  "memmap"
	  DstPort		  28
	}
	Line {
	  SrcBlock		  "From Register3"
	  SrcPort		  1
	  DstBlock		  "memmap"
	  DstPort		  29
	}
	Line {
	  SrcBlock		  "To Register2"
	  SrcPort		  1
	  DstBlock		  "memmap"
	  DstPort		  32
	}
	Line {
	  SrcBlock		  "S_AXI_WREADY"
	  SrcPort		  1
	  DstBlock		  "Terminator10"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "S_AXI_RVALID"
	  SrcPort		  1
	  DstBlock		  "Terminator9"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "S_AXI_RRESP"
	  SrcPort		  1
	  DstBlock		  "Terminator8"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "S_AXI_RLAST"
	  SrcPort		  1
	  DstBlock		  "Terminator7"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "S_AXI_RID"
	  SrcPort		  1
	  DstBlock		  "Terminator6"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "S_AXI_RDATA"
	  SrcPort		  1
	  DstBlock		  "Terminator5"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "S_AXI_BVALID"
	  SrcPort		  1
	  DstBlock		  "Terminator4"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "S_AXI_BRESP"
	  SrcPort		  1
	  DstBlock		  "Terminator3"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "S_AXI_BID"
	  SrcPort		  1
	  DstBlock		  "Terminator2"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "S_AXI_AWREADY"
	  SrcPort		  1
	  DstBlock		  "Terminator1"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "S_AXI_ARREADY"
	  SrcPort		  1
	  DstBlock		  "Terminator"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "Constant24"
	  SrcPort		  1
	  DstBlock		  "S_AXI_WVALID"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "Constant23"
	  SrcPort		  1
	  DstBlock		  "S_AXI_WSTRB"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "Constant22"
	  SrcPort		  1
	  DstBlock		  "S_AXI_WLAST"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "Constant21"
	  SrcPort		  1
	  DstBlock		  "S_AXI_WDATA"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "Constant20"
	  SrcPort		  1
	  DstBlock		  "S_AXI_RREADY"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "Constant19"
	  SrcPort		  1
	  DstBlock		  "S_AXI_BREADY"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "Constant18"
	  SrcPort		  1
	  DstBlock		  "S_AXI_AWVALID"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "Constant17"
	  SrcPort		  1
	  DstBlock		  "S_AXI_AWSIZE"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "Constant16"
	  SrcPort		  1
	  DstBlock		  "S_AXI_AWPROT"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "Constant15"
	  SrcPort		  1
	  DstBlock		  "S_AXI_AWLOCK"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "Constant14"
	  SrcPort		  1
	  DstBlock		  "S_AXI_AWLEN"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "Constant13"
	  SrcPort		  1
	  DstBlock		  "S_AXI_AWID"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "Constant12"
	  SrcPort		  1
	  DstBlock		  "S_AXI_AWCACHE"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "Constant11"
	  SrcPort		  1
	  DstBlock		  "S_AXI_AWBURST"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "Constant10"
	  SrcPort		  1
	  DstBlock		  "S_AXI_AWADDR"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "Constant9"
	  SrcPort		  1
	  DstBlock		  "S_AXI_ARVALID"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "Constant8"
	  SrcPort		  1
	  DstBlock		  "S_AXI_ARSIZE"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "Constant7"
	  SrcPort		  1
	  DstBlock		  "S_AXI_ARPROT"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "Constant6"
	  SrcPort		  1
	  DstBlock		  "S_AXI_ARLOCK"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "Constant5"
	  SrcPort		  1
	  DstBlock		  "S_AXI_ARLEN"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "Constant4"
	  SrcPort		  1
	  DstBlock		  "S_AXI_ARID"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "Constant3"
	  SrcPort		  1
	  DstBlock		  "S_AXI_ARCACHE"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "Constant2"
	  SrcPort		  1
	  DstBlock		  "S_AXI_ARBURST"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "Constant1"
	  SrcPort		  1
	  DstBlock		  "S_AXI_ARADDR"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "Constant"
	  SrcPort		  1
	  DstBlock		  "AXI_ARESETN"
	  DstPort		  1
	}
      }
    }
    Block {
      BlockType		      From
      Name		      "From1"
      SID		      "105"
      Position		      [130, 197, 320, 213]
      ZOrder		      -9
      ShowName		      off
      GotoTag		      "reg_New_MAC_Time_MSB"
      TagVisibility	      "global"
    }
    Block {
      BlockType		      From
      Name		      "From19"
      SID		      "106"
      Position		      [130, 212, 320, 228]
      ZOrder		      -9
      ShowName		      off
      GotoTag		      "reg_New_MAC_Time_LSB"
      TagVisibility	      "global"
    }
    Block {
      BlockType		      From
      Name		      "From2"
      SID		      "204"
      Position		      [130, 77, 320, 93]
      ZOrder		      -9
      ShowName		      off
      GotoTag		      "reg_Reset_System_Time"
      TagVisibility	      "global"
    }
    Block {
      BlockType		      From
      Name		      "From3"
      SID		      "130"
      Position		      [540, 412, 730, 428]
      ZOrder		      -9
      ShowName		      off
      GotoTag		      "MAC_TIME_USEC"
      TagVisibility	      "global"
    }
    Block {
      BlockType		      From
      Name		      "From4"
      SID		      "133"
      Position		      [540, 512, 730, 528]
      ZOrder		      -9
      ShowName		      off
      GotoTag		      "SYSTEM_TIME_USEC"
      TagVisibility	      "global"
    }
    Block {
      BlockType		      From
      Name		      "From5"
      SID		      "203"
      Position		      [130, 172, 320, 188]
      ZOrder		      -9
      ShowName		      off
      GotoTag		      "reg_Load_MAC_Time"
      TagVisibility	      "global"
    }
    Block {
      BlockType		      Goto
      Name		      "Goto"
      SID		      "9"
      Position		      [940, 91, 1130, 109]
      ZOrder		      -10
      ShowName		      off
      GotoTag		      "SYSTEM_TIME_USEC"
      TagVisibility	      "global"
    }
    Block {
      BlockType		      Goto
      Name		      "Goto1"
      SID		      "108"
      Position		      [940, 206, 1130, 224]
      ZOrder		      -10
      ShowName		      off
      GotoTag		      "MAC_TIME_USEC"
      TagVisibility	      "global"
    }
    Block {
      BlockType		      Reference
      Name		      "Logical"
      SID		      "109"
      Ports		      [2, 1]
      Position		      [565, 232, 595, 263]
      ShowName		      off
      LibraryVersion	      "1.2"
      SourceBlock	      "xbsIndex_r4/Logical"
      SourceType	      "Xilinx Logical Block Block"
      logical_function	      "OR"
      inputs		      "2"
      en		      off
      latency		      "0"
      precision		      "Full"
      arith_type	      "Unsigned"
      n_bits		      "16"
      bin_pt		      "0"
      align_bp		      on
      dbl_ovrd		      off
      xl_use_area	      off
      xl_area		      "[0,0,0,0,0,0,0]"
      has_advanced_control    "0"
      sggui_pos		      "-1,-1,-1,-1"
      block_type	      "logical"
      sg_icon_stat	      "30,31,2,1,white,blue,0,7ede7d88,right,,[ ],[ ]"
      sg_mask_display	      "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 31 31 0 ],[0.77 0."
      "82 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 31 31 0 ]);\npatch([6.1 11.88 15.88 19.88 23.88 15.88 10.1 6.1 ],[19.44 19"
      ".44 23.44 19.44 23.44 23.44 23.44 19.44 ],[1 1 1 ]);\npatch([10.1 15.88 11.88 6.1 10.1 ],[15.44 15.44 19.44 19.4"
      "4 15.44 ],[0.931 0.946 0.973 ]);\npatch([6.1 11.88 15.88 10.1 6.1 ],[11.44 11.44 15.44 15.44 11.44 ],[1 1 1 ]);\n"
      "patch([10.1 23.88 19.88 15.88 11.88 6.1 10.1 ],[7.44 7.44 11.44 7.44 11.44 11.44 7.44 ],[0.931 0.946 0.973 ]);\n"
      "fprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\ncolor('black');disp('o"
      "r');\nfprintf('','COMMENT: end icon text');"
    }
    Block {
      BlockType		      Reference
      Name		      "MAC Time\n64-bit Counter"
      SID		      "110"
      Ports		      [3, 1]
      Position		      [650, 164, 710, 266]
      LibraryVersion	      "1.2"
      SourceBlock	      "xbsIndex_r4/Counter"
      SourceType	      "Xilinx Counter Block"
      infoedit		      "Hardware notes: Free running counters are the least expensive in hardware.  A count limited cou"
      "nter is implemented by combining a counter with a comparator."
      cnt_type		      "Free Running"
      cnt_to		      "Inf"
      operation		      "Up"
      start_count	      "0"
      cnt_by_val	      "1"
      arith_type	      "Unsigned"
      n_bits		      "64"
      bin_pt		      "0"
      load_pin		      on
      rst		      off
      en		      on
      explicit_period	      "off"
      period		      "1"
      dbl_ovrd		      off
      use_behavioral_HDL      off
      implementation	      "Fabric"
      xl_use_area	      off
      xl_area		      "[0,0,0,0,0,0,0]"
      has_advanced_control    "0"
      sggui_pos		      "-1,-1,-1,-1"
      block_type	      "counter"
      sg_icon_stat	      "60,102,3,1,white,blue,0,4f561634,right,,[ ],[ ]"
      sg_mask_display	      "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 0 ],[0 0 102 102 0 ],[0.77 "
      "0.82 0.91 ]);\nplot([0 60 60 0 0 ],[0 0 102 102 0 ]);\npatch([12.2 23.76 31.76 39.76 47.76 31.76 20.2 12.2 ],[59"
      ".88 59.88 67.88 59.88 67.88 67.88 67.88 59.88 ],[1 1 1 ]);\npatch([20.2 31.76 23.76 12.2 20.2 ],[51.88 51.88 59."
      "88 59.88 51.88 ],[0.931 0.946 0.973 ]);\npatch([12.2 23.76 31.76 20.2 12.2 ],[43.88 43.88 51.88 51.88 43.88 ],[1"
      " 1 1 ]);\npatch([20.2 47.76 39.76 31.76 23.76 12.2 20.2 ],[35.88 35.88 43.88 35.88 43.88 43.88 35.88 ],[0.931 0."
      "946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black'"
      ");port_label('input',1,'load');\ncolor('black');port_label('input',2,'din');\ncolor('black');port_label('input',"
      "3,'en');\n\ncolor('black');disp('{\\fontsize{14}\\bf++}','texmode','on');\nfprintf('','COMMENT: end icon text');"
    }
    Block {
      BlockType		      Reference
      Name		      "MAC_TIME_LSB"
      SID		      "22"
      Ports		      [1, 1]
      Position		      [1055, 410, 1115, 430]
      LibraryVersion	      "1.2"
      SourceBlock	      "xbsIndex_r4/Gateway Out"
      SourceType	      "Xilinx Gateway Out Block"
      infoedit		      "Gateway out block.  Converts Xilinx fixed-point or floating-point type inputs into ouputs of ty"
      "pe Simulink integer, single, double, or fixed-point.<br><br>Hardware notes:  In hardware these blocks become top"
      " level output ports or are discarded, depending on how they are configured."
      inherit_from_input      off
      hdl_port		      on
      timing_constraint	      "None"
      locs_specified	      off
      LOCs		      "{}"
      UseAsDAC		      off
      DACChannel	      "'1'"
      xl_use_area	      off
      xl_area		      "[0,0,0,0,0,0,0]"
      has_advanced_control    "0"
      sggui_pos		      "-1,-1,-1,-1"
      block_type	      "gatewayout"
      sg_icon_stat	      "60,20,1,1,white,yellow,1,cc31b7ac,right,,[ ],[ ]"
      sg_mask_display	      "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 0 ],[0 0 20 20 0 ],[0.95 0."
      "93 0.65 ]);\nplot([0 60 60 0 0 ],[0 0 20 20 0 ]);\npatch([25.55 28.44 30.44 32.44 34.44 30.44 27.55 25.55 ],[12."
      "22 12.22 14.22 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([27.55 30.44 28.44 25.55 27.55 ],[10.22 10.22 1"
      "2.22 12.22 10.22 ],[0.985 0.979 0.895 ]);\npatch([25.55 28.44 30.44 27.55 25.55 ],[8.22 8.22 10.22 10.22 8.22 ],"
      "[1 1 1 ]);\npatch([27.55 34.44 32.44 30.44 28.44 25.55 27.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.985 0.97"
      "9 0.895 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');"
      "port_label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt}\\bf Out ','texmode','on');\nf"
      "printf('','COMMENT: end icon text');"
    }
    Block {
      BlockType		      Reference
      Name		      "MAC_TIME_MSB"
      SID		      "23"
      Ports		      [1, 1]
      Position		      [1055, 450, 1115, 470]
      LibraryVersion	      "1.2"
      SourceBlock	      "xbsIndex_r4/Gateway Out"
      SourceType	      "Xilinx Gateway Out Block"
      infoedit		      "Gateway out block.  Converts Xilinx fixed-point or floating-point type inputs into ouputs of ty"
      "pe Simulink integer, single, double, or fixed-point.<br><br>Hardware notes:  In hardware these blocks become top"
      " level output ports or are discarded, depending on how they are configured."
      inherit_from_input      off
      hdl_port		      on
      timing_constraint	      "None"
      locs_specified	      off
      LOCs		      "{}"
      UseAsDAC		      off
      DACChannel	      "'1'"
      xl_use_area	      off
      xl_area		      "[0,0,0,0,0,0,0]"
      has_advanced_control    "0"
      sggui_pos		      "-1,-1,-1,-1"
      block_type	      "gatewayout"
      sg_icon_stat	      "60,20,1,1,white,yellow,1,cc31b7ac,right,,[ ],[ ]"
      sg_mask_display	      "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 0 ],[0 0 20 20 0 ],[0.95 0."
      "93 0.65 ]);\nplot([0 60 60 0 0 ],[0 0 20 20 0 ]);\npatch([25.55 28.44 30.44 32.44 34.44 30.44 27.55 25.55 ],[12."
      "22 12.22 14.22 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([27.55 30.44 28.44 25.55 27.55 ],[10.22 10.22 1"
      "2.22 12.22 10.22 ],[0.985 0.979 0.895 ]);\npatch([25.55 28.44 30.44 27.55 25.55 ],[8.22 8.22 10.22 10.22 8.22 ],"
      "[1 1 1 ]);\npatch([27.55 34.44 32.44 30.44 28.44 25.55 27.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.985 0.97"
      "9 0.895 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');"
      "port_label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt}\\bf Out ','texmode','on');\nf"
      "printf('','COMMENT: end icon text');"
    }
    Block {
      BlockType		      SubSystem
      Name		      "Posedge"
      SID		      "111"
      Ports		      [1, 1]
      Position		      [360, 171, 405, 189]
      NamePlacement	      "alternate"
      MinAlgLoopOccurrences   off
      PropExecContextOutsideSubsystem off
      RTWSystemCode	      "Auto"
      FunctionWithSeparateData off
      Opaque		      off
      RequestExecContextInheritance off
      MaskHideContents	      off
      System {
	Name			"Posedge"
	Location		[88, 301, 2330, 1301]
	Open			off
	ModelBrowserVisibility	off
	ModelBrowserWidth	200
	ScreenColor		"white"
	PaperOrientation	"landscape"
	PaperPositionMode	"auto"
	PaperType		"usletter"
	PaperUnits		"inches"
	TiledPaperMargins	[0.500000, 0.500000, 0.500000, 0.500000]
	TiledPageScale		1
	ShowPageBoundaries	off
	ZoomFactor		"100"
	Block {
	  BlockType		  Inport
	  Name			  "D"
	  SID			  "112"
	  Position		  [200, 253, 230, 267]
	  IconDisplay		  "Port number"
	}
	Block {
	  BlockType		  Reference
	  Name			  "Delay"
	  SID			  "113"
	  Ports			  [1, 1]
	  Position		  [425, 153, 460, 177]
	  ShowName		  off
	  LibraryVersion	  "1.2"
	  SourceBlock		  "xbsIndex_r4/Delay"
	  SourceType		  "Xilinx Delay Block"
	  infoedit		  "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flop. If re"
	  "gister retiming is enabled, the delay line is a chain of flip-flops."
	  rst			  off
	  infoeditControl	  "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs"
	  en			  off
	  latency		  "1"
	  dbl_ovrd		  off
	  reg_retiming		  off
	  xl_use_area		  off
	  xl_area		  "[1 1 0 0 0 0 0]"
	  has_advanced_control	  "0"
	  sggui_pos		  "-1,-1,-1,-1"
	  block_type		  "delay"
	  block_version		  "VER_STRING_GOES_HERE"
	  sg_icon_stat		  "35,24,1,1,white,blue,0,07b98262,right,,[ ],[ ]"
	  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 24 24 0 ],[0.77 0.82 0.91"
	  " ]);\nplot([0 35 35 0 0 ],[0 0 24 24 0 ]);\npatch([10.325 14.66 17.66 20.66 23.66 17.66 13.325 10.325 ],[15.33 15.3"
	  "3 18.33 15.33 18.33 18.33 18.33 15.33 ],[1 1 1 ]);\npatch([13.325 17.66 14.66 10.325 13.325 ],[12.33 12.33 15.33 15"
	  ".33 12.33 ],[0.931 0.946 0.973 ]);\npatch([10.325 14.66 17.66 13.325 10.325 ],[9.33 9.33 12.33 12.33 9.33 ],[1 1 1 "
	  "]);\npatch([13.325 23.66 20.66 17.66 14.66 10.325 13.325 ],[6.33 6.33 9.33 6.33 9.33 9.33 6.33 ],[0.931 0.946 0.973"
	  " ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');disp('"
	  "z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');"
	}
	Block {
	  BlockType		  Reference
	  Name			  "Inverter"
	  SID			  "114"
	  Ports			  [1, 1]
	  Position		  [490, 156, 515, 174]
	  ShowName		  off
	  LibraryVersion	  "1.2"
	  SourceBlock		  "xbsIndex_r4/Inverter"
	  SourceType		  "Xilinx Inverter Block"
	  infoedit		  "Bitwise logical negation (one's complement) operator."
	  en			  off
	  latency		  "0"
	  dbl_ovrd		  off
	  xl_use_area		  off
	  xl_area		  "[0 0 0 0 0 0 0]"
	  has_advanced_control	  "0"
	  sggui_pos		  "-1,-1,-1,-1"
	  block_type		  "inv"
	  block_version		  "VER_STRING_GOES_HERE"
	  sg_icon_stat		  "25,18,1,1,white,blue,0,267846e5,right,,[ ],[ ]"
	  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 18 18 0 ],[0.77 0.82 0.91"
	  " ]);\nplot([0 25 25 0 0 ],[0 0 18 18 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[11.22 11.22 13.2"
	  "2 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[9.22 9.22 11.22 11.22 9.22 ],[0."
	  "931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);\npatch([9.55 16.44 "
	  "14.44 12.44 10.44 7.55 9.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: en"
	  "d icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');disp('not');\nfprintf('','COMMENT: "
	  "end icon text');"
	}
	Block {
	  BlockType		  Reference
	  Name			  "Logical1"
	  SID			  "115"
	  Ports			  [2, 1]
	  Position		  [540, 151, 585, 204]
	  ShowName		  off
	  LibraryVersion	  "1.2"
	  SourceBlock		  "xbsIndex_r4/Logical"
	  SourceType		  "Xilinx Logical Block Block"
	  logical_function	  "AND"
	  inputs		  "2"
	  en			  off
	  latency		  "0"
	  precision		  "Full"
	  arith_type		  "Unsigned"
	  n_bits		  "8"
	  bin_pt		  "2"
	  align_bp		  on
	  dbl_ovrd		  off
	  xl_use_area		  off
	  xl_area		  "[1 0 0 1 0 0 0]"
	  has_advanced_control	  "0"
	  sggui_pos		  "-1,-1,-1,-1"
	  block_type		  "logical"
	  block_version		  "VER_STRING_GOES_HERE"
	  sg_icon_stat		  "45,53,2,1,white,blue,0,83a4b621,right,,[ ],[ ]"
	  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 53 53 0 ],[0.77 0.82 0.91"
	  " ]);\nplot([0 45 45 0 0 ],[0 0 53 53 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[32.66 32.66 38."
	  "66 32.66 38.66 38.66 38.66 32.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[26.66 26.66 32.66 32.66 26.66"
	  " ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[20.66 20.66 26.66 26.66 20.66 ],[1 1 1 ]);\npatch("
	  "[14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[14.66 14.66 20.66 14.66 20.66 20.66 14.66 ],[0.931 0.946 0.973 ]);\nfp"
	  "rintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\ncolor('black');disp('and');"
	  "\nfprintf('','COMMENT: end icon text');"
	}
	Block {
	  BlockType		  Outport
	  Name			  "Q"
	  SID			  "116"
	  Position		  [610, 173, 640, 187]
	  IconDisplay		  "Port number"
	}
	Line {
	  SrcBlock		  "Delay"
	  SrcPort		  1
	  DstBlock		  "Inverter"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "Inverter"
	  SrcPort		  1
	  DstBlock		  "Logical1"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "Logical1"
	  SrcPort		  1
	  DstBlock		  "Q"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "D"
	  SrcPort		  1
	  Points		  [150, 0; 0, -70]
	  Branch {
	    Points		    [0, -25]
	    DstBlock		    "Delay"
	    DstPort		    1
	  }
	  Branch {
	    DstBlock		    "Logical1"
	    DstPort		    2
	  }
	}
	Annotation {
	  Name			  "Rising Edge Detection"
	  Position		  [500, 112]
	}
      }
    }
    Block {
      BlockType		      Reference
      Name		      "Register"
      SID		      "18"
      Ports		      [1, 1]
      Position		      [965, 446, 995, 474]
      ShowName		      off
      LibraryVersion	      "1.2"
      SourceBlock	      "xbsIndex_r4/Register"
      SourceType	      "Xilinx Register Block"
      init		      "0"
      rst		      off
      en		      off
      dbl_ovrd		      off
      xl_use_area	      off
      xl_area		      "[0,0,0,0,0,0,0]"
      has_advanced_control    "0"
      sggui_pos		      "-1,-1,-1,-1"
      block_type	      "register"
      sg_icon_stat	      "30,28,1,1,white,blue,0,c80657c5,right,,[ ],[ ]"
      sg_mask_display	      "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 28 28 0 ],[0.77 0."
      "82 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 28 28 0 ]);\npatch([6.1 11.88 15.88 19.88 23.88 15.88 10.1 6.1 ],[18.44 18"
      ".44 22.44 18.44 22.44 22.44 22.44 18.44 ],[1 1 1 ]);\npatch([10.1 15.88 11.88 6.1 10.1 ],[14.44 14.44 18.44 18.4"
      "4 14.44 ],[0.931 0.946 0.973 ]);\npatch([6.1 11.88 15.88 10.1 6.1 ],[10.44 10.44 14.44 14.44 10.44 ],[1 1 1 ]);\n"
      "patch([10.1 23.88 19.88 15.88 11.88 6.1 10.1 ],[6.44 6.44 10.44 6.44 10.44 10.44 6.44 ],[0.931 0.946 0.973 ]);\n"
      "fprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('i"
      "nput',1,'d');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprint"
      "f('','COMMENT: end icon text');"
    }
    Block {
      BlockType		      Reference
      Name		      "Register1"
      SID		      "19"
      Ports		      [1, 1]
      Position		      [900, 446, 930, 474]
      ShowName		      off
      LibraryVersion	      "1.2"
      SourceBlock	      "xbsIndex_r4/Register"
      SourceType	      "Xilinx Register Block"
      init		      "0"
      rst		      off
      en		      off
      dbl_ovrd		      off
      xl_use_area	      off
      xl_area		      "[0,0,0,0,0,0,0]"
      has_advanced_control    "0"
      sggui_pos		      "-1,-1,-1,-1"
      block_type	      "register"
      sg_icon_stat	      "30,28,1,1,white,blue,0,c80657c5,right,,[ ],[ ]"
      sg_mask_display	      "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 28 28 0 ],[0.77 0."
      "82 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 28 28 0 ]);\npatch([6.1 11.88 15.88 19.88 23.88 15.88 10.1 6.1 ],[18.44 18"
      ".44 22.44 18.44 22.44 22.44 22.44 18.44 ],[1 1 1 ]);\npatch([10.1 15.88 11.88 6.1 10.1 ],[14.44 14.44 18.44 18.4"
      "4 14.44 ],[0.931 0.946 0.973 ]);\npatch([6.1 11.88 15.88 10.1 6.1 ],[10.44 10.44 14.44 14.44 10.44 ],[1 1 1 ]);\n"
      "patch([10.1 23.88 19.88 15.88 11.88 6.1 10.1 ],[6.44 6.44 10.44 6.44 10.44 10.44 6.44 ],[0.931 0.946 0.973 ]);\n"
      "fprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('i"
      "nput',1,'d');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprint"
      "f('','COMMENT: end icon text');"
    }
    Block {
      BlockType		      Reference
      Name		      "Register10"
      SID		      "213"
      Ports		      [1, 1]
      Position		      [965, 331, 995, 359]
      ShowName		      off
      LibraryVersion	      "1.2"
      SourceBlock	      "xbsIndex_r4/Register"
      SourceType	      "Xilinx Register Block"
      init		      "0"
      rst		      off
      en		      off
      dbl_ovrd		      off
      xl_use_area	      off
      xl_area		      "[0,0,0,0,0,0,0]"
      has_advanced_control    "0"
      sggui_pos		      "-1,-1,-1,-1"
      block_type	      "register"
      sg_icon_stat	      "30,28,1,1,white,blue,0,c80657c5,right,,[ ],[ ]"
      sg_mask_display	      "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 28 28 0 ],[0.77 0."
      "82 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 28 28 0 ]);\npatch([6.1 11.88 15.88 19.88 23.88 15.88 10.1 6.1 ],[18.44 18"
      ".44 22.44 18.44 22.44 22.44 22.44 18.44 ],[1 1 1 ]);\npatch([10.1 15.88 11.88 6.1 10.1 ],[14.44 14.44 18.44 18.4"
      "4 14.44 ],[0.931 0.946 0.973 ]);\npatch([6.1 11.88 15.88 10.1 6.1 ],[10.44 10.44 14.44 14.44 10.44 ],[1 1 1 ]);\n"
      "patch([10.1 23.88 19.88 15.88 11.88 6.1 10.1 ],[6.44 6.44 10.44 6.44 10.44 10.44 6.44 ],[0.931 0.946 0.973 ]);\n"
      "fprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('i"
      "nput',1,'d');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprint"
      "f('','COMMENT: end icon text');"
    }
    Block {
      BlockType		      Reference
      Name		      "Register11"
      SID		      "218"
      Ports		      [1, 1]
      Position		      [900, 631, 930, 659]
      ShowName		      off
      LibraryVersion	      "1.2"
      SourceBlock	      "xbsIndex_r4/Register"
      SourceType	      "Xilinx Register Block"
      init		      "0"
      rst		      off
      en		      off
      dbl_ovrd		      off
      xl_use_area	      off
      xl_area		      "[0,0,0,0,0,0,0]"
      has_advanced_control    "0"
      sggui_pos		      "-1,-1,-1,-1"
      block_type	      "register"
      sg_icon_stat	      "30,28,1,1,white,blue,0,c80657c5,right,,[ ],[ ]"
      sg_mask_display	      "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 28 28 0 ],[0.77 0."
      "82 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 28 28 0 ]);\npatch([6.1 11.88 15.88 19.88 23.88 15.88 10.1 6.1 ],[18.44 18"
      ".44 22.44 18.44 22.44 22.44 22.44 18.44 ],[1 1 1 ]);\npatch([10.1 15.88 11.88 6.1 10.1 ],[14.44 14.44 18.44 18.4"
      "4 14.44 ],[0.931 0.946 0.973 ]);\npatch([6.1 11.88 15.88 10.1 6.1 ],[10.44 10.44 14.44 14.44 10.44 ],[1 1 1 ]);\n"
      "patch([10.1 23.88 19.88 15.88 11.88 6.1 10.1 ],[6.44 6.44 10.44 6.44 10.44 10.44 6.44 ],[0.931 0.946 0.973 ]);\n"
      "fprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('i"
      "nput',1,'d');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprint"
      "f('','COMMENT: end icon text');"
    }
    Block {
      BlockType		      Reference
      Name		      "Register12"
      SID		      "219"
      Ports		      [1, 1]
      Position		      [965, 631, 995, 659]
      ShowName		      off
      LibraryVersion	      "1.2"
      SourceBlock	      "xbsIndex_r4/Register"
      SourceType	      "Xilinx Register Block"
      init		      "0"
      rst		      off
      en		      off
      dbl_ovrd		      off
      xl_use_area	      off
      xl_area		      "[0,0,0,0,0,0,0]"
      has_advanced_control    "0"
      sggui_pos		      "-1,-1,-1,-1"
      block_type	      "register"
      sg_icon_stat	      "30,28,1,1,white,blue,0,c80657c5,right,,[ ],[ ]"
      sg_mask_display	      "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 28 28 0 ],[0.77 0."
      "82 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 28 28 0 ]);\npatch([6.1 11.88 15.88 19.88 23.88 15.88 10.1 6.1 ],[18.44 18"
      ".44 22.44 18.44 22.44 22.44 22.44 18.44 ],[1 1 1 ]);\npatch([10.1 15.88 11.88 6.1 10.1 ],[14.44 14.44 18.44 18.4"
      "4 14.44 ],[0.931 0.946 0.973 ]);\npatch([6.1 11.88 15.88 10.1 6.1 ],[10.44 10.44 14.44 14.44 10.44 ],[1 1 1 ]);\n"
      "patch([10.1 23.88 19.88 15.88 11.88 6.1 10.1 ],[6.44 6.44 10.44 6.44 10.44 10.44 6.44 ],[0.931 0.946 0.973 ]);\n"
      "fprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('i"
      "nput',1,'d');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprint"
      "f('','COMMENT: end icon text');"
    }
    Block {
      BlockType		      Reference
      Name		      "Register13"
      SID		      "221"
      Ports		      [1, 1]
      Position		      [830, 631, 860, 659]
      ShowName		      off
      LibraryVersion	      "1.2"
      SourceBlock	      "xbsIndex_r4/Register"
      SourceType	      "Xilinx Register Block"
      init		      "0"
      rst		      off
      en		      off
      dbl_ovrd		      off
      xl_use_area	      off
      xl_area		      "[0,0,0,0,0,0,0]"
      has_advanced_control    "0"
      sggui_pos		      "-1,-1,-1,-1"
      block_type	      "register"
      sg_icon_stat	      "30,28,1,1,white,blue,0,c80657c5,right,,[ ],[ ]"
      sg_mask_display	      "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 28 28 0 ],[0.77 0."
      "82 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 28 28 0 ]);\npatch([6.1 11.88 15.88 19.88 23.88 15.88 10.1 6.1 ],[18.44 18"
      ".44 22.44 18.44 22.44 22.44 22.44 18.44 ],[1 1 1 ]);\npatch([10.1 15.88 11.88 6.1 10.1 ],[14.44 14.44 18.44 18.4"
      "4 14.44 ],[0.931 0.946 0.973 ]);\npatch([6.1 11.88 15.88 10.1 6.1 ],[10.44 10.44 14.44 14.44 10.44 ],[1 1 1 ]);\n"
      "patch([10.1 23.88 19.88 15.88 11.88 6.1 10.1 ],[6.44 6.44 10.44 6.44 10.44 10.44 6.44 ],[0.931 0.946 0.973 ]);\n"
      "fprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('i"
      "nput',1,'d');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprint"
      "f('','COMMENT: end icon text');"
    }
    Block {
      BlockType		      Reference
      Name		      "Register2"
      SID		      "20"
      Ports		      [1, 1]
      Position		      [900, 406, 930, 434]
      ShowName		      off
      LibraryVersion	      "1.2"
      SourceBlock	      "xbsIndex_r4/Register"
      SourceType	      "Xilinx Register Block"
      init		      "0"
      rst		      off
      en		      off
      dbl_ovrd		      off
      xl_use_area	      off
      xl_area		      "[0,0,0,0,0,0,0]"
      has_advanced_control    "0"
      sggui_pos		      "-1,-1,-1,-1"
      block_type	      "register"
      sg_icon_stat	      "30,28,1,1,white,blue,0,c80657c5,right,,[ ],[ ]"
      sg_mask_display	      "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 28 28 0 ],[0.77 0."
      "82 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 28 28 0 ]);\npatch([6.1 11.88 15.88 19.88 23.88 15.88 10.1 6.1 ],[18.44 18"
      ".44 22.44 18.44 22.44 22.44 22.44 18.44 ],[1 1 1 ]);\npatch([10.1 15.88 11.88 6.1 10.1 ],[14.44 14.44 18.44 18.4"
      "4 14.44 ],[0.931 0.946 0.973 ]);\npatch([6.1 11.88 15.88 10.1 6.1 ],[10.44 10.44 14.44 14.44 10.44 ],[1 1 1 ]);\n"
      "patch([10.1 23.88 19.88 15.88 11.88 6.1 10.1 ],[6.44 6.44 10.44 6.44 10.44 10.44 6.44 ],[0.931 0.946 0.973 ]);\n"
      "fprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('i"
      "nput',1,'d');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprint"
      "f('','COMMENT: end icon text');"
    }
    Block {
      BlockType		      Reference
      Name		      "Register3"
      SID		      "21"
      Ports		      [1, 1]
      Position		      [965, 406, 995, 434]
      ShowName		      off
      LibraryVersion	      "1.2"
      SourceBlock	      "xbsIndex_r4/Register"
      SourceType	      "Xilinx Register Block"
      init		      "0"
      rst		      off
      en		      off
      dbl_ovrd		      off
      xl_use_area	      off
      xl_area		      "[0,0,0,0,0,0,0]"
      has_advanced_control    "0"
      sggui_pos		      "-1,-1,-1,-1"
      block_type	      "register"
      sg_icon_stat	      "30,28,1,1,white,blue,0,c80657c5,right,,[ ],[ ]"
      sg_mask_display	      "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 28 28 0 ],[0.77 0."
      "82 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 28 28 0 ]);\npatch([6.1 11.88 15.88 19.88 23.88 15.88 10.1 6.1 ],[18.44 18"
      ".44 22.44 18.44 22.44 22.44 22.44 18.44 ],[1 1 1 ]);\npatch([10.1 15.88 11.88 6.1 10.1 ],[14.44 14.44 18.44 18.4"
      "4 14.44 ],[0.931 0.946 0.973 ]);\npatch([6.1 11.88 15.88 10.1 6.1 ],[10.44 10.44 14.44 14.44 10.44 ],[1 1 1 ]);\n"
      "patch([10.1 23.88 19.88 15.88 11.88 6.1 10.1 ],[6.44 6.44 10.44 6.44 10.44 10.44 6.44 ],[0.931 0.946 0.973 ]);\n"
      "fprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('i"
      "nput',1,'d');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprint"
      "f('','COMMENT: end icon text');"
    }
    Block {
      BlockType		      Reference
      Name		      "Register4"
      SID		      "136"
      Ports		      [1, 1]
      Position		      [965, 546, 995, 574]
      ShowName		      off
      LibraryVersion	      "1.2"
      SourceBlock	      "xbsIndex_r4/Register"
      SourceType	      "Xilinx Register Block"
      init		      "0"
      rst		      off
      en		      off
      dbl_ovrd		      off
      xl_use_area	      off
      xl_area		      "[0,0,0,0,0,0,0]"
      has_advanced_control    "0"
      sggui_pos		      "-1,-1,-1,-1"
      block_type	      "register"
      sg_icon_stat	      "30,28,1,1,white,blue,0,c80657c5,right,,[ ],[ ]"
      sg_mask_display	      "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 28 28 0 ],[0.77 0."
      "82 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 28 28 0 ]);\npatch([6.1 11.88 15.88 19.88 23.88 15.88 10.1 6.1 ],[18.44 18"
      ".44 22.44 18.44 22.44 22.44 22.44 18.44 ],[1 1 1 ]);\npatch([10.1 15.88 11.88 6.1 10.1 ],[14.44 14.44 18.44 18.4"
      "4 14.44 ],[0.931 0.946 0.973 ]);\npatch([6.1 11.88 15.88 10.1 6.1 ],[10.44 10.44 14.44 14.44 10.44 ],[1 1 1 ]);\n"
      "patch([10.1 23.88 19.88 15.88 11.88 6.1 10.1 ],[6.44 6.44 10.44 6.44 10.44 10.44 6.44 ],[0.931 0.946 0.973 ]);\n"
      "fprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('i"
      "nput',1,'d');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprint"
      "f('','COMMENT: end icon text');"
    }
    Block {
      BlockType		      Reference
      Name		      "Register5"
      SID		      "137"
      Ports		      [1, 1]
      Position		      [900, 546, 930, 574]
      ShowName		      off
      LibraryVersion	      "1.2"
      SourceBlock	      "xbsIndex_r4/Register"
      SourceType	      "Xilinx Register Block"
      init		      "0"
      rst		      off
      en		      off
      dbl_ovrd		      off
      xl_use_area	      off
      xl_area		      "[0,0,0,0,0,0,0]"
      has_advanced_control    "0"
      sggui_pos		      "-1,-1,-1,-1"
      block_type	      "register"
      sg_icon_stat	      "30,28,1,1,white,blue,0,c80657c5,right,,[ ],[ ]"
      sg_mask_display	      "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 28 28 0 ],[0.77 0."
      "82 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 28 28 0 ]);\npatch([6.1 11.88 15.88 19.88 23.88 15.88 10.1 6.1 ],[18.44 18"
      ".44 22.44 18.44 22.44 22.44 22.44 18.44 ],[1 1 1 ]);\npatch([10.1 15.88 11.88 6.1 10.1 ],[14.44 14.44 18.44 18.4"
      "4 14.44 ],[0.931 0.946 0.973 ]);\npatch([6.1 11.88 15.88 10.1 6.1 ],[10.44 10.44 14.44 14.44 10.44 ],[1 1 1 ]);\n"
      "patch([10.1 23.88 19.88 15.88 11.88 6.1 10.1 ],[6.44 6.44 10.44 6.44 10.44 10.44 6.44 ],[0.931 0.946 0.973 ]);\n"
      "fprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('i"
      "nput',1,'d');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprint"
      "f('','COMMENT: end icon text');"
    }
    Block {
      BlockType		      Reference
      Name		      "Register50"
      SID		      "78"
      Ports		      [1, 1]
      Position		      [810, 86, 840, 114]
      ShowName		      off
      LibraryVersion	      "1.2"
      SourceBlock	      "xbsIndex_r4/Register"
      SourceType	      "Xilinx Register Block"
      init		      "0"
      rst		      off
      en		      off
      dbl_ovrd		      off
      xl_use_area	      off
      xl_area		      "[0,0,0,0,0,0,0]"
      has_advanced_control    "0"
      sggui_pos		      "-1,-1,-1,-1"
      block_type	      "register"
      sg_icon_stat	      "30,28,1,1,white,blue,0,c80657c5,right,,[ ],[ ]"
      sg_mask_display	      "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 28 28 0 ],[0.77 0."
      "82 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 28 28 0 ]);\npatch([6.1 11.88 15.88 19.88 23.88 15.88 10.1 6.1 ],[18.44 18"
      ".44 22.44 18.44 22.44 22.44 22.44 18.44 ],[1 1 1 ]);\npatch([10.1 15.88 11.88 6.1 10.1 ],[14.44 14.44 18.44 18.4"
      "4 14.44 ],[0.931 0.946 0.973 ]);\npatch([6.1 11.88 15.88 10.1 6.1 ],[10.44 10.44 14.44 14.44 10.44 ],[1 1 1 ]);\n"
      "patch([10.1 23.88 19.88 15.88 11.88 6.1 10.1 ],[6.44 6.44 10.44 6.44 10.44 10.44 6.44 ],[0.931 0.946 0.973 ]);\n"
      "fprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('i"
      "nput',1,'d');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprint"
      "f('','COMMENT: end icon text');"
    }
    Block {
      BlockType		      Reference
      Name		      "Register6"
      SID		      "138"
      Ports		      [1, 1]
      Position		      [900, 506, 930, 534]
      ShowName		      off
      LibraryVersion	      "1.2"
      SourceBlock	      "xbsIndex_r4/Register"
      SourceType	      "Xilinx Register Block"
      init		      "0"
      rst		      off
      en		      off
      dbl_ovrd		      off
      xl_use_area	      off
      xl_area		      "[0,0,0,0,0,0,0]"
      has_advanced_control    "0"
      sggui_pos		      "-1,-1,-1,-1"
      block_type	      "register"
      sg_icon_stat	      "30,28,1,1,white,blue,0,c80657c5,right,,[ ],[ ]"
      sg_mask_display	      "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 28 28 0 ],[0.77 0."
      "82 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 28 28 0 ]);\npatch([6.1 11.88 15.88 19.88 23.88 15.88 10.1 6.1 ],[18.44 18"
      ".44 22.44 18.44 22.44 22.44 22.44 18.44 ],[1 1 1 ]);\npatch([10.1 15.88 11.88 6.1 10.1 ],[14.44 14.44 18.44 18.4"
      "4 14.44 ],[0.931 0.946 0.973 ]);\npatch([6.1 11.88 15.88 10.1 6.1 ],[10.44 10.44 14.44 14.44 10.44 ],[1 1 1 ]);\n"
      "patch([10.1 23.88 19.88 15.88 11.88 6.1 10.1 ],[6.44 6.44 10.44 6.44 10.44 10.44 6.44 ],[0.931 0.946 0.973 ]);\n"
      "fprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('i"
      "nput',1,'d');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprint"
      "f('','COMMENT: end icon text');"
    }
    Block {
      BlockType		      Reference
      Name		      "Register7"
      SID		      "139"
      Ports		      [1, 1]
      Position		      [965, 506, 995, 534]
      ShowName		      off
      LibraryVersion	      "1.2"
      SourceBlock	      "xbsIndex_r4/Register"
      SourceType	      "Xilinx Register Block"
      init		      "0"
      rst		      off
      en		      off
      dbl_ovrd		      off
      xl_use_area	      off
      xl_area		      "[0,0,0,0,0,0,0]"
      has_advanced_control    "0"
      sggui_pos		      "-1,-1,-1,-1"
      block_type	      "register"
      sg_icon_stat	      "30,28,1,1,white,blue,0,c80657c5,right,,[ ],[ ]"
      sg_mask_display	      "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 28 28 0 ],[0.77 0."
      "82 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 28 28 0 ]);\npatch([6.1 11.88 15.88 19.88 23.88 15.88 10.1 6.1 ],[18.44 18"
      ".44 22.44 18.44 22.44 22.44 22.44 18.44 ],[1 1 1 ]);\npatch([10.1 15.88 11.88 6.1 10.1 ],[14.44 14.44 18.44 18.4"
      "4 14.44 ],[0.931 0.946 0.973 ]);\npatch([6.1 11.88 15.88 10.1 6.1 ],[10.44 10.44 14.44 14.44 10.44 ],[1 1 1 ]);\n"
      "patch([10.1 23.88 19.88 15.88 11.88 6.1 10.1 ],[6.44 6.44 10.44 6.44 10.44 10.44 6.44 ],[0.931 0.946 0.973 ]);\n"
      "fprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('i"
      "nput',1,'d');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprint"
      "f('','COMMENT: end icon text');"
    }
    Block {
      BlockType		      Reference
      Name		      "Register8"
      SID		      "154"
      Ports		      [1, 1]
      Position		      [810, 201, 840, 229]
      ShowName		      off
      LibraryVersion	      "1.2"
      SourceBlock	      "xbsIndex_r4/Register"
      SourceType	      "Xilinx Register Block"
      init		      "0"
      rst		      off
      en		      off
      dbl_ovrd		      off
      xl_use_area	      off
      xl_area		      "[0,0,0,0,0,0,0]"
      has_advanced_control    "0"
      sggui_pos		      "-1,-1,-1,-1"
      block_type	      "register"
      sg_icon_stat	      "30,28,1,1,white,blue,0,c80657c5,right,,[ ],[ ]"
      sg_mask_display	      "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 28 28 0 ],[0.77 0."
      "82 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 28 28 0 ]);\npatch([6.1 11.88 15.88 19.88 23.88 15.88 10.1 6.1 ],[18.44 18"
      ".44 22.44 18.44 22.44 22.44 22.44 18.44 ],[1 1 1 ]);\npatch([10.1 15.88 11.88 6.1 10.1 ],[14.44 14.44 18.44 18.4"
      "4 14.44 ],[0.931 0.946 0.973 ]);\npatch([6.1 11.88 15.88 10.1 6.1 ],[10.44 10.44 14.44 14.44 10.44 ],[1 1 1 ]);\n"
      "patch([10.1 23.88 19.88 15.88 11.88 6.1 10.1 ],[6.44 6.44 10.44 6.44 10.44 10.44 6.44 ],[0.931 0.946 0.973 ]);\n"
      "fprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('i"
      "nput',1,'d');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprint"
      "f('','COMMENT: end icon text');"
    }
    Block {
      BlockType		      Reference
      Name		      "Register9"
      SID		      "212"
      Ports		      [1, 1]
      Position		      [900, 331, 930, 359]
      ShowName		      off
      LibraryVersion	      "1.2"
      SourceBlock	      "xbsIndex_r4/Register"
      SourceType	      "Xilinx Register Block"
      init		      "0"
      rst		      off
      en		      off
      dbl_ovrd		      off
      xl_use_area	      off
      xl_area		      "[0,0,0,0,0,0,0]"
      has_advanced_control    "0"
      sggui_pos		      "-1,-1,-1,-1"
      block_type	      "register"
      sg_icon_stat	      "30,28,1,1,white,blue,0,c80657c5,right,,[ ],[ ]"
      sg_mask_display	      "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 28 28 0 ],[0.77 0."
      "82 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 28 28 0 ]);\npatch([6.1 11.88 15.88 19.88 23.88 15.88 10.1 6.1 ],[18.44 18"
      ".44 22.44 18.44 22.44 22.44 22.44 18.44 ],[1 1 1 ]);\npatch([10.1 15.88 11.88 6.1 10.1 ],[14.44 14.44 18.44 18.4"
      "4 14.44 ],[0.931 0.946 0.973 ]);\npatch([6.1 11.88 15.88 10.1 6.1 ],[10.44 10.44 14.44 14.44 10.44 ],[1 1 1 ]);\n"
      "patch([10.1 23.88 19.88 15.88 11.88 6.1 10.1 ],[6.44 6.44 10.44 6.44 10.44 10.44 6.44 ],[0.931 0.946 0.973 ]);\n"
      "fprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('i"
      "nput',1,'d');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprint"
      "f('','COMMENT: end icon text');"
    }
    Block {
      BlockType		      SubSystem
      Name		      "Registers"
      SID		      "32"
      Ports		      []
      Position		      [283, 397, 326, 443]
      MinAlgLoopOccurrences   off
      PropExecContextOutsideSubsystem off
      RTWSystemCode	      "Auto"
      FunctionWithSeparateData off
      Opaque		      off
      RequestExecContextInheritance off
      MaskHideContents	      off
      System {
	Name			"Registers"
	Location		[2, 94, 1918, 1115]
	Open			off
	ModelBrowserVisibility	off
	ModelBrowserWidth	200
	ScreenColor		"white"
	PaperOrientation	"landscape"
	PaperPositionMode	"auto"
	PaperType		"usletter"
	PaperUnits		"inches"
	TiledPaperMargins	[0.500000, 0.500000, 0.500000, 0.500000]
	TiledPageScale		1
	ShowPageBoundaries	off
	ZoomFactor		"100"
	Block {
	  BlockType		  Reference
	  Name			  "32LSB"
	  SID			  "33"
	  Ports			  [1, 1]
	  Position		  [1010, 113, 1050, 127]
	  NamePlacement		  "alternate"
	  LibraryVersion	  "1.2"
	  SourceBlock		  "xbsIndex_r4/Slice"
	  SourceType		  "Xilinx Bit Slice Extractor Block"
	  infoedit		  "Extracts a given range of bits from each input sample and presents it at the output.  The output type "
	  "is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.<br><br>Hardwar"
	  "e notes: In hardware this block costs nothing."
	  nbits			  "32"
	  boolean_output	  off
	  mode			  "Lower Bit Location + Width"
	  bit1			  "0"
	  base1			  "MSB of Input"
	  bit0			  "0"
	  base0			  "LSB of Input"
	  dbl_ovrd		  off
	  has_advanced_control	  "0"
	  sggui_pos		  "20,20,449,398"
	  block_type		  "slice"
	  block_version		  "VER_STRING_GOES_HERE"
	  sg_icon_stat		  "40,14,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]"
	  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 14 14 0 ],[0.77 0.82 0.91"
	  " ]);\nplot([0 40 40 0 0 ],[0 0 14 14 0 ]);\npatch([15.55 18.44 20.44 22.44 24.44 20.44 17.55 15.55 ],[9.22 9.22 11."
	  "22 9.22 11.22 11.22 11.22 9.22 ],[1 1 1 ]);\npatch([17.55 20.44 18.44 15.55 17.55 ],[7.22 7.22 9.22 9.22 7.22 ],[0."
	  "931 0.946 0.973 ]);\npatch([15.55 18.44 20.44 17.55 15.55 ],[5.22 5.22 7.22 7.22 5.22 ],[1 1 1 ]);\npatch([17.55 24"
	  ".44 22.44 20.44 18.44 15.55 17.55 ],[3.22 3.22 5.22 3.22 5.22 5.22 3.22 ],[0.931 0.946 0.973 ]);\nfprintf('','COMME"
	  "NT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('output',1,'[a:b]');"
	  "\nfprintf('','COMMENT: end icon text');"
	}
	Block {
	  BlockType		  Reference
	  Name			  "32LSB1"
	  SID			  "143"
	  Ports			  [1, 1]
	  Position		  [1010, 328, 1050, 342]
	  NamePlacement		  "alternate"
	  LibraryVersion	  "1.2"
	  SourceBlock		  "xbsIndex_r4/Slice"
	  SourceType		  "Xilinx Bit Slice Extractor Block"
	  infoedit		  "Extracts a given range of bits from each input sample and presents it at the output.  The output type "
	  "is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.<br><br>Hardwar"
	  "e notes: In hardware this block costs nothing."
	  nbits			  "32"
	  boolean_output	  off
	  mode			  "Lower Bit Location + Width"
	  bit1			  "0"
	  base1			  "MSB of Input"
	  bit0			  "0"
	  base0			  "LSB of Input"
	  dbl_ovrd		  off
	  has_advanced_control	  "0"
	  sggui_pos		  "20,20,449,398"
	  block_type		  "slice"
	  block_version		  "VER_STRING_GOES_HERE"
	  sg_icon_stat		  "40,14,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]"
	  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 14 14 0 ],[0.77 0.82 0.91"
	  " ]);\nplot([0 40 40 0 0 ],[0 0 14 14 0 ]);\npatch([15.55 18.44 20.44 22.44 24.44 20.44 17.55 15.55 ],[9.22 9.22 11."
	  "22 9.22 11.22 11.22 11.22 9.22 ],[1 1 1 ]);\npatch([17.55 20.44 18.44 15.55 17.55 ],[7.22 7.22 9.22 9.22 7.22 ],[0."
	  "931 0.946 0.973 ]);\npatch([15.55 18.44 20.44 17.55 15.55 ],[5.22 5.22 7.22 7.22 5.22 ],[1 1 1 ]);\npatch([17.55 24"
	  ".44 22.44 20.44 18.44 15.55 17.55 ],[3.22 3.22 5.22 3.22 5.22 5.22 3.22 ],[0.931 0.946 0.973 ]);\nfprintf('','COMME"
	  "NT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('output',1,'[a:b]');"
	  "\nfprintf('','COMMENT: end icon text');"
	}
	Block {
	  BlockType		  Reference
	  Name			  "32MSB"
	  SID			  "37"
	  Ports			  [1, 1]
	  Position		  [1010, 208, 1050, 222]
	  LibraryVersion	  "1.2"
	  SourceBlock		  "xbsIndex_r4/Slice"
	  SourceType		  "Xilinx Bit Slice Extractor Block"
	  infoedit		  "Extracts a given range of bits from each input sample and presents it at the output.  The output type "
	  "is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.<br><br>Hardwar"
	  "e notes: In hardware this block costs nothing."
	  nbits			  "32"
	  boolean_output	  off
	  mode			  "Upper Bit Location + Width"
	  bit1			  "0"
	  base1			  "MSB of Input"
	  bit0			  "0"
	  base0			  "LSB of Input"
	  dbl_ovrd		  off
	  has_advanced_control	  "0"
	  sggui_pos		  "20,20,449,398"
	  block_type		  "slice"
	  block_version		  "VER_STRING_GOES_HERE"
	  sg_icon_stat		  "40,14,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]"
	  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 14 14 0 ],[0.77 0.82 0.91"
	  " ]);\nplot([0 40 40 0 0 ],[0 0 14 14 0 ]);\npatch([15.55 18.44 20.44 22.44 24.44 20.44 17.55 15.55 ],[9.22 9.22 11."
	  "22 9.22 11.22 11.22 11.22 9.22 ],[1 1 1 ]);\npatch([17.55 20.44 18.44 15.55 17.55 ],[7.22 7.22 9.22 9.22 7.22 ],[0."
	  "931 0.946 0.973 ]);\npatch([15.55 18.44 20.44 17.55 15.55 ],[5.22 5.22 7.22 7.22 5.22 ],[1 1 1 ]);\npatch([17.55 24"
	  ".44 22.44 20.44 18.44 15.55 17.55 ],[3.22 3.22 5.22 3.22 5.22 5.22 3.22 ],[0.931 0.946 0.973 ]);\nfprintf('','COMME"
	  "NT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('output',1,'[a:b]');"
	  "\nfprintf('','COMMENT: end icon text');"
	}
	Block {
	  BlockType		  Reference
	  Name			  "32MSB1"
	  SID			  "144"
	  Ports			  [1, 1]
	  Position		  [1010, 423, 1050, 437]
	  LibraryVersion	  "1.2"
	  SourceBlock		  "xbsIndex_r4/Slice"
	  SourceType		  "Xilinx Bit Slice Extractor Block"
	  infoedit		  "Extracts a given range of bits from each input sample and presents it at the output.  The output type "
	  "is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.<br><br>Hardwar"
	  "e notes: In hardware this block costs nothing."
	  nbits			  "32"
	  boolean_output	  off
	  mode			  "Upper Bit Location + Width"
	  bit1			  "0"
	  base1			  "MSB of Input"
	  bit0			  "0"
	  base0			  "LSB of Input"
	  dbl_ovrd		  off
	  has_advanced_control	  "0"
	  sggui_pos		  "20,20,449,398"
	  block_type		  "slice"
	  block_version		  "VER_STRING_GOES_HERE"
	  sg_icon_stat		  "40,14,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]"
	  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 14 14 0 ],[0.77 0.82 0.91"
	  " ]);\nplot([0 40 40 0 0 ],[0 0 14 14 0 ]);\npatch([15.55 18.44 20.44 22.44 24.44 20.44 17.55 15.55 ],[9.22 9.22 11."
	  "22 9.22 11.22 11.22 11.22 9.22 ],[1 1 1 ]);\npatch([17.55 20.44 18.44 15.55 17.55 ],[7.22 7.22 9.22 9.22 7.22 ],[0."
	  "931 0.946 0.973 ]);\npatch([15.55 18.44 20.44 17.55 15.55 ],[5.22 5.22 7.22 7.22 5.22 ],[1 1 1 ]);\npatch([17.55 24"
	  ".44 22.44 20.44 18.44 15.55 17.55 ],[3.22 3.22 5.22 3.22 5.22 5.22 3.22 ],[0.931 0.946 0.973 ]);\nfprintf('','COMME"
	  "NT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('output',1,'[a:b]');"
	  "\nfprintf('','COMMENT: end icon text');"
	}
	Block {
	  BlockType		  Reference
	  Name			  "Constant1"
	  SID			  "145"
	  Ports			  [0, 1]
	  Position		  [1085, 355, 1110, 375]
	  ShowName		  off
	  LibraryVersion	  "1.2"
	  SourceBlock		  "xbsIndex_r4/Constant"
	  SourceType		  "Xilinx Constant Block Block"
	  const			  "1"
	  gui_display_data_type	  "Boolean"
	  arith_type		  "Boolean"
	  n_bits		  "30"
	  bin_pt		  "0"
	  preci_type		  "Single"
	  exp_width		  "8"
	  frac_width		  "24"
	  explicit_period	  on
	  period		  "1"
	  dsp48_infoedit	  "The use of this block for DSP48 instructions is deprecated.  Please use the Opmode block."
	  equ			  "P=C"
	  opselect		  "C"
	  inp2			  "PCIN>>17"
	  opr			  "+"
	  inp1			  "P"
	  carry			  "CIN"
	  dbl_ovrd		  off
	  has_advanced_control	  "0"
	  sggui_pos		  "-1,-1,-1,-1"
	  block_type		  "constant"
	  sg_icon_stat		  "25,20,0,1,white,blue,0,1c72b5be,right,,[ ],[ ]"
	  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 20 20 0 ],[0.77 0.82 0.91"
	  " ]);\nplot([0 25 25 0 0 ],[0 0 20 20 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[12.22 12.22 14.2"
	  "2 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[10.22 10.22 12.22 12.22 10.22 ],"
	  "[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[8.22 8.22 10.22 10.22 8.22 ],[1 1 1 ]);\npatch([9.55 1"
	  "6.44 14.44 12.44 10.44 7.55 9.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMEN"
	  "T: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'1');\nfprin"
	  "tf('','COMMENT: end icon text');"
	}
	Block {
	  BlockType		  Reference
	  Name			  "Constant2"
	  SID			  "146"
	  Ports			  [0, 1]
	  Position		  [1085, 450, 1110, 470]
	  ShowName		  off
	  LibraryVersion	  "1.2"
	  SourceBlock		  "xbsIndex_r4/Constant"
	  SourceType		  "Xilinx Constant Block Block"
	  const			  "1"
	  gui_display_data_type	  "Boolean"
	  arith_type		  "Boolean"
	  n_bits		  "30"
	  bin_pt		  "0"
	  preci_type		  "Single"
	  exp_width		  "8"
	  frac_width		  "24"
	  explicit_period	  on
	  period		  "1"
	  dsp48_infoedit	  "The use of this block for DSP48 instructions is deprecated.  Please use the Opmode block."
	  equ			  "P=C"
	  opselect		  "C"
	  inp2			  "PCIN>>17"
	  opr			  "+"
	  inp1			  "P"
	  carry			  "CIN"
	  dbl_ovrd		  off
	  has_advanced_control	  "0"
	  sggui_pos		  "-1,-1,-1,-1"
	  block_type		  "constant"
	  sg_icon_stat		  "25,20,0,1,white,blue,0,1c72b5be,right,,[ ],[ ]"
	  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 20 20 0 ],[0.77 0.82 0.91"
	  " ]);\nplot([0 25 25 0 0 ],[0 0 20 20 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[12.22 12.22 14.2"
	  "2 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[10.22 10.22 12.22 12.22 10.22 ],"
	  "[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[8.22 8.22 10.22 10.22 8.22 ],[1 1 1 ]);\npatch([9.55 1"
	  "6.44 14.44 12.44 10.44 7.55 9.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMEN"
	  "T: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'1');\nfprin"
	  "tf('','COMMENT: end icon text');"
	}
	Block {
	  BlockType		  Reference
	  Name			  "Constant5"
	  SID			  "42"
	  Ports			  [0, 1]
	  Position		  [1085, 140, 1110, 160]
	  ShowName		  off
	  LibraryVersion	  "1.2"
	  SourceBlock		  "xbsIndex_r4/Constant"
	  SourceType		  "Xilinx Constant Block Block"
	  const			  "1"
	  gui_display_data_type	  "Boolean"
	  arith_type		  "Boolean"
	  n_bits		  "30"
	  bin_pt		  "0"
	  preci_type		  "Single"
	  exp_width		  "8"
	  frac_width		  "24"
	  explicit_period	  on
	  period		  "1"
	  dsp48_infoedit	  "The use of this block for DSP48 instructions is deprecated.  Please use the Opmode block."
	  equ			  "P=C"
	  opselect		  "C"
	  inp2			  "PCIN>>17"
	  opr			  "+"
	  inp1			  "P"
	  carry			  "CIN"
	  dbl_ovrd		  off
	  has_advanced_control	  "0"
	  sggui_pos		  "-1,-1,-1,-1"
	  block_type		  "constant"
	  sg_icon_stat		  "25,20,0,1,white,blue,0,1c72b5be,right,,[ ],[ ]"
	  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 20 20 0 ],[0.77 0.82 0.91"
	  " ]);\nplot([0 25 25 0 0 ],[0 0 20 20 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[12.22 12.22 14.2"
	  "2 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[10.22 10.22 12.22 12.22 10.22 ],"
	  "[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[8.22 8.22 10.22 10.22 8.22 ],[1 1 1 ]);\npatch([9.55 1"
	  "6.44 14.44 12.44 10.44 7.55 9.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMEN"
	  "T: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'1');\nfprin"
	  "tf('','COMMENT: end icon text');"
	}
	Block {
	  BlockType		  Reference
	  Name			  "Constant6"
	  SID			  "43"
	  Ports			  [0, 1]
	  Position		  [1085, 235, 1110, 255]
	  ShowName		  off
	  LibraryVersion	  "1.2"
	  SourceBlock		  "xbsIndex_r4/Constant"
	  SourceType		  "Xilinx Constant Block Block"
	  const			  "1"
	  gui_display_data_type	  "Boolean"
	  arith_type		  "Boolean"
	  n_bits		  "30"
	  bin_pt		  "0"
	  preci_type		  "Single"
	  exp_width		  "8"
	  frac_width		  "24"
	  explicit_period	  on
	  period		  "1"
	  dsp48_infoedit	  "The use of this block for DSP48 instructions is deprecated.  Please use the Opmode block."
	  equ			  "P=C"
	  opselect		  "C"
	  inp2			  "PCIN>>17"
	  opr			  "+"
	  inp1			  "P"
	  carry			  "CIN"
	  dbl_ovrd		  off
	  has_advanced_control	  "0"
	  sggui_pos		  "-1,-1,-1,-1"
	  block_type		  "constant"
	  sg_icon_stat		  "25,20,0,1,white,blue,0,1c72b5be,right,,[ ],[ ]"
	  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 20 20 0 ],[0.77 0.82 0.91"
	  " ]);\nplot([0 25 25 0 0 ],[0 0 20 20 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[12.22 12.22 14.2"
	  "2 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[10.22 10.22 12.22 12.22 10.22 ],"
	  "[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[8.22 8.22 10.22 10.22 8.22 ],[1 1 1 ]);\npatch([9.55 1"
	  "6.44 14.44 12.44 10.44 7.55 9.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMEN"
	  "T: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'1');\nfprin"
	  "tf('','COMMENT: end icon text');"
	}
	Block {
	  BlockType		  SubSystem
	  Name			  "Ctrl Bits"
	  SID			  "155"
	  Ports			  [1]
	  Position		  [445, 124, 495, 156]
	  MinAlgLoopOccurrences	  off
	  PropExecContextOutsideSubsystem off
	  RTWSystemCode		  "Auto"
	  FunctionWithSeparateData off
	  Opaque		  off
	  RequestExecContextInheritance	off
	  MaskHideContents	  off
	  System {
	    Name		    "Ctrl Bits"
	    Location		    [950, 345, 1480, 478]
	    Open		    off
	    ModelBrowserVisibility  off
	    ModelBrowserWidth	    200
	    ScreenColor		    "white"
	    PaperOrientation	    "landscape"
	    PaperPositionMode	    "auto"
	    PaperType		    "usletter"
	    PaperUnits		    "inches"
	    TiledPaperMargins	    [0.500000, 0.500000, 0.500000, 0.500000]
	    TiledPageScale	    1
	    ShowPageBoundaries	    off
	    ZoomFactor		    "100"
	    Block {
	      BlockType		      Inport
	      Name		      "32b"
	      SID		      "156"
	      Position		      [25, 83, 55, 97]
	      IconDisplay	      "Port number"
	    }
	    Block {
	      BlockType		      Goto
	      Name		      "Goto1"
	      SID		      "158"
	      Position		      [340, 80, 540, 100]
	      ShowName		      off
	      GotoTag		      "reg_Reset_System_Time"
	      TagVisibility	      "global"
	    }
	    Block {
	      BlockType		      Goto
	      Name		      "Goto14"
	      SID		      "200"
	      Position		      [340, 120, 540, 140]
	      ShowName		      off
	      GotoTag		      "reg_Load_MAC_Time"
	      TagVisibility	      "global"
	    }
	    Block {
	      BlockType		      SubSystem
	      Name		      "Sim Reset"
	      SID		      "177"
	      Ports		      [0, 1]
	      Position		      [180, 25, 225, 55]
	      MinAlgLoopOccurrences   off
	      PropExecContextOutsideSubsystem off
	      RTWSystemCode	      "Auto"
	      FunctionWithSeparateData off
	      Opaque		      off
	      RequestExecContextInheritance off
	      MaskHideContents	      off
	      System {
		Name			"Sim Reset"
		Location		[347, 173, 617, 257]
		Open			off
		ModelBrowserVisibility	off
		ModelBrowserWidth	200
		ScreenColor		"white"
		PaperOrientation	"landscape"
		PaperPositionMode	"auto"
		PaperType		"usletter"
		PaperUnits		"inches"
		TiledPaperMargins	[0.500000, 0.500000, 0.500000, 0.500000]
		TiledPageScale		1
		ShowPageBoundaries	off
		ZoomFactor		"100"
		Block {
		  BlockType		  Sum
		  Name			  "Add"
		  SID			  "178"
		  Ports			  [2, 1]
		  Position		  [90, 57, 120, 88]
		  ZOrder		  -2
		  InputSameDT		  off
		  OutDataTypeStr	  "Inherit: Inherit via internal rule"
		  SaturateOnIntegerOverflow off
		}
		Block {
		  BlockType		  Reference
		  Name			  "Disregard Subsystem"
		  SID			  "179"
		  Tag			  "discardX"
		  Ports			  []
		  Position		  [553, 252, 611, 310]
		  ShowName		  off
		  AttributesFormatString  "Disregard Subsystem\\nFor Generation"
		  LibraryVersion	  "1.2"
		  SourceBlock		  "xbsIndex_r4/Disregard Subsystem"
		  SourceType		  "Xilinx Disregard Subsystem For Generation Block"
		  infoedit		  "Place this block into a subsystem to have System Generator ignore the subsystem during code generatio"
		  "n. This block can be used in combination with the Simulation Multiplexer block to provide an alternative simulatio"
		  "n model for another subsystem (e.g., to provide a simulation model for a black box)."
		  has_advanced_control	  "0"
		  sggui_pos		  "-1,-1,-1,-1"
		  block_type		  "disregard"
		  sg_icon_stat		  "58,58,-1,-1,darkgray,black,0,07734,right,,[ ],[ ]"
		  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 58 58 0 0 ],[0 0 58 58 0 ],[0.1 0.1 0.1 ]"
		  ");\nplot([0 58 58 0 0 ],[0 0 58 58 0 ]);\npatch([11.2 22.76 30.76 38.76 46.76 30.76 19.2 11.2 ],[37.88 37.88 45.88"
		  " 37.88 45.88 45.88 45.88 37.88 ],[0.33 0.33 0.33 ]);\npatch([19.2 30.76 22.76 11.2 19.2 ],[29.88 29.88 37.88 37.88"
		  " 29.88 ],[0.261 0.261 0.261 ]);\npatch([11.2 22.76 30.76 19.2 11.2 ],[21.88 21.88 29.88 29.88 21.88 ],[0.33 0.33 0"
		  ".33 ]);\npatch([19.2 46.76 38.76 30.76 22.76 11.2 19.2 ],[13.88 13.88 21.88 13.88 21.88 21.88 13.88 ],[0.261 0.261"
		  " 0.261 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\nfprintf('','COMMEN"
		  "T: end icon text');"
		}
		Block {
		  BlockType		  DiscretePulseGenerator
		  Name			  "Pulse\nGenerator"
		  SID			  "180"
		  Ports			  [0, 1]
		  Position		  [25, 29, 55, 61]
		  ZOrder		  -13
		  Period		  "1e6"
		  PulseWidth		  "2"
		  PhaseDelay		  "1.25e4"
		}
		Block {
		  BlockType		  DiscretePulseGenerator
		  Name			  "Pulse\nGenerator1"
		  SID			  "181"
		  Ports			  [0, 1]
		  Position		  [25, 99, 55, 131]
		  ZOrder		  -13
		  Period		  "1e6"
		  PulseWidth		  "2"
		  PhaseDelay		  "2.5e4"
		}
		Block {
		  BlockType		  Reference
		  Name			  "sim_only_reset"
		  SID			  "182"
		  Ports			  [1, 1]
		  Position		  [190, 63, 230, 77]
		  LibraryVersion	  "1.2"
		  SourceBlock		  "xbsIndex_r4/Gateway In"
		  SourceType		  "Xilinx Gateway In Block"
		  infoedit		  "Gateway in block.  Converts inputs of type Simulink integer, single, double and fixed-point to  Xilin"
		  "x fixed-point or floating-point data type.<br><br>Hardware notes:  In hardware these blocks become top level input"
		  " ports."
		  gui_display_data_type	  "Fixed-point"
		  arith_type		  "Unsigned"
		  n_bits		  "1"
		  bin_pt		  "0"
		  preci_type		  "Single"
		  exp_width		  "8"
		  frac_width		  "24"
		  quantization		  "Round  (unbiased: +/- Inf)"
		  overflow		  "Saturate"
		  period		  "1"
		  dbl_ovrd		  off
		  timing_constraint	  "None"
		  locs_specified	  off
		  LOCs			  "{}"
		  UseAsADC		  off
		  ADCChannel		  "'1'"
		  xl_use_area		  off
		  xl_area		  "[0,0,0,0,0,0,0]"
		  inherit_from_input	  off
		  hdl_port		  "on"
		  has_advanced_control	  "0"
		  sggui_pos		  "-1,-1,-1,-1"
		  block_type		  "gatewayin"
		  sg_icon_stat		  "40,14,1,1,white,yellow,1,00d3666e,right,,[ ],[ ]"
		  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 14 14 0 ],[0.95 0.93 0.6"
		  "5 ]);\nplot([0 40 40 0 0 ],[0 0 14 14 0 ]);\npatch([15.55 18.44 20.44 22.44 24.44 20.44 17.55 15.55 ],[9.22 9.22 1"
		  "1.22 9.22 11.22 11.22 11.22 9.22 ],[1 1 1 ]);\npatch([17.55 20.44 18.44 15.55 17.55 ],[7.22 7.22 9.22 9.22 7.22 ],"
		  "[0.985 0.979 0.895 ]);\npatch([15.55 18.44 20.44 17.55 15.55 ],[5.22 5.22 7.22 7.22 5.22 ],[1 1 1 ]);\npatch([17.5"
		  "5 24.44 22.44 20.44 18.44 15.55 17.55 ],[3.22 3.22 5.22 3.22 5.22 5.22 3.22 ],[0.985 0.979 0.895 ]);\nfprintf('','"
		  "COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'\\fon"
		  "tsize{11pt}\\bf In ','texmode','on');\ncolor('black');port_label('output',1,' ');\nfprintf('','COMMENT: end icon t"
		  "ext');"
		}
		Block {
		  BlockType		  Outport
		  Name			  "Out1"
		  SID			  "183"
		  Position		  [255, 63, 285, 77]
		  IconDisplay		  "Port number"
		}
		Line {
		  SrcBlock		  "Add"
		  SrcPort		  1
		  Points		  [5, 0; 0, -5]
		  DstBlock		  "sim_only_reset"
		  DstPort		  1
		}
		Line {
		  SrcBlock		  "Pulse\nGenerator1"
		  SrcPort		  1
		  Points		  [10, 0; 0, -35]
		  DstBlock		  "Add"
		  DstPort		  2
		}
		Line {
		  SrcBlock		  "Pulse\nGenerator"
		  SrcPort		  1
		  Points		  [10, 0; 0, 20]
		  DstBlock		  "Add"
		  DstPort		  1
		}
		Line {
		  SrcBlock		  "sim_only_reset"
		  SrcPort		  1
		  DstBlock		  "Out1"
		  DstPort		  1
		}
	      }
	    }
	    Block {
	      BlockType		      Reference
	      Name		      "b[0]"
	      SID		      "184"
	      Ports		      [1, 1]
	      Position		      [135, 83, 175, 97]
	      LibraryVersion	      "1.2"
	      SourceBlock	      "xbsIndex_r4/Slice"
	      SourceType	      "Xilinx Bit Slice Extractor Block"
	      infoedit		      "Extracts a given range of bits from each input sample and presents it at the output.  The outp"
	      "ut type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.<br"
	      "><br>Hardware notes: In hardware this block costs nothing."
	      nbits		      "1"
	      boolean_output	      on
	      mode		      "Lower Bit Location + Width"
	      bit1		      "0"
	      base1		      "MSB of Input"
	      bit0		      "0"
	      base0		      "LSB of Input"
	      dbl_ovrd		      off
	      has_advanced_control    "0"
	      sggui_pos		      "20,20,449,398"
	      block_type	      "slice"
	      block_version	      "VER_STRING_GOES_HERE"
	      sg_icon_stat	      "40,14,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]"
	      sg_mask_display	      "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 14 14 0 ],[0.77 0"
	      ".82 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 14 14 0 ]);\npatch([15.55 18.44 20.44 22.44 24.44 20.44 17.55 15.55 ],[9"
	      ".22 9.22 11.22 9.22 11.22 11.22 11.22 9.22 ],[1 1 1 ]);\npatch([17.55 20.44 18.44 15.55 17.55 ],[7.22 7.22 9.22"
	      " 9.22 7.22 ],[0.931 0.946 0.973 ]);\npatch([15.55 18.44 20.44 17.55 15.55 ],[5.22 5.22 7.22 7.22 5.22 ],[1 1 1 "
	      "]);\npatch([17.55 24.44 22.44 20.44 18.44 15.55 17.55 ],[3.22 3.22 5.22 3.22 5.22 5.22 3.22 ],[0.931 0.946 0.97"
	      "3 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');por"
	      "t_label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');"
	    }
	    Block {
	      BlockType		      Reference
	      Name		      "b[1]  "
	      SID		      "189"
	      Ports		      [1, 1]
	      Position		      [135, 123, 175, 137]
	      LibraryVersion	      "1.2"
	      SourceBlock	      "xbsIndex_r4/Slice"
	      SourceType	      "Xilinx Bit Slice Extractor Block"
	      infoedit		      "Extracts a given range of bits from each input sample and presents it at the output.  The outp"
	      "ut type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.<br"
	      "><br>Hardware notes: In hardware this block costs nothing."
	      nbits		      "1"
	      boolean_output	      on
	      mode		      "Lower Bit Location + Width"
	      bit1		      "0"
	      base1		      "MSB of Input"
	      bit0		      "1"
	      base0		      "LSB of Input"
	      dbl_ovrd		      off
	      has_advanced_control    "0"
	      sggui_pos		      "20,20,449,398"
	      block_type	      "slice"
	      block_version	      "VER_STRING_GOES_HERE"
	      sg_icon_stat	      "40,14,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]"
	      sg_mask_display	      "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 14 14 0 ],[0.77 0"
	      ".82 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 14 14 0 ]);\npatch([15.55 18.44 20.44 22.44 24.44 20.44 17.55 15.55 ],[9"
	      ".22 9.22 11.22 9.22 11.22 11.22 11.22 9.22 ],[1 1 1 ]);\npatch([17.55 20.44 18.44 15.55 17.55 ],[7.22 7.22 9.22"
	      " 9.22 7.22 ],[0.931 0.946 0.973 ]);\npatch([15.55 18.44 20.44 17.55 15.55 ],[5.22 5.22 7.22 7.22 5.22 ],[1 1 1 "
	      "]);\npatch([17.55 24.44 22.44 20.44 18.44 15.55 17.55 ],[3.22 3.22 5.22 3.22 5.22 5.22 3.22 ],[0.931 0.946 0.97"
	      "3 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');por"
	      "t_label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');"
	    }
	    Block {
	      BlockType		      Reference
	      Name		      "b[2]"
	      SID		      "190"
	      Ports		      [1, 1]
	      Position		      [135, 163, 175, 177]
	      LibraryVersion	      "1.2"
	      SourceBlock	      "xbsIndex_r4/Slice"
	      SourceType	      "Xilinx Bit Slice Extractor Block"
	      infoedit		      "Extracts a given range of bits from each input sample and presents it at the output.  The outp"
	      "ut type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.<br"
	      "><br>Hardware notes: In hardware this block costs nothing."
	      nbits		      "1"
	      boolean_output	      on
	      mode		      "Lower Bit Location + Width"
	      bit1		      "0"
	      base1		      "MSB of Input"
	      bit0		      "2"
	      base0		      "LSB of Input"
	      dbl_ovrd		      off
	      has_advanced_control    "0"
	      sggui_pos		      "20,20,449,398"
	      block_type	      "slice"
	      block_version	      "VER_STRING_GOES_HERE"
	      sg_icon_stat	      "40,14,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]"
	      sg_mask_display	      "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 14 14 0 ],[0.77 0"
	      ".82 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 14 14 0 ]);\npatch([15.55 18.44 20.44 22.44 24.44 20.44 17.55 15.55 ],[9"
	      ".22 9.22 11.22 9.22 11.22 11.22 11.22 9.22 ],[1 1 1 ]);\npatch([17.55 20.44 18.44 15.55 17.55 ],[7.22 7.22 9.22"
	      " 9.22 7.22 ],[0.931 0.946 0.973 ]);\npatch([15.55 18.44 20.44 17.55 15.55 ],[5.22 5.22 7.22 7.22 5.22 ],[1 1 1 "
	      "]);\npatch([17.55 24.44 22.44 20.44 18.44 15.55 17.55 ],[3.22 3.22 5.22 3.22 5.22 5.22 3.22 ],[0.931 0.946 0.97"
	      "3 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');por"
	      "t_label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');"
	    }
	    Block {
	      BlockType		      Reference
	      Name		      "b[3]"
	      SID		      "191"
	      Ports		      [1, 1]
	      Position		      [135, 203, 175, 217]
	      LibraryVersion	      "1.2"
	      SourceBlock	      "xbsIndex_r4/Slice"
	      SourceType	      "Xilinx Bit Slice Extractor Block"
	      infoedit		      "Extracts a given range of bits from each input sample and presents it at the output.  The outp"
	      "ut type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.<br"
	      "><br>Hardware notes: In hardware this block costs nothing."
	      nbits		      "1"
	      boolean_output	      on
	      mode		      "Lower Bit Location + Width"
	      bit1		      "0"
	      base1		      "MSB of Input"
	      bit0		      "3"
	      base0		      "LSB of Input"
	      dbl_ovrd		      off
	      has_advanced_control    "0"
	      sggui_pos		      "20,20,449,398"
	      block_type	      "slice"
	      block_version	      "VER_STRING_GOES_HERE"
	      sg_icon_stat	      "40,14,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]"
	      sg_mask_display	      "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 14 14 0 ],[0.77 0"
	      ".82 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 14 14 0 ]);\npatch([15.55 18.44 20.44 22.44 24.44 20.44 17.55 15.55 ],[9"
	      ".22 9.22 11.22 9.22 11.22 11.22 11.22 9.22 ],[1 1 1 ]);\npatch([17.55 20.44 18.44 15.55 17.55 ],[7.22 7.22 9.22"
	      " 9.22 7.22 ],[0.931 0.946 0.973 ]);\npatch([15.55 18.44 20.44 17.55 15.55 ],[5.22 5.22 7.22 7.22 5.22 ],[1 1 1 "
	      "]);\npatch([17.55 24.44 22.44 20.44 18.44 15.55 17.55 ],[3.22 3.22 5.22 3.22 5.22 5.22 3.22 ],[0.931 0.946 0.97"
	      "3 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');por"
	      "t_label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');"
	    }
	    Block {
	      BlockType		      Reference
	      Name		      "b[4]"
	      SID		      "192"
	      Ports		      [1, 1]
	      Position		      [135, 263, 175, 277]
	      LibraryVersion	      "1.2"
	      SourceBlock	      "xbsIndex_r4/Slice"
	      SourceType	      "Xilinx Bit Slice Extractor Block"
	      infoedit		      "Extracts a given range of bits from each input sample and presents it at the output.  The outp"
	      "ut type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.<br"
	      "><br>Hardware notes: In hardware this block costs nothing."
	      nbits		      "1"
	      boolean_output	      on
	      mode		      "Lower Bit Location + Width"
	      bit1		      "0"
	      base1		      "MSB of Input"
	      bit0		      "4"
	      base0		      "LSB of Input"
	      dbl_ovrd		      off
	      has_advanced_control    "0"
	      sggui_pos		      "20,20,449,398"
	      block_type	      "slice"
	      block_version	      "VER_STRING_GOES_HERE"
	      sg_icon_stat	      "40,14,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]"
	      sg_mask_display	      "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 14 14 0 ],[0.77 0"
	      ".82 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 14 14 0 ]);\npatch([15.55 18.44 20.44 22.44 24.44 20.44 17.55 15.55 ],[9"
	      ".22 9.22 11.22 9.22 11.22 11.22 11.22 9.22 ],[1 1 1 ]);\npatch([17.55 20.44 18.44 15.55 17.55 ],[7.22 7.22 9.22"
	      " 9.22 7.22 ],[0.931 0.946 0.973 ]);\npatch([15.55 18.44 20.44 17.55 15.55 ],[5.22 5.22 7.22 7.22 5.22 ],[1 1 1 "
	      "]);\npatch([17.55 24.44 22.44 20.44 18.44 15.55 17.55 ],[3.22 3.22 5.22 3.22 5.22 5.22 3.22 ],[0.931 0.946 0.97"
	      "3 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');por"
	      "t_label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');"
	    }
	    Block {
	      BlockType		      Reference
	      Name		      "b[5]"
	      SID		      "193"
	      Ports		      [1, 1]
	      Position		      [135, 303, 175, 317]
	      LibraryVersion	      "1.2"
	      SourceBlock	      "xbsIndex_r4/Slice"
	      SourceType	      "Xilinx Bit Slice Extractor Block"
	      infoedit		      "Extracts a given range of bits from each input sample and presents it at the output.  The outp"
	      "ut type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.<br"
	      "><br>Hardware notes: In hardware this block costs nothing."
	      nbits		      "1"
	      boolean_output	      on
	      mode		      "Lower Bit Location + Width"
	      bit1		      "0"
	      base1		      "MSB of Input"
	      bit0		      "5"
	      base0		      "LSB of Input"
	      dbl_ovrd		      off
	      has_advanced_control    "0"
	      sggui_pos		      "20,20,449,398"
	      block_type	      "slice"
	      block_version	      "VER_STRING_GOES_HERE"
	      sg_icon_stat	      "40,14,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]"
	      sg_mask_display	      "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 14 14 0 ],[0.77 0"
	      ".82 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 14 14 0 ]);\npatch([15.55 18.44 20.44 22.44 24.44 20.44 17.55 15.55 ],[9"
	      ".22 9.22 11.22 9.22 11.22 11.22 11.22 9.22 ],[1 1 1 ]);\npatch([17.55 20.44 18.44 15.55 17.55 ],[7.22 7.22 9.22"
	      " 9.22 7.22 ],[0.931 0.946 0.973 ]);\npatch([15.55 18.44 20.44 17.55 15.55 ],[5.22 5.22 7.22 7.22 5.22 ],[1 1 1 "
	      "]);\npatch([17.55 24.44 22.44 20.44 18.44 15.55 17.55 ],[3.22 3.22 5.22 3.22 5.22 5.22 3.22 ],[0.931 0.946 0.97"
	      "3 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');por"
	      "t_label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');"
	    }
	    Block {
	      BlockType		      Reference
	      Name		      "b[6]"
	      SID		      "194"
	      Ports		      [1, 1]
	      Position		      [135, 343, 175, 357]
	      LibraryVersion	      "1.2"
	      SourceBlock	      "xbsIndex_r4/Slice"
	      SourceType	      "Xilinx Bit Slice Extractor Block"
	      infoedit		      "Extracts a given range of bits from each input sample and presents it at the output.  The outp"
	      "ut type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.<br"
	      "><br>Hardware notes: In hardware this block costs nothing."
	      nbits		      "1"
	      boolean_output	      on
	      mode		      "Lower Bit Location + Width"
	      bit1		      "0"
	      base1		      "MSB of Input"
	      bit0		      "6"
	      base0		      "LSB of Input"
	      dbl_ovrd		      off
	      has_advanced_control    "0"
	      sggui_pos		      "20,20,449,398"
	      block_type	      "slice"
	      block_version	      "VER_STRING_GOES_HERE"
	      sg_icon_stat	      "40,14,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]"
	      sg_mask_display	      "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 14 14 0 ],[0.77 0"
	      ".82 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 14 14 0 ]);\npatch([15.55 18.44 20.44 22.44 24.44 20.44 17.55 15.55 ],[9"
	      ".22 9.22 11.22 9.22 11.22 11.22 11.22 9.22 ],[1 1 1 ]);\npatch([17.55 20.44 18.44 15.55 17.55 ],[7.22 7.22 9.22"
	      " 9.22 7.22 ],[0.931 0.946 0.973 ]);\npatch([15.55 18.44 20.44 17.55 15.55 ],[5.22 5.22 7.22 7.22 5.22 ],[1 1 1 "
	      "]);\npatch([17.55 24.44 22.44 20.44 18.44 15.55 17.55 ],[3.22 3.22 5.22 3.22 5.22 5.22 3.22 ],[0.931 0.946 0.97"
	      "3 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');por"
	      "t_label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');"
	    }
	    Block {
	      BlockType		      Reference
	      Name		      "b[7]"
	      SID		      "195"
	      Ports		      [1, 1]
	      Position		      [135, 383, 175, 397]
	      LibraryVersion	      "1.2"
	      SourceBlock	      "xbsIndex_r4/Slice"
	      SourceType	      "Xilinx Bit Slice Extractor Block"
	      infoedit		      "Extracts a given range of bits from each input sample and presents it at the output.  The outp"
	      "ut type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.<br"
	      "><br>Hardware notes: In hardware this block costs nothing."
	      nbits		      "1"
	      boolean_output	      on
	      mode		      "Lower Bit Location + Width"
	      bit1		      "0"
	      base1		      "MSB of Input"
	      bit0		      "7"
	      base0		      "LSB of Input"
	      dbl_ovrd		      off
	      has_advanced_control    "0"
	      sggui_pos		      "20,20,449,398"
	      block_type	      "slice"
	      block_version	      "VER_STRING_GOES_HERE"
	      sg_icon_stat	      "40,14,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]"
	      sg_mask_display	      "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 14 14 0 ],[0.77 0"
	      ".82 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 14 14 0 ]);\npatch([15.55 18.44 20.44 22.44 24.44 20.44 17.55 15.55 ],[9"
	      ".22 9.22 11.22 9.22 11.22 11.22 11.22 9.22 ],[1 1 1 ]);\npatch([17.55 20.44 18.44 15.55 17.55 ],[7.22 7.22 9.22"
	      " 9.22 7.22 ],[0.931 0.946 0.973 ]);\npatch([15.55 18.44 20.44 17.55 15.55 ],[5.22 5.22 7.22 7.22 5.22 ],[1 1 1 "
	      "]);\npatch([17.55 24.44 22.44 20.44 18.44 15.55 17.55 ],[3.22 3.22 5.22 3.22 5.22 5.22 3.22 ],[0.931 0.946 0.97"
	      "3 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');por"
	      "t_label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');"
	    }
	    Line {
	      SrcBlock		      "b[1]  "
	      SrcPort		      1
	      DstBlock		      "Goto14"
	      DstPort		      1
	    }
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	  ownership		  "Locally owned and initialized"
	  explicit_data_type	  on
	  gui_display_data_type	  "Fixed-point"
	  arith_type		  "Unsigned"
	  n_bits		  "32"
	  bin_pt		  "0"
	  preci_type		  "Single"
	  dbl_ovrd		  off
	  xl_use_area		  off
	  xl_area		  "[0,0,0,0,0,0,0]"
	  has_advanced_control	  "0"
	  sggui_pos		  "-1,-1,-1,-1"
	  block_type		  "toreg"
	  sg_icon_stat		  "60,56,2,1,white,blue,0,10ab453e,right,,[ ],[ ]"
	  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 0 ],[0 0 56 56 0 ],[0.77 0.82 0.91"
	  " ]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\npatch([12.2 23.76 31.76 39.76 47.76 31.76 20.2 12.2 ],[36.88 36.88 44.8"
	  "8 36.88 44.88 44.88 44.88 36.88 ],[1 1 1 ]);\npatch([20.2 31.76 23.76 12.2 20.2 ],[28.88 28.88 36.88 36.88 28.88 ],"
	  "[0.931 0.946 0.973 ]);\npatch([12.2 23.76 31.76 20.2 12.2 ],[20.88 20.88 28.88 28.88 20.88 ],[1 1 1 ]);\npatch([20."
	  "2 47.76 39.76 31.76 23.76 12.2 20.2 ],[12.88 12.88 20.88 12.88 20.88 20.88 12.88 ],[0.931 0.946 0.973 ]);\nfprintf("
	  "'','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'di"
	  "n');\ncolor('black');port_label('input',2,'en');\ncolor('black');port_label('output',1,'dout');\nfprintf('','COMMEN"
	  "T: end icon text');"
	}
	Block {
	  BlockType		  Reference
	  Name			  "To Register3"
	  SID			  "152"
	  Ports			  [2, 1]
	  Position		  [1170, 322, 1230, 378]
	  AttributesFormatString  "<< %<shared_memory_name> >>"
	  LibraryVersion	  "1.2"
	  SourceBlock		  "xbsIndex_r4/To Register"
	  SourceType		  "Xilinx Shared Memory Based To Register Block"
	  infoedit		  "Register block that writes data to a shared memory register.  Delay of one sample period."
	  shared_memory_name	  "'SYSTEM_TIME_USEC_LSB'"
	  init			  "0"
	  ownership		  "Locally owned and initialized"
	  explicit_data_type	  on
	  gui_display_data_type	  "Fixed-point"
	  arith_type		  "Unsigned"
	  n_bits		  "32"
	  bin_pt		  "0"
	  preci_type		  "Single"
	  dbl_ovrd		  off
	  xl_use_area		  off
	  xl_area		  "[0,0,0,0,0,0,0]"
	  has_advanced_control	  "0"
	  sggui_pos		  "-1,-1,-1,-1"
	  block_type		  "toreg"
	  sg_icon_stat		  "60,56,2,1,white,blue,0,10ab453e,right,,[ ],[ ]"
	  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 0 ],[0 0 56 56 0 ],[0.77 0.82 0.91"
	  " ]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\npatch([12.2 23.76 31.76 39.76 47.76 31.76 20.2 12.2 ],[36.88 36.88 44.8"
	  "8 36.88 44.88 44.88 44.88 36.88 ],[1 1 1 ]);\npatch([20.2 31.76 23.76 12.2 20.2 ],[28.88 28.88 36.88 36.88 28.88 ],"
	  "[0.931 0.946 0.973 ]);\npatch([12.2 23.76 31.76 20.2 12.2 ],[20.88 20.88 28.88 28.88 20.88 ],[1 1 1 ]);\npatch([20."
	  "2 47.76 39.76 31.76 23.76 12.2 20.2 ],[12.88 12.88 20.88 12.88 20.88 20.88 12.88 ],[0.931 0.946 0.973 ]);\nfprintf("
	  "'','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'di"
	  "n');\ncolor('black');port_label('input',2,'en');\ncolor('black');port_label('output',1,'dout');\nfprintf('','COMMEN"
	  "T: end icon text');"
	}
	Block {
	  BlockType		  Reference
	  Name			  "To Register4"
	  SID			  "153"
	  Ports			  [2, 1]
	  Position		  [1170, 417, 1230, 473]
	  AttributesFormatString  "<< %<shared_memory_name> >>"
	  LibraryVersion	  "1.2"
	  SourceBlock		  "xbsIndex_r4/To Register"
	  SourceType		  "Xilinx Shared Memory Based To Register Block"
	  infoedit		  "Register block that writes data to a shared memory register.  Delay of one sample period."
	  shared_memory_name	  "'SYSTEM_TIME_USEC_MSB'"
	  init			  "0"
	  ownership		  "Locally owned and initialized"
	  explicit_data_type	  on
	  gui_display_data_type	  "Fixed-point"
	  arith_type		  "Unsigned"
	  n_bits		  "32"
	  bin_pt		  "0"
	  preci_type		  "Single"
	  dbl_ovrd		  off
	  xl_use_area		  off
	  xl_area		  "[0,0,0,0,0,0,0]"
	  has_advanced_control	  "0"
	  sggui_pos		  "-1,-1,-1,-1"
	  block_type		  "toreg"
	  sg_icon_stat		  "60,56,2,1,white,blue,0,10ab453e,right,,[ ],[ ]"
	  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 0 ],[0 0 56 56 0 ],[0.77 0.82 0.91"
	  " ]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\npatch([12.2 23.76 31.76 39.76 47.76 31.76 20.2 12.2 ],[36.88 36.88 44.8"
	  "8 36.88 44.88 44.88 44.88 36.88 ],[1 1 1 ]);\npatch([20.2 31.76 23.76 12.2 20.2 ],[28.88 28.88 36.88 36.88 28.88 ],"
	  "[0.931 0.946 0.973 ]);\npatch([12.2 23.76 31.76 20.2 12.2 ],[20.88 20.88 28.88 28.88 20.88 ],[1 1 1 ]);\npatch([20."
	  "2 47.76 39.76 31.76 23.76 12.2 20.2 ],[12.88 12.88 20.88 12.88 20.88 20.88 12.88 ],[0.931 0.946 0.973 ]);\nfprintf("
	  "'','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'di"
	  "n');\ncolor('black');port_label('input',2,'en');\ncolor('black');port_label('output',1,'dout');\nfprintf('','COMMEN"
	  "T: end icon text');"
	}
	Line {
	  SrcBlock		  "32LSB"
	  SrcPort		  1
	  DstBlock		  "To Register1"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "Constant5"
	  SrcPort		  1
	  DstBlock		  "To Register1"
	  DstPort		  2
	}
	Line {
	  SrcBlock		  "32MSB"
	  SrcPort		  1
	  DstBlock		  "To Register2"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "Constant6"
	  SrcPort		  1
	  DstBlock		  "To Register2"
	  DstPort		  2
	}
	Line {
	  SrcBlock		  "From"
	  SrcPort		  1
	  DstBlock		  "Register1"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "Register1"
	  SrcPort		  1
	  Points		  [30, 0]
	  Branch {
	    DstBlock		    "32LSB"
	    DstPort		    1
	  }
	  Branch {
	    Points		    [0, 95]
	    DstBlock		    "32MSB"
	    DstPort		    1
	  }
	}
	Line {
	  SrcBlock		  "To Register1"
	  SrcPort		  1
	  DstBlock		  "Terminator2"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "To Register2"
	  SrcPort		  1
	  DstBlock		  "Terminator3"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "From Register2"
	  SrcPort		  1
	  DstBlock		  "Register28"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "From Register3"
	  SrcPort		  1
	  DstBlock		  "Register27"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "Register27"
	  SrcPort		  1
	  DstBlock		  "Goto4"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "Register28"
	  SrcPort		  1
	  DstBlock		  "Goto17"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "32LSB1"
	  SrcPort		  1
	  DstBlock		  "To Register3"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "Constant1"
	  SrcPort		  1
	  DstBlock		  "To Register3"
	  DstPort		  2
	}
	Line {
	  SrcBlock		  "32MSB1"
	  SrcPort		  1
	  DstBlock		  "To Register4"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "Constant2"
	  SrcPort		  1
	  DstBlock		  "To Register4"
	  DstPort		  2
	}
	Line {
	  SrcBlock		  "From1"
	  SrcPort		  1
	  DstBlock		  "Register2"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "Register2"
	  SrcPort		  1
	  Points		  [30, 0]
	  Branch {
	    Points		    [0, 95]
	    DstBlock		    "32MSB1"
	    DstPort		    1
	  }
	  Branch {
	    DstBlock		    "32LSB1"
	    DstPort		    1
	  }
	}
	Line {
	  SrcBlock		  "To Register3"
	  SrcPort		  1
	  DstBlock		  "Terminator1"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "To Register4"
	  SrcPort		  1
	  DstBlock		  "Terminator4"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "From Register1"
	  SrcPort		  1
	  DstBlock		  "Register36"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "Register36"
	  SrcPort		  1
	  DstBlock		  "Ctrl Bits"
	  DstPort		  1
	}
      }
    }
    Block {
      BlockType		      Reference
      Name		      "SYSTEM_TIME_LSB"
      SID		      "134"
      Ports		      [1, 1]
      Position		      [1055, 510, 1115, 530]
      LibraryVersion	      "1.2"
      SourceBlock	      "xbsIndex_r4/Gateway Out"
      SourceType	      "Xilinx Gateway Out Block"
      infoedit		      "Gateway out block.  Converts Xilinx fixed-point or floating-point type inputs into ouputs of ty"
      "pe Simulink integer, single, double, or fixed-point.<br><br>Hardware notes:  In hardware these blocks become top"
      " level output ports or are discarded, depending on how they are configured."
      inherit_from_input      off
      hdl_port		      on
      timing_constraint	      "None"
      locs_specified	      off
      LOCs		      "{}"
      UseAsDAC		      off
      DACChannel	      "'1'"
      xl_use_area	      off
      xl_area		      "[0,0,0,0,0,0,0]"
      has_advanced_control    "0"
      sggui_pos		      "-1,-1,-1,-1"
      block_type	      "gatewayout"
      sg_icon_stat	      "60,20,1,1,white,yellow,1,cc31b7ac,right,,[ ],[ ]"
      sg_mask_display	      "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 0 ],[0 0 20 20 0 ],[0.95 0."
      "93 0.65 ]);\nplot([0 60 60 0 0 ],[0 0 20 20 0 ]);\npatch([25.55 28.44 30.44 32.44 34.44 30.44 27.55 25.55 ],[12."
      "22 12.22 14.22 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([27.55 30.44 28.44 25.55 27.55 ],[10.22 10.22 1"
      "2.22 12.22 10.22 ],[0.985 0.979 0.895 ]);\npatch([25.55 28.44 30.44 27.55 25.55 ],[8.22 8.22 10.22 10.22 8.22 ],"
      "[1 1 1 ]);\npatch([27.55 34.44 32.44 30.44 28.44 25.55 27.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.985 0.97"
      "9 0.895 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');"
      "port_label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt}\\bf Out ','texmode','on');\nf"
      "printf('','COMMENT: end icon text');"
    }
    Block {
      BlockType		      Reference
      Name		      "SYSTEM_TIME_MSB"
      SID		      "135"
      Ports		      [1, 1]
      Position		      [1055, 550, 1115, 570]
      LibraryVersion	      "1.2"
      SourceBlock	      "xbsIndex_r4/Gateway Out"
      SourceType	      "Xilinx Gateway Out Block"
      infoedit		      "Gateway out block.  Converts Xilinx fixed-point or floating-point type inputs into ouputs of ty"
      "pe Simulink integer, single, double, or fixed-point.<br><br>Hardware notes:  In hardware these blocks become top"
      " level output ports or are discarded, depending on how they are configured."
      inherit_from_input      off
      hdl_port		      on
      timing_constraint	      "None"
      locs_specified	      off
      LOCs		      "{}"
      UseAsDAC		      off
      DACChannel	      "'1'"
      xl_use_area	      off
      xl_area		      "[0,0,0,0,0,0,0]"
      has_advanced_control    "0"
      sggui_pos		      "-1,-1,-1,-1"
      block_type	      "gatewayout"
      sg_icon_stat	      "60,20,1,1,white,yellow,1,cc31b7ac,right,,[ ],[ ]"
      sg_mask_display	      "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 0 ],[0 0 20 20 0 ],[0.95 0."
      "93 0.65 ]);\nplot([0 60 60 0 0 ],[0 0 20 20 0 ]);\npatch([25.55 28.44 30.44 32.44 34.44 30.44 27.55 25.55 ],[12."
      "22 12.22 14.22 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([27.55 30.44 28.44 25.55 27.55 ],[10.22 10.22 1"
      "2.22 12.22 10.22 ],[0.985 0.979 0.895 ]);\npatch([25.55 28.44 30.44 27.55 25.55 ],[8.22 8.22 10.22 10.22 8.22 ],"
      "[1 1 1 ]);\npatch([27.55 34.44 32.44 30.44 28.44 25.55 27.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.985 0.97"
      "9 0.895 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');"
      "port_label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt}\\bf Out ','texmode','on');\nf"
      "printf('','COMMENT: end icon text');"
    }
    Block {
      BlockType		      Scope
      Name		      "Scope"
      SID		      "220"
      Ports		      [3]
      Position		      [1245, 401, 1280, 519]
      ZOrder		      -16
      Floating		      off
      Location		      [14, 559, 672, 1553]
      Open		      off
      NumInputPorts	      "3"
      ZoomMode		      "xonly"
      List {
	ListType		AxesTitles
	axes1			"%<SignalLabel>"
	axes2			"%<SignalLabel>"
	axes3			"%<SignalLabel>"
      }
      List {
	ListType		ScopeGraphics
	FigureColor		"[0.5 0.5 0.5]"
	AxesColor		"[0 0 0]"
	AxesTickColor		"[1 1 1]"
	LineColors		"[1 1 0;1 0 1;0 1 1;1 0 0;0 1 0;0 0 1]"
	LineStyles		"-|-|-|-|-|-"
	LineWidths		"[0.5 0.5 0.5 0.5 0.5 0.5]"
	MarkerStyles		"none|none|none|none|none|none"
      }
      YMin		      "-5~-5~-5"
      YMax		      "5~5~5"
      SaveName		      "ScopeData2"
      DataFormat	      "StructureWithTime"
      SampleTime	      "0"
      MaskIconFrame	      on
      MaskIconOpaque	      on
      MaskIconRotate	      "none"
      MaskPortRotate	      "default"
      MaskIconUnits	      "autoscale"
    }
    Block {
      BlockType		      Reference
      Name		      "System Time\n64-bit Counter"
      SID		      "11"
      Ports		      [2, 1]
      Position		      [650, 70, 710, 125]
      NamePlacement	      "alternate"
      LibraryVersion	      "1.2"
      SourceBlock	      "xbsIndex_r4/Counter"
      SourceType	      "Xilinx Counter Block"
      infoedit		      "Hardware notes: Free running counters are the least expensive in hardware.  A count limited cou"
      "nter is implemented by combining a counter with a comparator."
      cnt_type		      "Free Running"
      cnt_to		      "Inf"
      operation		      "Up"
      start_count	      "0"
      cnt_by_val	      "1"
      arith_type	      "Unsigned"
      n_bits		      "64"
      bin_pt		      "0"
      load_pin		      off
      rst		      on
      en		      on
      explicit_period	      "off"
      period		      "1"
      dbl_ovrd		      off
      use_behavioral_HDL      off
      implementation	      "Fabric"
      xl_use_area	      off
      xl_area		      "[0,0,0,0,0,0,0]"
      has_advanced_control    "0"
      sggui_pos		      "-1,-1,-1,-1"
      block_type	      "counter"
      sg_icon_stat	      "60,55,2,1,white,blue,0,ae3608d6,right,,[ ],[ ]"
      sg_mask_display	      "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 0 ],[0 0 55 55 0 ],[0.77 0."
      "82 0.91 ]);\nplot([0 60 60 0 0 ],[0 0 55 55 0 ]);\npatch([14.425 24.54 31.54 38.54 45.54 31.54 21.425 14.425 ],["
      "34.77 34.77 41.77 34.77 41.77 41.77 41.77 34.77 ],[1 1 1 ]);\npatch([21.425 31.54 24.54 14.425 21.425 ],[27.77 2"
      "7.77 34.77 34.77 27.77 ],[0.931 0.946 0.973 ]);\npatch([14.425 24.54 31.54 21.425 14.425 ],[20.77 20.77 27.77 27"
      ".77 20.77 ],[1 1 1 ]);\npatch([21.425 45.54 38.54 31.54 24.54 14.425 21.425 ],[13.77 13.77 20.77 13.77 20.77 20."
      "77 13.77 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon te"
      "xt');\ncolor('black');port_label('input',1,'rst');\ncolor('black');port_label('input',2,'en');\n\ncolor('black')"
      ";disp('{\\fontsize{14}\\bf++}','texmode','on');\nfprintf('','COMMENT: end icon text');"
    }
    Block {
      BlockType		      Reference
      Name		      "TIME_USEC_FRAC"
      SID		      "217"
      Ports		      [1, 1]
      Position		      [1055, 635, 1115, 655]
      LibraryVersion	      "1.2"
      SourceBlock	      "xbsIndex_r4/Gateway Out"
      SourceType	      "Xilinx Gateway Out Block"
      infoedit		      "Gateway out block.  Converts Xilinx fixed-point or floating-point type inputs into ouputs of ty"
      "pe Simulink integer, single, double, or fixed-point.<br><br>Hardware notes:  In hardware these blocks become top"
      " level output ports or are discarded, depending on how they are configured."
      inherit_from_input      off
      hdl_port		      on
      timing_constraint	      "None"
      locs_specified	      off
      LOCs		      "{}"
      UseAsDAC		      off
      DACChannel	      "'1'"
      xl_use_area	      off
      xl_area		      "[0,0,0,0,0,0,0]"
      has_advanced_control    "0"
      sggui_pos		      "-1,-1,-1,-1"
      block_type	      "gatewayout"
      sg_icon_stat	      "60,20,1,1,white,yellow,1,cc31b7ac,right,,[ ],[ ]"
      sg_mask_display	      "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 0 ],[0 0 20 20 0 ],[0.95 0."
      "93 0.65 ]);\nplot([0 60 60 0 0 ],[0 0 20 20 0 ]);\npatch([25.55 28.44 30.44 32.44 34.44 30.44 27.55 25.55 ],[12."
      "22 12.22 14.22 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([27.55 30.44 28.44 25.55 27.55 ],[10.22 10.22 1"
      "2.22 12.22 10.22 ],[0.985 0.979 0.895 ]);\npatch([25.55 28.44 30.44 27.55 25.55 ],[8.22 8.22 10.22 10.22 8.22 ],"
      "[1 1 1 ]);\npatch([27.55 34.44 32.44 30.44 28.44 25.55 27.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.985 0.97"
      "9 0.895 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');"
      "port_label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt}\\bf Out ','texmode','on');\nf"
      "printf('','COMMENT: end icon text');"
    }
    Block {
      BlockType		      Reference
      Name		      "USEC_PULSE"
      SID		      "211"
      Ports		      [1, 1]
      Position		      [1055, 335, 1115, 355]
      LibraryVersion	      "1.2"
      SourceBlock	      "xbsIndex_r4/Gateway Out"
      SourceType	      "Xilinx Gateway Out Block"
      infoedit		      "Gateway out block.  Converts Xilinx fixed-point or floating-point type inputs into ouputs of ty"
      "pe Simulink integer, single, double, or fixed-point.<br><br>Hardware notes:  In hardware these blocks become top"
      " level output ports or are discarded, depending on how they are configured."
      inherit_from_input      off
      hdl_port		      on
      timing_constraint	      "None"
      locs_specified	      off
      LOCs		      "{}"
      UseAsDAC		      off
      DACChannel	      "'1'"
      xl_use_area	      off
      xl_area		      "[0,0,0,0,0,0,0]"
      has_advanced_control    "0"
      sggui_pos		      "-1,-1,-1,-1"
      block_type	      "gatewayout"
      sg_icon_stat	      "60,20,1,1,white,yellow,1,cc31b7ac,right,,[ ],[ ]"
      sg_mask_display	      "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 0 ],[0 0 20 20 0 ],[0.95 0."
      "93 0.65 ]);\nplot([0 60 60 0 0 ],[0 0 20 20 0 ]);\npatch([25.55 28.44 30.44 32.44 34.44 30.44 27.55 25.55 ],[12."
      "22 12.22 14.22 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([27.55 30.44 28.44 25.55 27.55 ],[10.22 10.22 1"
      "2.22 12.22 10.22 ],[0.985 0.979 0.895 ]);\npatch([25.55 28.44 30.44 27.55 25.55 ],[8.22 8.22 10.22 10.22 8.22 ],"
      "[1 1 1 ]);\npatch([27.55 34.44 32.44 30.44 28.44 25.55 27.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.985 0.97"
      "9 0.895 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');"
      "port_label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt}\\bf Out ','texmode','on');\nf"
      "printf('','COMMENT: end icon text');"
    }
    Block {
      BlockType		      SubSystem
      Name		      "usec Pulse"
      SID		      "24"
      Ports		      [0, 2]
      Position		      [370, 100, 470, 140]
      MinAlgLoopOccurrences   off
      PropExecContextOutsideSubsystem off
      RTWSystemCode	      "Auto"
      FunctionWithSeparateData off
      Opaque		      off
      RequestExecContextInheritance off
      MaskHideContents	      off
      System {
	Name			"usec Pulse"
	Location		[2, 94, 1918, 1115]
	Open			off
	ModelBrowserVisibility	off
	ModelBrowserWidth	200
	ScreenColor		"white"
	PaperOrientation	"landscape"
	PaperPositionMode	"auto"
	PaperType		"usletter"
	PaperUnits		"inches"
	TiledPaperMargins	[0.500000, 0.500000, 0.500000, 0.500000]
	TiledPageScale		1
	ShowPageBoundaries	off
	ZoomFactor		"156"
	Block {
	  BlockType		  Reference
	  Name			  "Clk->usec"
	  SID			  "26"
	  Ports			  [1, 1]
	  Position		  [295, 198, 360, 242]
	  NamePlacement		  "alternate"
	  LibraryVersion	  "1.2"
	  SourceBlock		  "xbsIndex_r4/Counter"
	  SourceType		  "Xilinx Counter Block"
	  infoedit		  "Hardware notes: Free running counters are the least expensive in hardware.  A count limited counter is"
	  " implemented by combining a counter with a comparator."
	  cnt_type		  "Free Running"
	  cnt_to		  "159"
	  operation		  "Up"
	  start_count		  "0"
	  cnt_by_val		  "1"
	  arith_type		  "Unsigned"
	  n_bits		  "8"
	  bin_pt		  "0"
	  load_pin		  off
	  rst			  on
	  en			  off
	  explicit_period	  "off"
	  period		  "1"
	  dbl_ovrd		  off
	  use_behavioral_HDL	  off
	  implementation	  "Fabric"
	  xl_use_area		  off
	  xl_area		  "[0,0,0,0,0,0,0]"
	  has_advanced_control	  "0"
	  sggui_pos		  "-1,-1,-1,-1"
	  block_type		  "counter"
	  sg_icon_stat		  "65,44,1,1,white,blue,0,803eba70,right,,[ ],[ ]"
	  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 65 65 0 0 ],[0 0 44 44 0 ],[0.77 0.82 0.91"
	  " ]);\nplot([0 65 65 0 0 ],[0 0 44 44 0 ]);\npatch([18.65 27.32 33.32 39.32 45.32 33.32 24.65 18.65 ],[28.66 28.66 3"
	  "4.66 28.66 34.66 34.66 34.66 28.66 ],[1 1 1 ]);\npatch([24.65 33.32 27.32 18.65 24.65 ],[22.66 22.66 28.66 28.66 22"
	  ".66 ],[0.931 0.946 0.973 ]);\npatch([18.65 27.32 33.32 24.65 18.65 ],[16.66 16.66 22.66 22.66 16.66 ],[1 1 1 ]);\np"
	  "atch([24.65 45.32 39.32 33.32 27.32 18.65 24.65 ],[10.66 10.66 16.66 10.66 16.66 16.66 10.66 ],[0.931 0.946 0.973 ]"
	  ");\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('"
	  "input',1,'rst');\n\ncolor('black');disp('{\\fontsize{14}\\bf++}','texmode','on');\nfprintf('','COMMENT: end icon te"
	  "xt');"
	}
	Block {
	  BlockType		  Reference
	  Name			  "Constant1"
	  SID			  "27"
	  Ports			  [0, 1]
	  Position		  [320, 254, 340, 276]
	  ShowName		  off
	  LibraryVersion	  "1.2"
	  SourceBlock		  "xbsIndex_r4/Constant"
	  SourceType		  "Xilinx Constant Block Block"
	  const			  "159"
	  gui_display_data_type	  "Fixed-point"
	  arith_type		  "Unsigned"
	  n_bits		  "8"
	  bin_pt		  "0"
	  preci_type		  "Single"
	  exp_width		  "8"
	  frac_width		  "24"
	  explicit_period	  on
	  period		  "1"
	  dsp48_infoedit	  "The use of this block for DSP48 instructions is deprecated.  Please use the Opmode block."
	  equ			  "P=C"
	  opselect		  "C"
	  inp2			  "PCIN>>17"
	  opr			  "+"
	  inp1			  "P"
	  carry			  "CIN"
	  dbl_ovrd		  off
	  has_advanced_control	  "0"
	  sggui_pos		  "-1,-1,-1,-1"
	  block_type		  "constant"
	  block_version		  "8.2.02"
	  sg_icon_stat		  "20,22,0,1,white,blue,0,04b97b88,right,,[ ],[ ]"
	  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 20 20 0 0 ],[0 0 22 22 0 ],[0.77 0.82 0.91"
	  " ]);\nplot([0 20 20 0 0 ],[0 0 22 22 0 ]);\npatch([5.55 8.44 10.44 12.44 14.44 10.44 7.55 5.55 ],[13.22 13.22 15.22"
	  " 13.22 15.22 15.22 15.22 13.22 ],[1 1 1 ]);\npatch([7.55 10.44 8.44 5.55 7.55 ],[11.22 11.22 13.22 13.22 11.22 ],[0"
	  ".931 0.946 0.973 ]);\npatch([5.55 8.44 10.44 7.55 5.55 ],[9.22 9.22 11.22 11.22 9.22 ],[1 1 1 ]);\npatch([7.55 14.4"
	  "4 12.44 10.44 8.44 5.55 7.55 ],[7.22 7.22 9.22 7.22 9.22 9.22 7.22 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: e"
	  "nd icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'159');\nfprintf"
	  "('','COMMENT: end icon text');"
	}
	Block {
	  BlockType		  Reference
	  Name			  "Relational"
	  SID			  "29"
	  Ports			  [2, 1]
	  Position		  [405, 207, 460, 263]
	  ShowName		  off
	  LibraryVersion	  "1.2"
	  SourceBlock		  "xbsIndex_r4/Relational"
	  SourceType		  "Xilinx Arithmetic Relational Operator Block"
	  mode			  "a=b"
	  en			  off
	  latency		  "0"
	  dbl_ovrd		  off
	  xl_use_area		  off
	  xl_area		  "[0,0,0,0,0,0,0]"
	  has_advanced_control	  "0"
	  sggui_pos		  "-1,-1,-1,-1"
	  block_type		  "relational"
	  sg_icon_stat		  "55,56,2,1,white,blue,0,2a81ff49,right,,[ ],[ ]"
	  sg_mask_display	  "fprintf('','COMMENT: begin icon graphics');\npatch([0 55 55 0 0 ],[0 0 56 56 0 ],[0.77 0.82 0.91"
	  " ]);\nplot([0 55 55 0 0 ],[0 0 56 56 0 ]);\npatch([11.425 21.54 28.54 35.54 42.54 28.54 18.425 11.425 ],[35.77 35.7"
	  "7 42.77 35.77 42.77 42.77 42.77 35.77 ],[1 1 1 ]);\npatch([18.425 28.54 21.54 11.425 18.425 ],[28.77 28.77 35.77 35"
	  ".77 28.77 ],[0.931 0.946 0.973 ]);\npatch([11.425 21.54 28.54 18.425 11.425 ],[21.77 21.77 28.77 28.77 21.77 ],[1 1"
	  " 1 ]);\npatch([18.425 42.54 35.54 28.54 21.54 11.425 18.425 ],[14.77 14.77 21.77 14.77 21.77 21.77 14.77 ],[0.931 0"
	  ".946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');"
	  "port_label('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('output',1,'\\bfa "
	  "= b','texmode','on');\ncolor('black');disp(' ');\nfprintf('','COMMENT: end icon text');"
	}
	Block {
	  BlockType		  Outport
	  Name			  "uSec"
	  SID			  "30"
	  Position		  [530, 228, 560, 242]
	  IconDisplay		  "Port number"
	}
	Block {
	  BlockType		  Outport
	  Name			  "uSec Fractional Part"
	  SID			  "216"
	  Position		  [535, 313, 565, 327]
	  Port			  "2"
	  IconDisplay		  "Port number"
	}
	Line {
	  SrcBlock		  "Clk->usec"
	  SrcPort		  1
	  Points		  [15, 0]
	  Branch {
	    DstBlock		    "Relational"
	    DstPort		    1
	  }
	  Branch {
	    Points		    [0, 100]
	    DstBlock		    "uSec Fractional Part"
	    DstPort		    1
	  }
	}
	Line {
	  SrcBlock		  "Constant1"
	  SrcPort		  1
	  Points		  [20, 0; 0, -15]
	  DstBlock		  "Relational"
	  DstPort		  2
	}
	Line {
	  SrcBlock		  "Relational"
	  SrcPort		  1
	  Points		  [35, 0]
	  Branch {
	    DstBlock		    "uSec"
	    DstPort		    1
	  }
	  Branch {
	    Points		    [0, -75; -275, 0; 0, 60]
	    DstBlock		    "Clk->usec"
	    DstPort		    1
	  }
	}
      }
    }
    Line {
      SrcBlock		      "32LSB"
      SrcPort		      1
      DstBlock		      "Register2"
      DstPort		      1
    }
    Line {
      SrcBlock		      "32MSB"
      SrcPort		      1
      DstBlock		      "Register1"
      DstPort		      1
    }
    Line {
      SrcBlock		      "Register"
      SrcPort		      1
      DstBlock		      "MAC_TIME_MSB"
      DstPort		      1
    }
    Line {
      SrcBlock		      "Register1"
      SrcPort		      1
      DstBlock		      "Register"
      DstPort		      1
    }
    Line {
      SrcBlock		      "Register2"
      SrcPort		      1
      DstBlock		      "Register3"
      DstPort		      1
    }
    Line {
      SrcBlock		      "Register3"
      SrcPort		      1
      DstBlock		      "MAC_TIME_LSB"
      DstPort		      1
    }
    Line {
      SrcBlock		      "System Time\n64-bit Counter"
      SrcPort		      1
      DstBlock		      "Register50"
      DstPort		      1
    }
    Line {
      SrcBlock		      "usec Pulse"
      SrcPort		      1
      Points		      [60, 0]
      Branch {
	DstBlock		"System Time\n64-bit Counter"
	DstPort			2
      }
      Branch {
	Points			[0, 145]
	Branch {
	  DstBlock		  "Logical"
	  DstPort		  2
	}
	Branch {
	  Points		  [0, 90]
	  DstBlock		  "Register9"
	  DstPort		  1
	}
      }
    }
    Line {
      SrcBlock		      "Posedge"
      SrcPort		      1
      Points		      [135, 0]
      Branch {
	Points			[0, 60]
	DstBlock		"Logical"
	DstPort			1
      }
      Branch {
	DstBlock		"MAC Time\n64-bit Counter"
	DstPort			1
      }
    }
    Line {
      SrcBlock		      "From5"
      SrcPort		      1
      DstBlock		      "Posedge"
      DstPort		      1
    }
    Line {
      SrcBlock		      "Concat"
      SrcPort		      1
      DstBlock		      "MAC Time\n64-bit Counter"
      DstPort		      2
    }
    Line {
      SrcBlock		      "From1"
      SrcPort		      1
      DstBlock		      "Concat"
      DstPort		      1
    }
    Line {
      SrcBlock		      "From19"
      SrcPort		      1
      DstBlock		      "Concat"
      DstPort		      2
    }
    Line {
      SrcBlock		      "Logical"
      SrcPort		      1
      DstBlock		      "MAC Time\n64-bit Counter"
      DstPort		      3
    }
    Line {
      SrcBlock		      "MAC Time\n64-bit Counter"
      SrcPort		      1
      DstBlock		      "Register8"
      DstPort		      1
    }
    Line {
      SrcBlock		      "From3"
      SrcPort		      1
      Points		      [35, 0]
      Branch {
	DstBlock		"32LSB"
	DstPort			1
      }
      Branch {
	Points			[0, 40]
	DstBlock		"32MSB"
	DstPort			1
      }
    }
    Line {
      SrcBlock		      "32LSB1"
      SrcPort		      1
      DstBlock		      "Register6"
      DstPort		      1
    }
    Line {
      SrcBlock		      "32MSB1"
      SrcPort		      1
      DstBlock		      "Register5"
      DstPort		      1
    }
    Line {
      SrcBlock		      "Register4"
      SrcPort		      1
      DstBlock		      "SYSTEM_TIME_MSB"
      DstPort		      1
    }
    Line {
      SrcBlock		      "Register5"
      SrcPort		      1
      DstBlock		      "Register4"
      DstPort		      1
    }
    Line {
      SrcBlock		      "Register6"
      SrcPort		      1
      DstBlock		      "Register7"
      DstPort		      1
    }
    Line {
      SrcBlock		      "Register7"
      SrcPort		      1
      DstBlock		      "SYSTEM_TIME_LSB"
      DstPort		      1
    }
    Line {
      SrcBlock		      "From4"
      SrcPort		      1
      Points		      [35, 0]
      Branch {
	Points			[0, 40]
	DstBlock		"32MSB1"
	DstPort			1
      }
      Branch {
	DstBlock		"32LSB1"
	DstPort			1
      }
    }
    Line {
      SrcBlock		      "Register50"
      SrcPort		      1
      DstBlock		      "Goto"
      DstPort		      1
    }
    Line {
      SrcBlock		      "Register8"
      SrcPort		      1
      DstBlock		      "Goto1"
      DstPort		      1
    }
    Line {
      SrcBlock		      "From2"
      SrcPort		      1
      DstBlock		      "System Time\n64-bit Counter"
      DstPort		      1
    }
    Line {
      SrcBlock		      "Register9"
      SrcPort		      1
      DstBlock		      "Register10"
      DstPort		      1
    }
    Line {
      SrcBlock		      "Register10"
      SrcPort		      1
      DstBlock		      "USEC_PULSE"
      DstPort		      1
    }
    Line {
      SrcBlock		      "usec Pulse"
      SrcPort		      2
      Points		      [45, 0; 0, 515]
      DstBlock		      "Register13"
      DstPort		      1
    }
    Line {
      SrcBlock		      "Register11"
      SrcPort		      1
      DstBlock		      "Register12"
      DstPort		      1
    }
    Line {
      SrcBlock		      "Register12"
      SrcPort		      1
      DstBlock		      "TIME_USEC_FRAC"
      DstPort		      1
    }
    Line {
      SrcBlock		      "MAC_TIME_LSB"
      SrcPort		      1
      DstBlock		      "Scope"
      DstPort		      1
    }
    Line {
      SrcBlock		      "MAC_TIME_MSB"
      SrcPort		      1
      DstBlock		      "Scope"
      DstPort		      2
    }
    Line {
      SrcBlock		      "TIME_USEC_FRAC"
      SrcPort		      1
      Points		      [55, 0; 0, -145]
      DstBlock		      "Scope"
      DstPort		      3
    }
    Line {
      SrcBlock		      "Register13"
      SrcPort		      1
      DstBlock		      "Register11"
      DstPort		      1
    }
    Annotation {
      Name		      "Copyright (c) 2016 Mango Communications, Inc. All rights reserved.\n\nDistributed under the Mango R"
      "eference Design License:\nhttp://mangocomm.com/802.11/license"
      Position		      [257, 516]
      DropShadow	      on
    }
    Annotation {
      Name		      "Critical that the fractional and integer parts of the timestamps\nhave the same latency. Otherwise "
      "consumers will observe a fractional\npart that wraps at a different time than the integer part increments."
      Position		      [956, 698]
    }
  }
}
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